3 bool "Bit-banged ethernet MII management channel support"
5 config MV88E6352_SWITCH
6 bool "Marvell 88E6352 switch support"
9 bool "Ethernet PHY (physical media interface) support"
12 Enable Ethernet PHY (physical media interface) support.
16 config PHY_ADDR_ENABLE
17 bool "Limit phy address"
18 default y if ARCH_SUNXI
20 Select this if you want to control which phy address is used
25 default 1 if ARCH_SUNXI
28 The address of PHY on MII bus. Usually in range of 0 to 31.
32 bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
34 Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
35 This currently supports BCM53125 and similar models.
44 hex "Bitmask of PHY ports"
48 config MV88E61XX_SWITCH
49 bool "Marvell MV88E61xx Ethernet switch PHY support."
53 config MV88E61XX_CPU_PORT
56 config MV88E61XX_PHY_PORTS
57 hex "Bitmask of PHY Ports"
59 config MV88E61XX_FIXED_PORTS
60 hex "Bitmask of PHYless serdes Ports"
62 endif # MV88E61XX_SWITCH
65 bool "Generic 10G PHY support"
67 menuconfig PHY_AQUANTIA
68 bool "Aquantia Ethernet PHYs support"
72 config PHY_AQUANTIA_UPLOAD_FW
73 bool "Aquantia firmware loading support"
74 depends on PHY_AQUANTIA
76 Aquantia PHYs use firmware which can be either loaded automatically
77 from storage directly attached to the phy or loaded by the boot loader
78 via MDIO commands. The firmware is loaded from a file, specified by
79 the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
81 config PHY_AQUANTIA_FW_PART
82 string "Aquantia firmware partition"
83 depends on PHY_AQUANTIA_UPLOAD_FW
85 Partition containing the firmware file.
87 config PHY_AQUANTIA_FW_NAME
88 string "Aquantia firmware filename"
89 depends on PHY_AQUANTIA_UPLOAD_FW
94 bool "Atheros Ethernet PHYs support"
97 bool "Broadcom Ethernet PHYs support"
100 bool "Cortina Ethernet PHYs support"
102 config SYS_CORTINA_NO_FW_UPLOAD
103 bool "Cortina firmware loading support"
104 depends on PHY_CORTINA
106 Cortina phy has provision to store phy firmware in attached dedicated
107 EEPROM. And boards designed with such EEPROM does not require firmware
111 prompt "Location of the Cortina firmware"
112 default SYS_CORTINA_FW_IN_NOR
113 depends on PHY_CORTINA
115 config SYS_CORTINA_FW_IN_MMC
116 bool "Cortina firmware in MMC"
118 config SYS_CORTINA_FW_IN_NAND
119 bool "Cortina firmware in NAND flash"
121 config SYS_CORTINA_FW_IN_NOR
122 bool "Cortina firmware in NOR flash"
124 config SYS_CORTINA_FW_IN_REMOTE
125 bool "Cortina firmware in remote device"
127 config SYS_CORTINA_FW_IN_SPIFLASH
128 bool "Cortina firmware in SPI flash"
132 config CORTINA_FW_ADDR
133 hex "Cortina Firmware Address"
134 depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
137 config CORTINA_FW_LENGTH
138 hex "Cortina Firmware Length"
139 depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
142 config PHY_CORTINA_ACCESS
143 bool "Cortina Access Ethernet PHYs support"
145 depends on CORTINA_NI_ENET
147 Cortina Access Ethernet PHYs init process
150 bool "Davicom Ethernet PHYs support"
153 bool "LSI TruePHY ET1011C support"
156 bool "LXT971 Ethernet PHY support"
159 bool "Marvell Ethernet PHYs support"
162 bool "Amlogic Meson GXL Internal PHY support"
165 bool "Micrel Ethernet PHYs support"
167 Enable support for the GbE PHYs manufactured by Micrel (now
168 a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
169 KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
170 family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
171 KSZ90x1 family support" is selected).
175 config PHY_MICREL_KSZ9021
177 select PHY_MICREL_KSZ90X1
179 config PHY_MICREL_KSZ9031
181 select PHY_MICREL_KSZ90X1
183 config PHY_MICREL_KSZ90X1
184 bool "Micrel KSZ90x1 family support"
187 Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
188 enabled, the extended register read/write for KSZ90x1 PHYs
189 is supported through the 'mdio' command and any RGMII signal
190 delays configured in the device tree will be applied to the
191 PHY during initialization.
193 config PHY_MICREL_KSZ8XXX
194 bool "Micrel KSZ8xxx family support"
196 Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
197 (now a part of Microchip). This includes drivers for the KSZ804,
198 KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
203 bool "Microsemi Corp Ethernet PHYs support"
206 bool "National Semiconductor Ethernet PHYs support"
208 config PHY_NXP_C45_TJA11XX
209 tristate "NXP C45 TJA11XX PHYs"
211 Enable support for NXP C45 TJA11XX PHYs.
212 Currently supports only the TJA1103 PHY.
215 bool "Realtek Ethernet PHYs support"
217 config RTL8211X_PHY_FORCE_MASTER
218 bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
219 depends on PHY_REALTEK
221 Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
222 This can work around link stability and data corruption issues on gigabit
223 links which can occur in slave mode on certain PHYs, e.g. on the
226 Please note that two directly connected devices (i.e. via crossover cable)
227 will not be able to establish a link between each other if they both force
228 master mode. Multiple devices forcing master mode when connected by a
229 network switch do not pose a problem as the switch configures its affected
230 ports into slave mode.
232 This option only affects gigabit links. If you must establish a direct
233 connection between two devices which both force master mode, try forcing
234 the link speed to 100MBit/s.
238 config RTL8211F_PHY_FORCE_EEE_RXC_ON
239 bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
240 depends on PHY_REALTEK
242 The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
243 transitions to/from a lower power consumption level (Low Power Idle
244 mode) based on link utilization. When no packets are being
245 transmitted, the system goes to Low Power Idle mode to save power.
247 Under particular circumstances this setting can cause issues where
248 the PHY is unable to transmit or receive any packet when in LPI mode.
249 The problem is caused when the PHY is configured to stop receiving
250 the xMII clock while it is signaling LPI. For some PHYs the bit
251 configuring this behavior is set by the Linux kernel, causing the
252 issue in U-Boot on reboot if the PHY retains the register value.
254 Default n, which means that the PHY state is not changed. To work
255 around the issues, change this setting to y.
257 config RTL8201F_PHY_S700_RMII_TIMINGS
258 bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
259 depends on PHY_REALTEK
261 This provides an option to configure specific timing requirements (needed
262 for proper PHY operations) for the PHY module present on ACTION SEMI S700
263 based cubieboard7. Exact timing requiremnets seems to be SoC specific
264 (and it's undocumented) that comes from vendor code itself.
267 bool "Microchip(SMSC) Ethernet PHYs support"
269 config PHY_TERANETICS
270 bool "Teranetics Ethernet PHYs support"
273 bool "Texas Instruments Ethernet PHYs support"
275 Adds PHY registration support for TI PHYs.
277 config PHY_TI_DP83867
279 bool "Texas Instruments Ethernet DP83867 PHY support"
281 Adds support for the TI DP83867 1Gbit PHY.
283 config PHY_TI_DP83869
285 bool "Texas Instruments Ethernet DP83869 PHY support"
287 Adds support for the TI DP83869 1Gbit PHY.
289 config PHY_TI_GENERIC
291 bool "Texas Instruments Generic Ethernet PHYs support"
293 Adds support for Generic TI PHYs that don't need special handling but
294 the PHY name is associated with a PHY ID.
297 bool "Vitesse Ethernet PHYs support"
300 bool "Xilinx Ethernet PHYs support"
302 config PHY_XILINX_GMII2RGMII
303 bool "Xilinx GMII to RGMII Ethernet PHYs support"
306 This adds support for Xilinx GMII to RGMII IP core. This IP acts
307 as bridge between MAC connected over GMII and external phy that
308 is connected over RGMII interface.
310 config PHY_ETHERNET_ID
311 bool "Read ethernet PHY id"
313 default y if ZYNQ_GEM
315 Enable this config to read ethernet phy id from the phy node of DT
316 and create a phy device using id.
319 bool "Fixed-Link PHY"
322 Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
323 connection (MII, RGMII, ...).
324 There is nothing like autoneogation and so
325 on, the link is always up with fixed speed and fixed duplex-setting.
326 More information: doc/device-tree-bindings/net/fixed-link.txt
329 bool "NC-SI based PHY"