2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
4 * This driver for AMD PCnet network controllers is derived from the
5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
7 * SPDX-License-Identifier: GPL-2.0+
17 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
19 #define PCNET_DEBUG1(fmt,args...) \
20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
21 #define PCNET_DEBUG2(fmt,args...) \
22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
24 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
25 #error "Macro for PCnet chip version is not defined!"
29 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
33 #define PCNET_LOG_TX_BUFFERS 0
34 #define PCNET_LOG_RX_BUFFERS 2
36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
42 #define PKT_BUF_SZ 1544
44 /* The PCNET Rx and Tx ring descriptors. */
45 struct pcnet_rx_head {
53 struct pcnet_tx_head {
61 /* The PCNET 32-Bit initialization block, described in databook. */
62 struct pcnet_init_block {
68 /* Receive and transmit ring base, along with extra bits. */
74 typedef struct pcnet_priv {
75 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
76 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
77 struct pcnet_init_block init_block;
78 /* Receive Buffer space */
79 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
84 static pcnet_priv_t *lp;
86 /* Offsets from base I/O address for WIO mode */
87 #define PCNET_RDP 0x10
88 #define PCNET_RAP 0x12
89 #define PCNET_RESET 0x14
90 #define PCNET_BDP 0x16
92 static u16 pcnet_read_csr(struct eth_device *dev, int index)
94 outw(index, dev->iobase + PCNET_RAP);
95 return inw(dev->iobase + PCNET_RDP);
98 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
100 outw(index, dev->iobase + PCNET_RAP);
101 outw(val, dev->iobase + PCNET_RDP);
104 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
106 outw(index, dev->iobase + PCNET_RAP);
107 return inw(dev->iobase + PCNET_BDP);
110 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
112 outw(index, dev->iobase + PCNET_RAP);
113 outw(val, dev->iobase + PCNET_BDP);
116 static void pcnet_reset(struct eth_device *dev)
118 inw(dev->iobase + PCNET_RESET);
121 static int pcnet_check(struct eth_device *dev)
123 outw(88, dev->iobase + PCNET_RAP);
124 return inw(dev->iobase + PCNET_RAP) == 88;
127 static int pcnet_init (struct eth_device *dev, bd_t * bis);
128 static int pcnet_send(struct eth_device *dev, void *packet, int length);
129 static int pcnet_recv (struct eth_device *dev);
130 static void pcnet_halt (struct eth_device *dev);
131 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
133 #define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
134 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
136 static struct pci_device_id supported[] = {
137 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
142 int pcnet_initialize(bd_t *bis)
145 struct eth_device *dev;
149 PCNET_DEBUG1("\npcnet_initialize...\n");
151 for (dev_nr = 0;; dev_nr++) {
154 * Find the PCnet PCI device(s).
156 devbusfn = pci_find_devices(supported, dev_nr);
161 * Allocate and pre-fill the device structure.
163 dev = (struct eth_device *)malloc(sizeof(*dev));
165 printf("pcnet: Can not allocate memory\n");
168 memset(dev, 0, sizeof(*dev));
169 dev->priv = (void *)devbusfn;
170 sprintf(dev->name, "pcnet#%d", dev_nr);
173 * Setup the PCI device.
175 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
176 (unsigned int *)&dev->iobase);
177 dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
180 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
181 dev->name, devbusfn, dev->iobase);
183 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
184 pci_write_config_word(devbusfn, PCI_COMMAND, command);
185 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
186 if ((status & command) != command) {
187 printf("%s: Couldn't enable IO access or Bus Mastering\n",
193 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
196 * Probe the PCnet chip.
198 if (pcnet_probe(dev, bis, dev_nr) < 0) {
204 * Setup device structure and register the driver.
206 dev->init = pcnet_init;
207 dev->halt = pcnet_halt;
208 dev->send = pcnet_send;
209 dev->recv = pcnet_recv;
219 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
224 #ifdef PCNET_HAS_PROM
228 /* Reset the PCnet controller */
231 /* Check if register access is working */
232 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
233 printf("%s: CSR register access check failed\n", dev->name);
237 /* Identify the chip */
239 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
240 if ((chip_version & 0xfff) != 0x003)
242 chip_version = (chip_version >> 12) & 0xffff;
243 switch (chip_version) {
245 chipname = "PCnet/PCI II 79C970A"; /* PCI */
247 #ifdef CONFIG_PCNET_79C973
249 chipname = "PCnet/FAST III 79C973"; /* PCI */
252 #ifdef CONFIG_PCNET_79C975
254 chipname = "PCnet/FAST III 79C975"; /* PCI */
258 printf("%s: PCnet version %#x not supported\n",
259 dev->name, chip_version);
263 PCNET_DEBUG1("AMD %s\n", chipname);
265 #ifdef PCNET_HAS_PROM
267 * In most chips, after a chip reset, the ethernet address is read from
268 * the station address PROM at the base address and programmed into the
269 * "Physical Address Registers" CSR12-14.
271 for (i = 0; i < 3; i++) {
274 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
275 /* There may be endianness issues here. */
276 dev->enetaddr[2 * i] = val & 0x0ff;
277 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
279 #endif /* PCNET_HAS_PROM */
284 static int pcnet_init(struct eth_device *dev, bd_t *bis)
289 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
291 /* Switch pcnet to 32bit mode */
292 pcnet_write_bcr(dev, 20, 2);
294 /* Set/reset autoselect bit */
295 val = pcnet_read_bcr(dev, 2) & ~2;
297 pcnet_write_bcr(dev, 2, val);
299 /* Enable auto negotiate, setup, disable fd */
300 val = pcnet_read_bcr(dev, 32) & ~0x98;
302 pcnet_write_bcr(dev, 32, val);
305 * Enable NOUFLO on supported controllers, with the transmit
306 * start point set to the full packet. This will cause entire
307 * packets to be buffered by the ethernet controller before
308 * transmission, eliminating underflows which are common on
309 * slower devices. Controllers which do not support NOUFLO will
310 * simply be left with a larger transmit FIFO threshold.
312 val = pcnet_read_bcr(dev, 18);
314 pcnet_write_bcr(dev, 18, val);
315 val = pcnet_read_csr(dev, 80);
317 pcnet_write_csr(dev, 80, val);
320 * We only maintain one structure because the drivers will never
321 * be used concurrently. In 32bit mode the RX and TX ring entries
322 * must be aligned on 16-byte boundaries.
325 addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
326 addr = (addr + 0xf) & ~0xf;
327 lp = (pcnet_priv_t *)addr;
330 lp->init_block.mode = cpu_to_le16(0x0000);
331 lp->init_block.filter[0] = 0x00000000;
332 lp->init_block.filter[1] = 0x00000000;
335 * Initialize the Rx ring.
338 for (i = 0; i < RX_RING_SIZE; i++) {
339 lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
340 lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
341 lp->rx_ring[i].status = cpu_to_le16(0x8000);
343 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
344 lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
345 lp->rx_ring[i].status);
349 * Initialize the Tx ring. The Tx buffer address is filled in as
350 * needed, but we do need to clear the upper ownership bit.
353 for (i = 0; i < TX_RING_SIZE; i++) {
354 lp->tx_ring[i].base = 0;
355 lp->tx_ring[i].status = 0;
361 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
363 for (i = 0; i < 6; i++) {
364 lp->init_block.phys_addr[i] = dev->enetaddr[i];
365 PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
368 lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
370 lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
371 lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
372 flush_dcache_range((unsigned long)lp, (unsigned long)&lp->rx_buf);
374 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
375 lp->init_block.tlen_rlen,
376 lp->init_block.rx_ring, lp->init_block.tx_ring);
379 * Tell the controller where the Init Block is located.
381 addr = PCI_TO_MEM(dev, &lp->init_block);
382 pcnet_write_csr(dev, 1, addr & 0xffff);
383 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
385 pcnet_write_csr(dev, 4, 0x0915);
386 pcnet_write_csr(dev, 0, 0x0001); /* start */
388 /* Wait for Init Done bit */
389 for (i = 10000; i > 0; i--) {
390 if (pcnet_read_csr(dev, 0) & 0x0100)
395 printf("%s: TIMEOUT: controller init failed\n", dev->name);
401 * Finally start network controller operation.
403 pcnet_write_csr(dev, 0, 0x0002);
408 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
411 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
413 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
416 flush_dcache_range((unsigned long)packet,
417 (unsigned long)packet + pkt_len);
419 /* Wait for completion by testing the OWN bit */
420 for (i = 1000; i > 0; i--) {
421 invalidate_dcache_range((unsigned long)entry,
422 (unsigned long)entry + sizeof(*entry));
423 status = le16_to_cpu(entry->status);
424 if ((status & 0x8000) == 0)
430 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
431 dev->name, lp->cur_tx, status);
437 * Setup Tx ring. Caution: the write order is important here,
438 * set the status with the "ownership" bits last.
441 entry->length = cpu_to_le16(-pkt_len);
442 entry->misc = 0x00000000;
443 entry->base = PCI_TO_MEM_LE(dev, packet);
444 entry->status = cpu_to_le16(status);
445 flush_dcache_range((unsigned long)entry,
446 (unsigned long)entry + sizeof(*entry));
448 /* Trigger an immediate send poll. */
449 pcnet_write_csr(dev, 0, 0x0008);
452 if (++lp->cur_tx >= TX_RING_SIZE)
455 PCNET_DEBUG2("done\n");
459 static int pcnet_recv (struct eth_device *dev)
461 struct pcnet_rx_head *entry;
466 entry = &lp->rx_ring[lp->cur_rx];
467 invalidate_dcache_range((unsigned long)entry,
468 (unsigned long)entry + sizeof(*entry));
470 * If we own the next entry, it's a new packet. Send it up.
472 status = le16_to_cpu(entry->status);
473 if ((status & 0x8000) != 0)
477 if (status != 0x03) { /* There was an error. */
478 printf("%s: Rx%d", dev->name, lp->cur_rx);
479 PCNET_DEBUG1(" (status=0x%x)", status);
489 entry->status &= le16_to_cpu(0x03ff);
492 pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
494 printf("%s: Rx%d: invalid packet length %d\n",
495 dev->name, lp->cur_rx, pkt_len);
497 invalidate_dcache_range(
498 (unsigned long)lp->rx_buf[lp->cur_rx],
499 (unsigned long)lp->rx_buf[lp->cur_rx] +
501 NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
502 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
504 lp->rx_buf[lp->cur_rx]);
507 entry->status |= cpu_to_le16(0x8000);
508 flush_dcache_range((unsigned long)entry,
509 (unsigned long)entry + sizeof(*entry));
511 if (++lp->cur_rx >= RX_RING_SIZE)
517 static void pcnet_halt(struct eth_device *dev)
521 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
523 /* Reset the PCnet controller */
526 /* Wait for Stop bit */
527 for (i = 1000; i > 0; i--) {
528 if (pcnet_read_csr(dev, 0) & 0x4)
533 printf("%s: TIMEOUT: controller reset failed\n", dev->name);