drivers/net/pcnet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
   4  *
   5  * This driver for AMD PCnet network controllers is derived from the
   6  * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18 #include <pci.h>
  19 #include <linux/delay.h>
  20
  21 #define PCNET_DEBUG_LEVEL       0       /* 0=off, 1=init, 2=rx/tx */
  22
  23 #define PCNET_DEBUG1(fmt,args...)       \
  24         debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
  25 #define PCNET_DEBUG2(fmt,args...)       \
  26         debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
  27
  28 /*
  29  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  30  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  31  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  32  */
  33 #define PCNET_LOG_TX_BUFFERS    0
  34 #define PCNET_LOG_RX_BUFFERS    2
  35
  36 #define TX_RING_SIZE            (1 << (PCNET_LOG_TX_BUFFERS))
  37 #define TX_RING_LEN_BITS        ((PCNET_LOG_TX_BUFFERS) << 12)
  38
  39 #define RX_RING_SIZE            (1 << (PCNET_LOG_RX_BUFFERS))
  40 #define RX_RING_LEN_BITS        ((PCNET_LOG_RX_BUFFERS) << 4)
  41
  42 #define PKT_BUF_SZ              1544
  43
  44 /* The PCNET Rx and Tx ring descriptors. */
  45 struct pcnet_rx_head {
  46         u32 base;
  47         s16 buf_length;
  48         s16 status;
  49         u32 msg_length;
  50         u32 reserved;
  51 };
  52
  53 struct pcnet_tx_head {
  54         u32 base;
  55         s16 length;
  56         s16 status;
  57         u32 misc;
  58         u32 reserved;
  59 };
  60
  61 /* The PCNET 32-Bit initialization block, described in databook. */
  62 struct pcnet_init_block {
  63         u16 mode;
  64         u16 tlen_rlen;
  65         u8 phys_addr[6];
  66         u16 reserved;
  67         u32 filter[2];
  68         /* Receive and transmit ring base, along with extra bits. */
  69         u32 rx_ring;
  70         u32 tx_ring;
  71         u32 reserved2;
  72 };
  73
  74 struct pcnet_uncached_priv {
  75         struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  76         struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  77         struct pcnet_init_block init_block;
  78 } __aligned(ARCH_DMA_MINALIGN);
  79
  80 struct pcnet_priv {
  81         struct pcnet_uncached_priv ucp;
  82         /* Receive Buffer space */
  83         unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
  84         struct pcnet_uncached_priv *uc;
  85         pci_dev_t dev;
  86         void __iomem *iobase;
  87         int cur_rx;
  88         int cur_tx;
  89 };
  90
  91 /* Offsets from base I/O address for WIO mode */
  92 #define PCNET_RDP               0x10
  93 #define PCNET_RAP               0x12
  94 #define PCNET_RESET             0x14
  95 #define PCNET_BDP               0x16
  96
  97 static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
  98 {
  99         writew(index, lp->iobase + PCNET_RAP);
 100         return readw(lp->iobase + PCNET_RDP);
 101 }
 102
 103 static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
 104 {
 105         writew(index, lp->iobase + PCNET_RAP);
 106         writew(val, lp->iobase + PCNET_RDP);
 107 }
 108
 109 static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
 110 {
 111         writew(index, lp->iobase + PCNET_RAP);
 112         return readw(lp->iobase + PCNET_BDP);
 113 }
 114
 115 static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
 116 {
 117         writew(index, lp->iobase + PCNET_RAP);
 118         writew(val, lp->iobase + PCNET_BDP);
 119 }
 120
 121 static void pcnet_reset(struct pcnet_priv *lp)
 122 {
 123         readw(lp->iobase + PCNET_RESET);
 124 }
 125
 126 static int pcnet_check(struct pcnet_priv *lp)
 127 {
 128         writew(88, lp->iobase + PCNET_RAP);
 129         return readw(lp->iobase + PCNET_RAP) == 88;
 130 }
 131
 132 static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
 133 {
 134         void *virt_addr = addr;
 135
 136         return pci_virt_to_mem(lp->dev, virt_addr);
 137 }
 138
 139 static struct pci_device_id supported[] = {
 140         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
 141         {}
 142 };
 143
 144 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
 145 {
 146         struct pcnet_priv *lp = dev->priv;
 147         int chip_version;
 148         char *chipname;
 149         int i;
 150
 151         /* Reset the PCnet controller */
 152         pcnet_reset(lp);
 153
 154         /* Check if register access is working */
 155         if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
 156                 printf("%s: CSR register access check failed\n", dev->name);
 157                 return -1;
 158         }
 159
 160         /* Identify the chip */
 161         chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
 162         if ((chip_version & 0xfff) != 0x003)
 163                 return -1;
 164         chip_version = (chip_version >> 12) & 0xffff;
 165         switch (chip_version) {
 166         case 0x2621:
 167                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
 168                 break;
 169         case 0x2625:
 170                 chipname = "PCnet/FAST III 79C973";     /* PCI */
 171                 break;
 172         case 0x2627:
 173                 chipname = "PCnet/FAST III 79C975";     /* PCI */
 174                 break;
 175         default:
 176                 printf("%s: PCnet version %#x not supported\n",
 177                        dev->name, chip_version);
 178                 return -1;
 179         }
 180
 181         PCNET_DEBUG1("AMD %s\n", chipname);
 182
 183         /*
 184          * In most chips, after a chip reset, the ethernet address is read from
 185          * the station address PROM at the base address and programmed into the
 186          * "Physical Address Registers" CSR12-14.
 187          */
 188         for (i = 0; i < 3; i++) {
 189                 unsigned int val;
 190
 191                 val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
 192                 /* There may be endianness issues here. */
 193                 dev->enetaddr[2 * i] = val & 0x0ff;
 194                 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int pcnet_init(struct eth_device *dev, bd_t *bis)
 201 {
 202         struct pcnet_priv *lp = dev->priv;
 203         struct pcnet_uncached_priv *uc;
 204         int i, val;
 205         unsigned long addr;
 206
 207         PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 208
 209         /* Switch pcnet to 32bit mode */
 210         pcnet_write_bcr(lp, 20, 2);
 211
 212         /* Set/reset autoselect bit */
 213         val = pcnet_read_bcr(lp, 2) & ~2;
 214         val |= 2;
 215         pcnet_write_bcr(lp, 2, val);
 216
 217         /* Enable auto negotiate, setup, disable fd */
 218         val = pcnet_read_bcr(lp, 32) & ~0x98;
 219         val |= 0x20;
 220         pcnet_write_bcr(lp, 32, val);
 221
 222         /*
 223          * Enable NOUFLO on supported controllers, with the transmit
 224          * start point set to the full packet. This will cause entire
 225          * packets to be buffered by the ethernet controller before
 226          * transmission, eliminating underflows which are common on
 227          * slower devices. Controllers which do not support NOUFLO will
 228          * simply be left with a larger transmit FIFO threshold.
 229          */
 230         val = pcnet_read_bcr(lp, 18);
 231         val |= 1 << 11;
 232         pcnet_write_bcr(lp, 18, val);
 233         val = pcnet_read_csr(lp, 80);
 234         val |= 0x3 << 10;
 235         pcnet_write_csr(lp, 80, val);
 236
 237         uc = lp->uc;
 238
 239         uc->init_block.mode = cpu_to_le16(0x0000);
 240         uc->init_block.filter[0] = 0x00000000;
 241         uc->init_block.filter[1] = 0x00000000;
 242
 243         /*
 244          * Initialize the Rx ring.
 245          */
 246         lp->cur_rx = 0;
 247         for (i = 0; i < RX_RING_SIZE; i++) {
 248                 addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
 249                 uc->rx_ring[i].base = cpu_to_le32(addr);
 250                 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 251                 uc->rx_ring[i].status = cpu_to_le16(0x8000);
 252                 PCNET_DEBUG1
 253                         ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
 254                          uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
 255                          uc->rx_ring[i].status);
 256         }
 257
 258         /*
 259          * Initialize the Tx ring. The Tx buffer address is filled in as
 260          * needed, but we do need to clear the upper ownership bit.
 261          */
 262         lp->cur_tx = 0;
 263         for (i = 0; i < TX_RING_SIZE; i++) {
 264                 uc->tx_ring[i].base = 0;
 265                 uc->tx_ring[i].status = 0;
 266         }
 267
 268         /*
 269          * Setup Init Block.
 270          */
 271         PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
 272
 273         for (i = 0; i < 6; i++) {
 274                 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
 275                 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
 276         }
 277
 278         uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 279                                                RX_RING_LEN_BITS);
 280         addr = pcnet_virt_to_mem(lp, uc->rx_ring);
 281         uc->init_block.rx_ring = cpu_to_le32(addr);
 282         addr = pcnet_virt_to_mem(lp, uc->tx_ring);
 283         uc->init_block.tx_ring = cpu_to_le32(addr);
 284
 285         PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
 286                      uc->init_block.tlen_rlen,
 287                      uc->init_block.rx_ring, uc->init_block.tx_ring);
 288
 289         /*
 290          * Tell the controller where the Init Block is located.
 291          */
 292         barrier();
 293         addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
 294         pcnet_write_csr(lp, 1, addr & 0xffff);
 295         pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
 296
 297         pcnet_write_csr(lp, 4, 0x0915);
 298         pcnet_write_csr(lp, 0, 0x0001); /* start */
 299
 300         /* Wait for Init Done bit */
 301         for (i = 10000; i > 0; i--) {
 302                 if (pcnet_read_csr(lp, 0) & 0x0100)
 303                         break;
 304                 udelay(10);
 305         }
 306         if (i <= 0) {
 307                 printf("%s: TIMEOUT: controller init failed\n", dev->name);
 308                 pcnet_reset(lp);
 309                 return -1;
 310         }
 311
 312         /*
 313          * Finally start network controller operation.
 314          */
 315         pcnet_write_csr(lp, 0, 0x0002);
 316
 317         return 0;
 318 }
 319
 320 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 321 {
 322         struct pcnet_priv *lp = dev->priv;
 323         int i, status;
 324         u32 addr;
 325         struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
 326
 327         PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
 328                      packet);
 329
 330         flush_dcache_range((unsigned long)packet,
 331                            (unsigned long)packet + pkt_len);
 332
 333         /* Wait for completion by testing the OWN bit */
 334         for (i = 1000; i > 0; i--) {
 335                 status = readw(&entry->status);
 336                 if ((status & 0x8000) == 0)
 337                         break;
 338                 udelay(100);
 339                 PCNET_DEBUG2(".");
 340         }
 341         if (i <= 0) {
 342                 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
 343                        dev->name, lp->cur_tx, status);
 344                 pkt_len = 0;
 345                 goto failure;
 346         }
 347
 348         /*
 349          * Setup Tx ring. Caution: the write order is important here,
 350          * set the status with the "ownership" bits last.
 351          */
 352         addr = pcnet_virt_to_mem(lp, packet);
 353         writew(-pkt_len, &entry->length);
 354         writel(0, &entry->misc);
 355         writel(addr, &entry->base);
 356         writew(0x8300, &entry->status);
 357
 358         /* Trigger an immediate send poll. */
 359         pcnet_write_csr(lp, 0, 0x0008);
 360
 361       failure:
 362         if (++lp->cur_tx >= TX_RING_SIZE)
 363                 lp->cur_tx = 0;
 364
 365         PCNET_DEBUG2("done\n");
 366         return pkt_len;
 367 }
 368
 369 static int pcnet_recv (struct eth_device *dev)
 370 {
 371         struct pcnet_priv *lp = dev->priv;
 372         struct pcnet_rx_head *entry;
 373         unsigned char *buf;
 374         int pkt_len = 0;
 375         u16 status, err_status;
 376
 377         while (1) {
 378                 entry = &lp->uc->rx_ring[lp->cur_rx];
 379                 /*
 380                  * If we own the next entry, it's a new packet. Send it up.
 381                  */
 382                 status = readw(&entry->status);
 383                 if ((status & 0x8000) != 0)
 384                         break;
 385                 err_status = status >> 8;
 386
 387                 if (err_status != 0x03) {       /* There was an error. */
 388                         printf("%s: Rx%d", dev->name, lp->cur_rx);
 389                         PCNET_DEBUG1(" (status=0x%x)", err_status);
 390                         if (err_status & 0x20)
 391                                 printf(" Frame");
 392                         if (err_status & 0x10)
 393                                 printf(" Overflow");
 394                         if (err_status & 0x08)
 395                                 printf(" CRC");
 396                         if (err_status & 0x04)
 397                                 printf(" Fifo");
 398                         printf(" Error\n");
 399                         status &= 0x03ff;
 400
 401                 } else {
 402                         pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
 403                         if (pkt_len < 60) {
 404                                 printf("%s: Rx%d: invalid packet length %d\n",
 405                                        dev->name, lp->cur_rx, pkt_len);
 406                         } else {
 407                                 buf = lp->rx_buf[lp->cur_rx];
 408                                 invalidate_dcache_range((unsigned long)buf,
 409                                         (unsigned long)buf + pkt_len);
 410                                 net_process_received_packet(buf, pkt_len);
 411                                 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
 412                                              lp->cur_rx, pkt_len, buf);
 413                         }
 414                 }
 415
 416                 status |= 0x8000;
 417                 writew(status, &entry->status);
 418
 419                 if (++lp->cur_rx >= RX_RING_SIZE)
 420                         lp->cur_rx = 0;
 421         }
 422         return pkt_len;
 423 }
 424
 425 static void pcnet_halt(struct eth_device *dev)
 426 {
 427         struct pcnet_priv *lp = dev->priv;
 428         int i;
 429
 430         PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
 431
 432         /* Reset the PCnet controller */
 433         pcnet_reset(lp);
 434
 435         /* Wait for Stop bit */
 436         for (i = 1000; i > 0; i--) {
 437                 if (pcnet_read_csr(lp, 0) & 0x4)
 438                         break;
 439                 udelay(10);
 440         }
 441         if (i <= 0)
 442                 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
 443 }
 444
 445 int pcnet_initialize(bd_t *bis)
 446 {
 447         pci_dev_t devbusfn;
 448         struct eth_device *dev;
 449         struct pcnet_priv *lp;
 450         u16 command, status;
 451         int dev_nr = 0;
 452         u32 bar;
 453
 454         PCNET_DEBUG1("\npcnet_initialize...\n");
 455
 456         for (dev_nr = 0; ; dev_nr++) {
 457                 /*
 458                  * Find the PCnet PCI device(s).
 459                  */
 460                 devbusfn = pci_find_devices(supported, dev_nr);
 461                 if (devbusfn < 0)
 462                         break;
 463
 464                 /*
 465                  * Allocate and pre-fill the device structure.
 466                  */
 467                 dev = calloc(1, sizeof(*dev));
 468                 if (!dev) {
 469                         printf("pcnet: Can not allocate memory\n");
 470                         break;
 471                 }
 472
 473                 /*
 474                  * We only maintain one structure because the drivers will
 475                  * never be used concurrently. In 32bit mode the RX and TX
 476                  * ring entries must be aligned on 16-byte boundaries.
 477                  */
 478                 lp = malloc_cache_aligned(sizeof(*lp));
 479                 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
 480                                      sizeof(lp->ucp), MAP_NOCACHE);
 481                 lp->dev = devbusfn;
 482                 flush_dcache_range((unsigned long)lp,
 483                                    (unsigned long)lp + sizeof(*lp));
 484                 dev->priv = lp;
 485                 sprintf(dev->name, "pcnet#%d", dev_nr);
 486
 487                 /*
 488                  * Setup the PCI device.
 489                  */
 490                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
 491                 lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
 492
 493                 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
 494                              dev->name, devbusfn, lp->iobase);
 495
 496                 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 497                 pci_write_config_word(devbusfn, PCI_COMMAND, command);
 498                 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 499                 if ((status & command) != command) {
 500                         printf("%s: Couldn't enable IO access or Bus Mastering\n",
 501                                dev->name);
 502                         free(dev);
 503                         continue;
 504                 }
 505
 506                 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
 507
 508                 /*
 509                  * Probe the PCnet chip.
 510                  */
 511                 if (pcnet_probe(dev, bis, dev_nr) < 0) {
 512                         free(dev);
 513                         continue;
 514                 }
 515
 516                 /*
 517                  * Setup device structure and register the driver.
 518                  */
 519                 dev->init = pcnet_init;
 520                 dev->halt = pcnet_halt;
 521                 dev->send = pcnet_send;
 522                 dev->recv = pcnet_recv;
 523
 524                 eth_register(dev);
 525         }
 526
 527         udelay(10 * 1000);
 528
 529         return dev_nr;
 530 }