drivers/net/pcnet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
   4  *
   5  * This driver for AMD PCnet network controllers is derived from the
   6  * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <malloc.h>
  12 #include <net.h>
  13 #include <netdev.h>
  14 #include <asm/cache.h>
  15 #include <asm/io.h>
  16 #include <pci.h>
  17
  18 #define PCNET_DEBUG_LEVEL       0       /* 0=off, 1=init, 2=rx/tx */
  19
  20 #define PCNET_DEBUG1(fmt,args...)       \
  21         debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
  22 #define PCNET_DEBUG2(fmt,args...)       \
  23         debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
  24
  25 /*
  26  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  27  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  28  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  29  */
  30 #define PCNET_LOG_TX_BUFFERS    0
  31 #define PCNET_LOG_RX_BUFFERS    2
  32
  33 #define TX_RING_SIZE            (1 << (PCNET_LOG_TX_BUFFERS))
  34 #define TX_RING_LEN_BITS        ((PCNET_LOG_TX_BUFFERS) << 12)
  35
  36 #define RX_RING_SIZE            (1 << (PCNET_LOG_RX_BUFFERS))
  37 #define RX_RING_LEN_BITS        ((PCNET_LOG_RX_BUFFERS) << 4)
  38
  39 #define PKT_BUF_SZ              1544
  40
  41 /* The PCNET Rx and Tx ring descriptors. */
  42 struct pcnet_rx_head {
  43         u32 base;
  44         s16 buf_length;
  45         s16 status;
  46         u32 msg_length;
  47         u32 reserved;
  48 };
  49
  50 struct pcnet_tx_head {
  51         u32 base;
  52         s16 length;
  53         s16 status;
  54         u32 misc;
  55         u32 reserved;
  56 };
  57
  58 /* The PCNET 32-Bit initialization block, described in databook. */
  59 struct pcnet_init_block {
  60         u16 mode;
  61         u16 tlen_rlen;
  62         u8 phys_addr[6];
  63         u16 reserved;
  64         u32 filter[2];
  65         /* Receive and transmit ring base, along with extra bits. */
  66         u32 rx_ring;
  67         u32 tx_ring;
  68         u32 reserved2;
  69 };
  70
  71 struct pcnet_uncached_priv {
  72         struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  73         struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  74         struct pcnet_init_block init_block;
  75 };
  76
  77 typedef struct pcnet_priv {
  78         struct pcnet_uncached_priv *uc;
  79         /* Receive Buffer space */
  80         unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
  81         int cur_rx;
  82         int cur_tx;
  83 } pcnet_priv_t;
  84
  85 static pcnet_priv_t *lp;
  86
  87 /* Offsets from base I/O address for WIO mode */
  88 #define PCNET_RDP               0x10
  89 #define PCNET_RAP               0x12
  90 #define PCNET_RESET             0x14
  91 #define PCNET_BDP               0x16
  92
  93 static u16 pcnet_read_csr(struct eth_device *dev, int index)
  94 {
  95         void __iomem *base = (void __iomem *)dev->iobase;
  96
  97         writew(index, base + PCNET_RAP);
  98         return readw(base + PCNET_RDP);
  99 }
 100
 101 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
 102 {
 103         void __iomem *base = (void __iomem *)dev->iobase;
 104
 105         writew(index, base + PCNET_RAP);
 106         writew(val, base + PCNET_RDP);
 107 }
 108
 109 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
 110 {
 111         void __iomem *base = (void __iomem *)dev->iobase;
 112
 113         writew(index, base + PCNET_RAP);
 114         return readw(base + PCNET_BDP);
 115 }
 116
 117 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
 118 {
 119         void __iomem *base = (void __iomem *)dev->iobase;
 120
 121         writew(index, base + PCNET_RAP);
 122         writew(val, base + PCNET_BDP);
 123 }
 124
 125 static void pcnet_reset(struct eth_device *dev)
 126 {
 127         void __iomem *base = (void __iomem *)dev->iobase;
 128
 129         readw(base + PCNET_RESET);
 130 }
 131
 132 static int pcnet_check(struct eth_device *dev)
 133 {
 134         void __iomem *base = (void __iomem *)dev->iobase;
 135
 136         writew(88, base + PCNET_RAP);
 137         return readw(base + PCNET_RAP) == 88;
 138 }
 139
 140 static int pcnet_init (struct eth_device *dev, bd_t * bis);
 141 static int pcnet_send(struct eth_device *dev, void *packet, int length);
 142 static int pcnet_recv (struct eth_device *dev);
 143 static void pcnet_halt (struct eth_device *dev);
 144 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 145
 146 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
 147                                                 void *addr)
 148 {
 149         pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
 150         void *virt_addr = addr;
 151
 152         return pci_virt_to_mem(devbusfn, virt_addr);
 153 }
 154
 155 static struct pci_device_id supported[] = {
 156         {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
 157         {}
 158 };
 159
 160
 161 int pcnet_initialize(bd_t *bis)
 162 {
 163         pci_dev_t devbusfn;
 164         struct eth_device *dev;
 165         u16 command, status;
 166         int dev_nr = 0;
 167         u32 bar;
 168
 169         PCNET_DEBUG1("\npcnet_initialize...\n");
 170
 171         for (dev_nr = 0;; dev_nr++) {
 172
 173                 /*
 174                  * Find the PCnet PCI device(s).
 175                  */
 176                 devbusfn = pci_find_devices(supported, dev_nr);
 177                 if (devbusfn < 0)
 178                         break;
 179
 180                 /*
 181                  * Allocate and pre-fill the device structure.
 182                  */
 183                 dev = (struct eth_device *)malloc(sizeof(*dev));
 184                 if (!dev) {
 185                         printf("pcnet: Can not allocate memory\n");
 186                         break;
 187                 }
 188                 memset(dev, 0, sizeof(*dev));
 189                 dev->priv = (void *)(unsigned long)devbusfn;
 190                 sprintf(dev->name, "pcnet#%d", dev_nr);
 191
 192                 /*
 193                  * Setup the PCI device.
 194                  */
 195                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
 196                 dev->iobase = pci_mem_to_phys(devbusfn, bar);
 197                 dev->iobase &= ~0xf;
 198
 199                 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
 200                              dev->name, devbusfn, (unsigned long)dev->iobase);
 201
 202                 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 203                 pci_write_config_word(devbusfn, PCI_COMMAND, command);
 204                 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 205                 if ((status & command) != command) {
 206                         printf("%s: Couldn't enable IO access or Bus Mastering\n",
 207                                dev->name);
 208                         free(dev);
 209                         continue;
 210                 }
 211
 212                 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
 213
 214                 /*
 215                  * Probe the PCnet chip.
 216                  */
 217                 if (pcnet_probe(dev, bis, dev_nr) < 0) {
 218                         free(dev);
 219                         continue;
 220                 }
 221
 222                 /*
 223                  * Setup device structure and register the driver.
 224                  */
 225                 dev->init = pcnet_init;
 226                 dev->halt = pcnet_halt;
 227                 dev->send = pcnet_send;
 228                 dev->recv = pcnet_recv;
 229
 230                 eth_register(dev);
 231         }
 232
 233         udelay(10 * 1000);
 234
 235         return dev_nr;
 236 }
 237
 238 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
 239 {
 240         int chip_version;
 241         char *chipname;
 242
 243 #ifdef PCNET_HAS_PROM
 244         int i;
 245 #endif
 246
 247         /* Reset the PCnet controller */
 248         pcnet_reset(dev);
 249
 250         /* Check if register access is working */
 251         if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
 252                 printf("%s: CSR register access check failed\n", dev->name);
 253                 return -1;
 254         }
 255
 256         /* Identify the chip */
 257         chip_version =
 258                 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
 259         if ((chip_version & 0xfff) != 0x003)
 260                 return -1;
 261         chip_version = (chip_version >> 12) & 0xffff;
 262         switch (chip_version) {
 263         case 0x2621:
 264                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
 265                 break;
 266         case 0x2625:
 267                 chipname = "PCnet/FAST III 79C973";     /* PCI */
 268                 break;
 269         case 0x2627:
 270                 chipname = "PCnet/FAST III 79C975";     /* PCI */
 271                 break;
 272         default:
 273                 printf("%s: PCnet version %#x not supported\n",
 274                        dev->name, chip_version);
 275                 return -1;
 276         }
 277
 278         PCNET_DEBUG1("AMD %s\n", chipname);
 279
 280 #ifdef PCNET_HAS_PROM
 281         /*
 282          * In most chips, after a chip reset, the ethernet address is read from
 283          * the station address PROM at the base address and programmed into the
 284          * "Physical Address Registers" CSR12-14.
 285          */
 286         for (i = 0; i < 3; i++) {
 287                 unsigned int val;
 288
 289                 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
 290                 /* There may be endianness issues here. */
 291                 dev->enetaddr[2 * i] = val & 0x0ff;
 292                 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
 293         }
 294 #endif /* PCNET_HAS_PROM */
 295
 296         return 0;
 297 }
 298
 299 static int pcnet_init(struct eth_device *dev, bd_t *bis)
 300 {
 301         struct pcnet_uncached_priv *uc;
 302         int i, val;
 303         unsigned long addr;
 304
 305         PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 306
 307         /* Switch pcnet to 32bit mode */
 308         pcnet_write_bcr(dev, 20, 2);
 309
 310         /* Set/reset autoselect bit */
 311         val = pcnet_read_bcr(dev, 2) & ~2;
 312         val |= 2;
 313         pcnet_write_bcr(dev, 2, val);
 314
 315         /* Enable auto negotiate, setup, disable fd */
 316         val = pcnet_read_bcr(dev, 32) & ~0x98;
 317         val |= 0x20;
 318         pcnet_write_bcr(dev, 32, val);
 319
 320         /*
 321          * Enable NOUFLO on supported controllers, with the transmit
 322          * start point set to the full packet. This will cause entire
 323          * packets to be buffered by the ethernet controller before
 324          * transmission, eliminating underflows which are common on
 325          * slower devices. Controllers which do not support NOUFLO will
 326          * simply be left with a larger transmit FIFO threshold.
 327          */
 328         val = pcnet_read_bcr(dev, 18);
 329         val |= 1 << 11;
 330         pcnet_write_bcr(dev, 18, val);
 331         val = pcnet_read_csr(dev, 80);
 332         val |= 0x3 << 10;
 333         pcnet_write_csr(dev, 80, val);
 334
 335         /*
 336          * We only maintain one structure because the drivers will never
 337          * be used concurrently. In 32bit mode the RX and TX ring entries
 338          * must be aligned on 16-byte boundaries.
 339          */
 340         if (lp == NULL) {
 341                 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
 342                 addr = (addr + 0xf) & ~0xf;
 343                 lp = (pcnet_priv_t *)addr;
 344
 345                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 346                                                sizeof(*lp->uc));
 347                 flush_dcache_range(addr, addr + sizeof(*lp->uc));
 348                 addr = (unsigned long)map_physmem(addr,
 349                                 roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
 350                                 MAP_NOCACHE);
 351                 lp->uc = (struct pcnet_uncached_priv *)addr;
 352
 353                 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 354                                                sizeof(*lp->rx_buf));
 355                 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
 356                 lp->rx_buf = (void *)addr;
 357         }
 358
 359         uc = lp->uc;
 360
 361         uc->init_block.mode = cpu_to_le16(0x0000);
 362         uc->init_block.filter[0] = 0x00000000;
 363         uc->init_block.filter[1] = 0x00000000;
 364
 365         /*
 366          * Initialize the Rx ring.
 367          */
 368         lp->cur_rx = 0;
 369         for (i = 0; i < RX_RING_SIZE; i++) {
 370                 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
 371                 uc->rx_ring[i].base = cpu_to_le32(addr);
 372                 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 373                 uc->rx_ring[i].status = cpu_to_le16(0x8000);
 374                 PCNET_DEBUG1
 375                         ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
 376                          uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
 377                          uc->rx_ring[i].status);
 378         }
 379
 380         /*
 381          * Initialize the Tx ring. The Tx buffer address is filled in as
 382          * needed, but we do need to clear the upper ownership bit.
 383          */
 384         lp->cur_tx = 0;
 385         for (i = 0; i < TX_RING_SIZE; i++) {
 386                 uc->tx_ring[i].base = 0;
 387                 uc->tx_ring[i].status = 0;
 388         }
 389
 390         /*
 391          * Setup Init Block.
 392          */
 393         PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
 394
 395         for (i = 0; i < 6; i++) {
 396                 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
 397                 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
 398         }
 399
 400         uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 401                                                RX_RING_LEN_BITS);
 402         addr = pcnet_virt_to_mem(dev, uc->rx_ring);
 403         uc->init_block.rx_ring = cpu_to_le32(addr);
 404         addr = pcnet_virt_to_mem(dev, uc->tx_ring);
 405         uc->init_block.tx_ring = cpu_to_le32(addr);
 406
 407         PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
 408                      uc->init_block.tlen_rlen,
 409                      uc->init_block.rx_ring, uc->init_block.tx_ring);
 410
 411         /*
 412          * Tell the controller where the Init Block is located.
 413          */
 414         barrier();
 415         addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
 416         pcnet_write_csr(dev, 1, addr & 0xffff);
 417         pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 418
 419         pcnet_write_csr(dev, 4, 0x0915);
 420         pcnet_write_csr(dev, 0, 0x0001);        /* start */
 421
 422         /* Wait for Init Done bit */
 423         for (i = 10000; i > 0; i--) {
 424                 if (pcnet_read_csr(dev, 0) & 0x0100)
 425                         break;
 426                 udelay(10);
 427         }
 428         if (i <= 0) {
 429                 printf("%s: TIMEOUT: controller init failed\n", dev->name);
 430                 pcnet_reset(dev);
 431                 return -1;
 432         }
 433
 434         /*
 435          * Finally start network controller operation.
 436          */
 437         pcnet_write_csr(dev, 0, 0x0002);
 438
 439         return 0;
 440 }
 441
 442 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 443 {
 444         int i, status;
 445         u32 addr;
 446         struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
 447
 448         PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
 449                      packet);
 450
 451         flush_dcache_range((unsigned long)packet,
 452                            (unsigned long)packet + pkt_len);
 453
 454         /* Wait for completion by testing the OWN bit */
 455         for (i = 1000; i > 0; i--) {
 456                 status = readw(&entry->status);
 457                 if ((status & 0x8000) == 0)
 458                         break;
 459                 udelay(100);
 460                 PCNET_DEBUG2(".");
 461         }
 462         if (i <= 0) {
 463                 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
 464                        dev->name, lp->cur_tx, status);
 465                 pkt_len = 0;
 466                 goto failure;
 467         }
 468
 469         /*
 470          * Setup Tx ring. Caution: the write order is important here,
 471          * set the status with the "ownership" bits last.
 472          */
 473         addr = pcnet_virt_to_mem(dev, packet);
 474         writew(-pkt_len, &entry->length);
 475         writel(0, &entry->misc);
 476         writel(addr, &entry->base);
 477         writew(0x8300, &entry->status);
 478
 479         /* Trigger an immediate send poll. */
 480         pcnet_write_csr(dev, 0, 0x0008);
 481
 482       failure:
 483         if (++lp->cur_tx >= TX_RING_SIZE)
 484                 lp->cur_tx = 0;
 485
 486         PCNET_DEBUG2("done\n");
 487         return pkt_len;
 488 }
 489
 490 static int pcnet_recv (struct eth_device *dev)
 491 {
 492         struct pcnet_rx_head *entry;
 493         unsigned char *buf;
 494         int pkt_len = 0;
 495         u16 status, err_status;
 496
 497         while (1) {
 498                 entry = &lp->uc->rx_ring[lp->cur_rx];
 499                 /*
 500                  * If we own the next entry, it's a new packet. Send it up.
 501                  */
 502                 status = readw(&entry->status);
 503                 if ((status & 0x8000) != 0)
 504                         break;
 505                 err_status = status >> 8;
 506
 507                 if (err_status != 0x03) {       /* There was an error. */
 508                         printf("%s: Rx%d", dev->name, lp->cur_rx);
 509                         PCNET_DEBUG1(" (status=0x%x)", err_status);
 510                         if (err_status & 0x20)
 511                                 printf(" Frame");
 512                         if (err_status & 0x10)
 513                                 printf(" Overflow");
 514                         if (err_status & 0x08)
 515                                 printf(" CRC");
 516                         if (err_status & 0x04)
 517                                 printf(" Fifo");
 518                         printf(" Error\n");
 519                         status &= 0x03ff;
 520
 521                 } else {
 522                         pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
 523                         if (pkt_len < 60) {
 524                                 printf("%s: Rx%d: invalid packet length %d\n",
 525                                        dev->name, lp->cur_rx, pkt_len);
 526                         } else {
 527                                 buf = (*lp->rx_buf)[lp->cur_rx];
 528                                 invalidate_dcache_range((unsigned long)buf,
 529                                         (unsigned long)buf + pkt_len);
 530                                 net_process_received_packet(buf, pkt_len);
 531                                 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
 532                                              lp->cur_rx, pkt_len, buf);
 533                         }
 534                 }
 535
 536                 status |= 0x8000;
 537                 writew(status, &entry->status);
 538
 539                 if (++lp->cur_rx >= RX_RING_SIZE)
 540                         lp->cur_rx = 0;
 541         }
 542         return pkt_len;
 543 }
 544
 545 static void pcnet_halt(struct eth_device *dev)
 546 {
 547         int i;
 548
 549         PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
 550
 551         /* Reset the PCnet controller */
 552         pcnet_reset(dev);
 553
 554         /* Wait for Stop bit */
 555         for (i = 1000; i > 0; i--) {
 556                 if (pcnet_read_csr(dev, 0) & 0x4)
 557                         break;
 558                 udelay(10);
 559         }
 560         if (i <= 0)
 561                 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
 562 }