1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
16 #include <asm/cache.h>
19 #include <linux/delay.h>
21 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
23 #define PCNET_DEBUG1(fmt,args...) \
24 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
25 #define PCNET_DEBUG2(fmt,args...) \
26 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
29 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
33 #define PCNET_LOG_TX_BUFFERS 0
34 #define PCNET_LOG_RX_BUFFERS 2
36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
42 #define PKT_BUF_SZ 1544
44 /* The PCNET Rx and Tx ring descriptors. */
45 struct pcnet_rx_head {
53 struct pcnet_tx_head {
61 /* The PCNET 32-Bit initialization block, described in databook. */
62 struct pcnet_init_block {
68 /* Receive and transmit ring base, along with extra bits. */
74 struct pcnet_uncached_priv {
75 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
76 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
77 struct pcnet_init_block init_block;
78 } __aligned(ARCH_DMA_MINALIGN);
81 struct pcnet_uncached_priv ucp;
82 /* Receive Buffer space */
83 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
84 struct pcnet_uncached_priv *uc;
89 static struct pcnet_priv *lp;
91 /* Offsets from base I/O address for WIO mode */
92 #define PCNET_RDP 0x10
93 #define PCNET_RAP 0x12
94 #define PCNET_RESET 0x14
95 #define PCNET_BDP 0x16
97 static u16 pcnet_read_csr(struct eth_device *dev, int index)
99 void __iomem *base = (void __iomem *)dev->iobase;
101 writew(index, base + PCNET_RAP);
102 return readw(base + PCNET_RDP);
105 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
107 void __iomem *base = (void __iomem *)dev->iobase;
109 writew(index, base + PCNET_RAP);
110 writew(val, base + PCNET_RDP);
113 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
115 void __iomem *base = (void __iomem *)dev->iobase;
117 writew(index, base + PCNET_RAP);
118 return readw(base + PCNET_BDP);
121 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
123 void __iomem *base = (void __iomem *)dev->iobase;
125 writew(index, base + PCNET_RAP);
126 writew(val, base + PCNET_BDP);
129 static void pcnet_reset(struct eth_device *dev)
131 void __iomem *base = (void __iomem *)dev->iobase;
133 readw(base + PCNET_RESET);
136 static int pcnet_check(struct eth_device *dev)
138 void __iomem *base = (void __iomem *)dev->iobase;
140 writew(88, base + PCNET_RAP);
141 return readw(base + PCNET_RAP) == 88;
144 static int pcnet_init (struct eth_device *dev, bd_t * bis);
145 static int pcnet_send(struct eth_device *dev, void *packet, int length);
146 static int pcnet_recv (struct eth_device *dev);
147 static void pcnet_halt (struct eth_device *dev);
148 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
150 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
153 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
154 void *virt_addr = addr;
156 return pci_virt_to_mem(devbusfn, virt_addr);
159 static struct pci_device_id supported[] = {
160 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
165 int pcnet_initialize(bd_t *bis)
168 struct eth_device *dev;
173 PCNET_DEBUG1("\npcnet_initialize...\n");
175 for (dev_nr = 0;; dev_nr++) {
178 * Find the PCnet PCI device(s).
180 devbusfn = pci_find_devices(supported, dev_nr);
185 * Allocate and pre-fill the device structure.
187 dev = (struct eth_device *)malloc(sizeof(*dev));
189 printf("pcnet: Can not allocate memory\n");
192 memset(dev, 0, sizeof(*dev));
193 dev->priv = (void *)(unsigned long)devbusfn;
194 sprintf(dev->name, "pcnet#%d", dev_nr);
197 * Setup the PCI device.
199 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
200 dev->iobase = pci_mem_to_phys(devbusfn, bar);
203 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
204 dev->name, devbusfn, (unsigned long)dev->iobase);
206 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
207 pci_write_config_word(devbusfn, PCI_COMMAND, command);
208 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
209 if ((status & command) != command) {
210 printf("%s: Couldn't enable IO access or Bus Mastering\n",
216 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
219 * Probe the PCnet chip.
221 if (pcnet_probe(dev, bis, dev_nr) < 0) {
227 * Setup device structure and register the driver.
229 dev->init = pcnet_init;
230 dev->halt = pcnet_halt;
231 dev->send = pcnet_send;
232 dev->recv = pcnet_recv;
242 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
248 /* Reset the PCnet controller */
251 /* Check if register access is working */
252 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
253 printf("%s: CSR register access check failed\n", dev->name);
257 /* Identify the chip */
259 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
260 if ((chip_version & 0xfff) != 0x003)
262 chip_version = (chip_version >> 12) & 0xffff;
263 switch (chip_version) {
265 chipname = "PCnet/PCI II 79C970A"; /* PCI */
268 chipname = "PCnet/FAST III 79C973"; /* PCI */
271 chipname = "PCnet/FAST III 79C975"; /* PCI */
274 printf("%s: PCnet version %#x not supported\n",
275 dev->name, chip_version);
279 PCNET_DEBUG1("AMD %s\n", chipname);
282 * In most chips, after a chip reset, the ethernet address is read from
283 * the station address PROM at the base address and programmed into the
284 * "Physical Address Registers" CSR12-14.
286 for (i = 0; i < 3; i++) {
289 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
290 /* There may be endianness issues here. */
291 dev->enetaddr[2 * i] = val & 0x0ff;
292 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
298 static int pcnet_init(struct eth_device *dev, bd_t *bis)
300 struct pcnet_uncached_priv *uc;
304 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
306 /* Switch pcnet to 32bit mode */
307 pcnet_write_bcr(dev, 20, 2);
309 /* Set/reset autoselect bit */
310 val = pcnet_read_bcr(dev, 2) & ~2;
312 pcnet_write_bcr(dev, 2, val);
314 /* Enable auto negotiate, setup, disable fd */
315 val = pcnet_read_bcr(dev, 32) & ~0x98;
317 pcnet_write_bcr(dev, 32, val);
320 * Enable NOUFLO on supported controllers, with the transmit
321 * start point set to the full packet. This will cause entire
322 * packets to be buffered by the ethernet controller before
323 * transmission, eliminating underflows which are common on
324 * slower devices. Controllers which do not support NOUFLO will
325 * simply be left with a larger transmit FIFO threshold.
327 val = pcnet_read_bcr(dev, 18);
329 pcnet_write_bcr(dev, 18, val);
330 val = pcnet_read_csr(dev, 80);
332 pcnet_write_csr(dev, 80, val);
335 * We only maintain one structure because the drivers will never
336 * be used concurrently. In 32bit mode the RX and TX ring entries
337 * must be aligned on 16-byte boundaries.
340 lp = malloc_cache_aligned(sizeof(*lp));
341 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
342 sizeof(lp->ucp), MAP_NOCACHE);
343 flush_dcache_range((unsigned long)lp,
344 (unsigned long)lp + sizeof(*lp));
349 uc->init_block.mode = cpu_to_le16(0x0000);
350 uc->init_block.filter[0] = 0x00000000;
351 uc->init_block.filter[1] = 0x00000000;
354 * Initialize the Rx ring.
357 for (i = 0; i < RX_RING_SIZE; i++) {
358 addr = pcnet_virt_to_mem(dev, lp->rx_buf[i]);
359 uc->rx_ring[i].base = cpu_to_le32(addr);
360 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
361 uc->rx_ring[i].status = cpu_to_le16(0x8000);
363 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
364 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
365 uc->rx_ring[i].status);
369 * Initialize the Tx ring. The Tx buffer address is filled in as
370 * needed, but we do need to clear the upper ownership bit.
373 for (i = 0; i < TX_RING_SIZE; i++) {
374 uc->tx_ring[i].base = 0;
375 uc->tx_ring[i].status = 0;
381 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
383 for (i = 0; i < 6; i++) {
384 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
385 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
388 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
390 addr = pcnet_virt_to_mem(dev, uc->rx_ring);
391 uc->init_block.rx_ring = cpu_to_le32(addr);
392 addr = pcnet_virt_to_mem(dev, uc->tx_ring);
393 uc->init_block.tx_ring = cpu_to_le32(addr);
395 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
396 uc->init_block.tlen_rlen,
397 uc->init_block.rx_ring, uc->init_block.tx_ring);
400 * Tell the controller where the Init Block is located.
403 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
404 pcnet_write_csr(dev, 1, addr & 0xffff);
405 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
407 pcnet_write_csr(dev, 4, 0x0915);
408 pcnet_write_csr(dev, 0, 0x0001); /* start */
410 /* Wait for Init Done bit */
411 for (i = 10000; i > 0; i--) {
412 if (pcnet_read_csr(dev, 0) & 0x0100)
417 printf("%s: TIMEOUT: controller init failed\n", dev->name);
423 * Finally start network controller operation.
425 pcnet_write_csr(dev, 0, 0x0002);
430 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
434 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
436 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
439 flush_dcache_range((unsigned long)packet,
440 (unsigned long)packet + pkt_len);
442 /* Wait for completion by testing the OWN bit */
443 for (i = 1000; i > 0; i--) {
444 status = readw(&entry->status);
445 if ((status & 0x8000) == 0)
451 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
452 dev->name, lp->cur_tx, status);
458 * Setup Tx ring. Caution: the write order is important here,
459 * set the status with the "ownership" bits last.
461 addr = pcnet_virt_to_mem(dev, packet);
462 writew(-pkt_len, &entry->length);
463 writel(0, &entry->misc);
464 writel(addr, &entry->base);
465 writew(0x8300, &entry->status);
467 /* Trigger an immediate send poll. */
468 pcnet_write_csr(dev, 0, 0x0008);
471 if (++lp->cur_tx >= TX_RING_SIZE)
474 PCNET_DEBUG2("done\n");
478 static int pcnet_recv (struct eth_device *dev)
480 struct pcnet_rx_head *entry;
483 u16 status, err_status;
486 entry = &lp->uc->rx_ring[lp->cur_rx];
488 * If we own the next entry, it's a new packet. Send it up.
490 status = readw(&entry->status);
491 if ((status & 0x8000) != 0)
493 err_status = status >> 8;
495 if (err_status != 0x03) { /* There was an error. */
496 printf("%s: Rx%d", dev->name, lp->cur_rx);
497 PCNET_DEBUG1(" (status=0x%x)", err_status);
498 if (err_status & 0x20)
500 if (err_status & 0x10)
502 if (err_status & 0x08)
504 if (err_status & 0x04)
510 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
512 printf("%s: Rx%d: invalid packet length %d\n",
513 dev->name, lp->cur_rx, pkt_len);
515 buf = lp->rx_buf[lp->cur_rx];
516 invalidate_dcache_range((unsigned long)buf,
517 (unsigned long)buf + pkt_len);
518 net_process_received_packet(buf, pkt_len);
519 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
520 lp->cur_rx, pkt_len, buf);
525 writew(status, &entry->status);
527 if (++lp->cur_rx >= RX_RING_SIZE)
533 static void pcnet_halt(struct eth_device *dev)
537 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
539 /* Reset the PCnet controller */
542 /* Wait for Stop bit */
543 for (i = 1000; i > 0; i--) {
544 if (pcnet_read_csr(dev, 0) & 0x4)
549 printf("%s: TIMEOUT: controller reset failed\n", dev->name);