1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
17 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
19 #define PCNET_DEBUG1(fmt,args...) \
20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
21 #define PCNET_DEBUG2(fmt,args...) \
22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
25 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
26 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
27 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
29 #define PCNET_LOG_TX_BUFFERS 0
30 #define PCNET_LOG_RX_BUFFERS 2
32 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
33 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
35 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
36 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
38 #define PKT_BUF_SZ 1544
40 /* The PCNET Rx and Tx ring descriptors. */
41 struct pcnet_rx_head {
49 struct pcnet_tx_head {
57 /* The PCNET 32-Bit initialization block, described in databook. */
58 struct pcnet_init_block {
64 /* Receive and transmit ring base, along with extra bits. */
70 struct pcnet_uncached_priv {
71 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
72 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
73 struct pcnet_init_block init_block;
76 typedef struct pcnet_priv {
77 struct pcnet_uncached_priv *uc;
78 /* Receive Buffer space */
79 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
84 static pcnet_priv_t *lp;
86 /* Offsets from base I/O address for WIO mode */
87 #define PCNET_RDP 0x10
88 #define PCNET_RAP 0x12
89 #define PCNET_RESET 0x14
90 #define PCNET_BDP 0x16
92 static u16 pcnet_read_csr(struct eth_device *dev, int index)
94 outw(index, dev->iobase + PCNET_RAP);
95 return inw(dev->iobase + PCNET_RDP);
98 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
100 outw(index, dev->iobase + PCNET_RAP);
101 outw(val, dev->iobase + PCNET_RDP);
104 static u16 pcnet_read_bcr(struct eth_device *dev, int index)
106 outw(index, dev->iobase + PCNET_RAP);
107 return inw(dev->iobase + PCNET_BDP);
110 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
112 outw(index, dev->iobase + PCNET_RAP);
113 outw(val, dev->iobase + PCNET_BDP);
116 static void pcnet_reset(struct eth_device *dev)
118 inw(dev->iobase + PCNET_RESET);
121 static int pcnet_check(struct eth_device *dev)
123 outw(88, dev->iobase + PCNET_RAP);
124 return inw(dev->iobase + PCNET_RAP) == 88;
127 static int pcnet_init (struct eth_device *dev, bd_t * bis);
128 static int pcnet_send(struct eth_device *dev, void *packet, int length);
129 static int pcnet_recv (struct eth_device *dev);
130 static void pcnet_halt (struct eth_device *dev);
131 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
133 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
136 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
137 void *virt_addr = addr;
139 return pci_virt_to_mem(devbusfn, virt_addr);
142 static struct pci_device_id supported[] = {
143 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
148 int pcnet_initialize(bd_t *bis)
151 struct eth_device *dev;
156 PCNET_DEBUG1("\npcnet_initialize...\n");
158 for (dev_nr = 0;; dev_nr++) {
161 * Find the PCnet PCI device(s).
163 devbusfn = pci_find_devices(supported, dev_nr);
168 * Allocate and pre-fill the device structure.
170 dev = (struct eth_device *)malloc(sizeof(*dev));
172 printf("pcnet: Can not allocate memory\n");
175 memset(dev, 0, sizeof(*dev));
176 dev->priv = (void *)(unsigned long)devbusfn;
177 sprintf(dev->name, "pcnet#%d", dev_nr);
180 * Setup the PCI device.
182 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
183 dev->iobase = pci_io_to_phys(devbusfn, bar);
186 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
187 dev->name, devbusfn, (unsigned long)dev->iobase);
189 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
190 pci_write_config_word(devbusfn, PCI_COMMAND, command);
191 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
192 if ((status & command) != command) {
193 printf("%s: Couldn't enable IO access or Bus Mastering\n",
199 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
202 * Probe the PCnet chip.
204 if (pcnet_probe(dev, bis, dev_nr) < 0) {
210 * Setup device structure and register the driver.
212 dev->init = pcnet_init;
213 dev->halt = pcnet_halt;
214 dev->send = pcnet_send;
215 dev->recv = pcnet_recv;
225 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
230 #ifdef PCNET_HAS_PROM
234 /* Reset the PCnet controller */
237 /* Check if register access is working */
238 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
239 printf("%s: CSR register access check failed\n", dev->name);
243 /* Identify the chip */
245 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
246 if ((chip_version & 0xfff) != 0x003)
248 chip_version = (chip_version >> 12) & 0xffff;
249 switch (chip_version) {
251 chipname = "PCnet/PCI II 79C970A"; /* PCI */
254 chipname = "PCnet/FAST III 79C973"; /* PCI */
257 chipname = "PCnet/FAST III 79C975"; /* PCI */
260 printf("%s: PCnet version %#x not supported\n",
261 dev->name, chip_version);
265 PCNET_DEBUG1("AMD %s\n", chipname);
267 #ifdef PCNET_HAS_PROM
269 * In most chips, after a chip reset, the ethernet address is read from
270 * the station address PROM at the base address and programmed into the
271 * "Physical Address Registers" CSR12-14.
273 for (i = 0; i < 3; i++) {
276 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
277 /* There may be endianness issues here. */
278 dev->enetaddr[2 * i] = val & 0x0ff;
279 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
281 #endif /* PCNET_HAS_PROM */
286 static int pcnet_init(struct eth_device *dev, bd_t *bis)
288 struct pcnet_uncached_priv *uc;
292 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
294 /* Switch pcnet to 32bit mode */
295 pcnet_write_bcr(dev, 20, 2);
297 /* Set/reset autoselect bit */
298 val = pcnet_read_bcr(dev, 2) & ~2;
300 pcnet_write_bcr(dev, 2, val);
302 /* Enable auto negotiate, setup, disable fd */
303 val = pcnet_read_bcr(dev, 32) & ~0x98;
305 pcnet_write_bcr(dev, 32, val);
308 * Enable NOUFLO on supported controllers, with the transmit
309 * start point set to the full packet. This will cause entire
310 * packets to be buffered by the ethernet controller before
311 * transmission, eliminating underflows which are common on
312 * slower devices. Controllers which do not support NOUFLO will
313 * simply be left with a larger transmit FIFO threshold.
315 val = pcnet_read_bcr(dev, 18);
317 pcnet_write_bcr(dev, 18, val);
318 val = pcnet_read_csr(dev, 80);
320 pcnet_write_csr(dev, 80, val);
323 * We only maintain one structure because the drivers will never
324 * be used concurrently. In 32bit mode the RX and TX ring entries
325 * must be aligned on 16-byte boundaries.
328 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
329 addr = (addr + 0xf) & ~0xf;
330 lp = (pcnet_priv_t *)addr;
332 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
334 flush_dcache_range(addr, addr + sizeof(*lp->uc));
335 addr = UNCACHED_SDRAM(addr);
336 lp->uc = (struct pcnet_uncached_priv *)addr;
338 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
339 sizeof(*lp->rx_buf));
340 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
341 lp->rx_buf = (void *)addr;
346 uc->init_block.mode = cpu_to_le16(0x0000);
347 uc->init_block.filter[0] = 0x00000000;
348 uc->init_block.filter[1] = 0x00000000;
351 * Initialize the Rx ring.
354 for (i = 0; i < RX_RING_SIZE; i++) {
355 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
356 uc->rx_ring[i].base = cpu_to_le32(addr);
357 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
358 uc->rx_ring[i].status = cpu_to_le16(0x8000);
360 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
361 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
362 uc->rx_ring[i].status);
366 * Initialize the Tx ring. The Tx buffer address is filled in as
367 * needed, but we do need to clear the upper ownership bit.
370 for (i = 0; i < TX_RING_SIZE; i++) {
371 uc->tx_ring[i].base = 0;
372 uc->tx_ring[i].status = 0;
378 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
380 for (i = 0; i < 6; i++) {
381 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
382 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
385 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
387 addr = pcnet_virt_to_mem(dev, uc->rx_ring);
388 uc->init_block.rx_ring = cpu_to_le32(addr);
389 addr = pcnet_virt_to_mem(dev, uc->tx_ring);
390 uc->init_block.tx_ring = cpu_to_le32(addr);
392 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
393 uc->init_block.tlen_rlen,
394 uc->init_block.rx_ring, uc->init_block.tx_ring);
397 * Tell the controller where the Init Block is located.
400 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
401 pcnet_write_csr(dev, 1, addr & 0xffff);
402 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
404 pcnet_write_csr(dev, 4, 0x0915);
405 pcnet_write_csr(dev, 0, 0x0001); /* start */
407 /* Wait for Init Done bit */
408 for (i = 10000; i > 0; i--) {
409 if (pcnet_read_csr(dev, 0) & 0x0100)
414 printf("%s: TIMEOUT: controller init failed\n", dev->name);
420 * Finally start network controller operation.
422 pcnet_write_csr(dev, 0, 0x0002);
427 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
431 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
433 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
436 flush_dcache_range((unsigned long)packet,
437 (unsigned long)packet + pkt_len);
439 /* Wait for completion by testing the OWN bit */
440 for (i = 1000; i > 0; i--) {
441 status = readw(&entry->status);
442 if ((status & 0x8000) == 0)
448 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
449 dev->name, lp->cur_tx, status);
455 * Setup Tx ring. Caution: the write order is important here,
456 * set the status with the "ownership" bits last.
458 addr = pcnet_virt_to_mem(dev, packet);
459 writew(-pkt_len, &entry->length);
460 writel(0, &entry->misc);
461 writel(addr, &entry->base);
462 writew(0x8300, &entry->status);
464 /* Trigger an immediate send poll. */
465 pcnet_write_csr(dev, 0, 0x0008);
468 if (++lp->cur_tx >= TX_RING_SIZE)
471 PCNET_DEBUG2("done\n");
475 static int pcnet_recv (struct eth_device *dev)
477 struct pcnet_rx_head *entry;
480 u16 status, err_status;
483 entry = &lp->uc->rx_ring[lp->cur_rx];
485 * If we own the next entry, it's a new packet. Send it up.
487 status = readw(&entry->status);
488 if ((status & 0x8000) != 0)
490 err_status = status >> 8;
492 if (err_status != 0x03) { /* There was an error. */
493 printf("%s: Rx%d", dev->name, lp->cur_rx);
494 PCNET_DEBUG1(" (status=0x%x)", err_status);
495 if (err_status & 0x20)
497 if (err_status & 0x10)
499 if (err_status & 0x08)
501 if (err_status & 0x04)
507 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
509 printf("%s: Rx%d: invalid packet length %d\n",
510 dev->name, lp->cur_rx, pkt_len);
512 buf = (*lp->rx_buf)[lp->cur_rx];
513 invalidate_dcache_range((unsigned long)buf,
514 (unsigned long)buf + pkt_len);
515 net_process_received_packet(buf, pkt_len);
516 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
517 lp->cur_rx, pkt_len, buf);
522 writew(status, &entry->status);
524 if (++lp->cur_rx >= RX_RING_SIZE)
530 static void pcnet_halt(struct eth_device *dev)
534 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
536 /* Reset the PCnet controller */
539 /* Wait for Stop bit */
540 for (i = 1000; i > 0; i--) {
541 if (pcnet_read_csr(dev, 0) & 0x4)
546 printf("%s: TIMEOUT: controller reset failed\n", dev->name);