1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
18 #include <asm/cache.h>
21 #include <linux/delay.h>
23 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
25 #define PCNET_DEBUG1(fmt,args...) \
26 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
27 #define PCNET_DEBUG2(fmt,args...) \
28 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
31 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
32 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
33 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
35 #define PCNET_LOG_TX_BUFFERS 0
36 #define PCNET_LOG_RX_BUFFERS 2
38 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
39 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
41 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
42 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
44 #define PKT_BUF_SZ 1544
46 /* The PCNET Rx and Tx ring descriptors. */
47 struct pcnet_rx_head {
55 struct pcnet_tx_head {
63 /* The PCNET 32-Bit initialization block, described in databook. */
64 struct pcnet_init_block {
70 /* Receive and transmit ring base, along with extra bits. */
76 struct pcnet_uncached_priv {
77 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
78 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
79 struct pcnet_init_block init_block;
80 } __aligned(ARCH_DMA_MINALIGN);
83 struct pcnet_uncached_priv ucp;
84 /* Receive Buffer space */
85 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
86 struct pcnet_uncached_priv *uc;
101 /* Offsets from base I/O address for WIO mode */
102 #define PCNET_RDP 0x10
103 #define PCNET_RAP 0x12
104 #define PCNET_RESET 0x14
105 #define PCNET_BDP 0x16
107 static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
109 writew(index, lp->iobase + PCNET_RAP);
110 return readw(lp->iobase + PCNET_RDP);
113 static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
115 writew(index, lp->iobase + PCNET_RAP);
116 writew(val, lp->iobase + PCNET_RDP);
119 static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
121 writew(index, lp->iobase + PCNET_RAP);
122 return readw(lp->iobase + PCNET_BDP);
125 static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
127 writew(index, lp->iobase + PCNET_RAP);
128 writew(val, lp->iobase + PCNET_BDP);
131 static void pcnet_reset(struct pcnet_priv *lp)
133 readw(lp->iobase + PCNET_RESET);
136 static int pcnet_check(struct pcnet_priv *lp)
138 writew(88, lp->iobase + PCNET_RAP);
139 return readw(lp->iobase + PCNET_RAP) == 88;
142 static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
144 void *virt_addr = addr;
147 return dm_pci_virt_to_mem(lp->dev, virt_addr);
149 return pci_virt_to_mem(lp->dev, virt_addr);
153 static struct pci_device_id supported[] = {
154 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
158 static int pcnet_probe_common(struct pcnet_priv *lp)
164 /* Reset the PCnet controller */
167 /* Check if register access is working */
168 if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
169 printf("%s: CSR register access check failed\n", lp->name);
173 /* Identify the chip */
174 chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
175 if ((chip_version & 0xfff) != 0x003)
177 chip_version = (chip_version >> 12) & 0xffff;
178 switch (chip_version) {
180 chipname = "PCnet/PCI II 79C970A"; /* PCI */
183 chipname = "PCnet/FAST III 79C973"; /* PCI */
186 chipname = "PCnet/FAST III 79C975"; /* PCI */
189 printf("%s: PCnet version %#x not supported\n",
190 lp->name, chip_version);
194 PCNET_DEBUG1("AMD %s\n", chipname);
197 * In most chips, after a chip reset, the ethernet address is read from
198 * the station address PROM at the base address and programmed into the
199 * "Physical Address Registers" CSR12-14.
201 for (i = 0; i < 3; i++) {
204 val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
205 /* There may be endianness issues here. */
206 lp->enetaddr[2 * i] = val & 0x0ff;
207 lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
213 static int pcnet_init_common(struct pcnet_priv *lp)
215 struct pcnet_uncached_priv *uc;
219 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
221 /* Switch pcnet to 32bit mode */
222 pcnet_write_bcr(lp, 20, 2);
224 /* Set/reset autoselect bit */
225 val = pcnet_read_bcr(lp, 2) & ~2;
227 pcnet_write_bcr(lp, 2, val);
229 /* Enable auto negotiate, setup, disable fd */
230 val = pcnet_read_bcr(lp, 32) & ~0x98;
232 pcnet_write_bcr(lp, 32, val);
235 * Enable NOUFLO on supported controllers, with the transmit
236 * start point set to the full packet. This will cause entire
237 * packets to be buffered by the ethernet controller before
238 * transmission, eliminating underflows which are common on
239 * slower devices. Controllers which do not support NOUFLO will
240 * simply be left with a larger transmit FIFO threshold.
242 val = pcnet_read_bcr(lp, 18);
244 pcnet_write_bcr(lp, 18, val);
245 val = pcnet_read_csr(lp, 80);
247 pcnet_write_csr(lp, 80, val);
251 uc->init_block.mode = cpu_to_le16(0x0000);
252 uc->init_block.filter[0] = 0x00000000;
253 uc->init_block.filter[1] = 0x00000000;
256 * Initialize the Rx ring.
259 for (i = 0; i < RX_RING_SIZE; i++) {
260 addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
261 uc->rx_ring[i].base = cpu_to_le32(addr);
262 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
263 uc->rx_ring[i].status = cpu_to_le16(0x8000);
265 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
266 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
267 uc->rx_ring[i].status);
271 * Initialize the Tx ring. The Tx buffer address is filled in as
272 * needed, but we do need to clear the upper ownership bit.
275 for (i = 0; i < TX_RING_SIZE; i++) {
276 uc->tx_ring[i].base = 0;
277 uc->tx_ring[i].status = 0;
283 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
285 for (i = 0; i < 6; i++) {
286 lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
287 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
290 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
292 addr = pcnet_virt_to_mem(lp, uc->rx_ring);
293 uc->init_block.rx_ring = cpu_to_le32(addr);
294 addr = pcnet_virt_to_mem(lp, uc->tx_ring);
295 uc->init_block.tx_ring = cpu_to_le32(addr);
297 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
298 uc->init_block.tlen_rlen,
299 uc->init_block.rx_ring, uc->init_block.tx_ring);
302 * Tell the controller where the Init Block is located.
305 addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
306 pcnet_write_csr(lp, 1, addr & 0xffff);
307 pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
309 pcnet_write_csr(lp, 4, 0x0915);
310 pcnet_write_csr(lp, 0, 0x0001); /* start */
312 /* Wait for Init Done bit */
313 for (i = 10000; i > 0; i--) {
314 if (pcnet_read_csr(lp, 0) & 0x0100)
319 printf("%s: TIMEOUT: controller init failed\n", lp->name);
325 * Finally start network controller operation.
327 pcnet_write_csr(lp, 0, 0x0002);
332 static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
336 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
338 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
341 flush_dcache_range((unsigned long)packet,
342 (unsigned long)packet + pkt_len);
344 /* Wait for completion by testing the OWN bit */
345 for (i = 1000; i > 0; i--) {
346 status = readw(&entry->status);
347 if ((status & 0x8000) == 0)
353 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
354 lp->name, lp->cur_tx, status);
360 * Setup Tx ring. Caution: the write order is important here,
361 * set the status with the "ownership" bits last.
363 addr = pcnet_virt_to_mem(lp, packet);
364 writew(-pkt_len, &entry->length);
365 writel(0, &entry->misc);
366 writel(addr, &entry->base);
367 writew(0x8300, &entry->status);
369 /* Trigger an immediate send poll. */
370 pcnet_write_csr(lp, 0, 0x0008);
373 if (++lp->cur_tx >= TX_RING_SIZE)
376 PCNET_DEBUG2("done\n");
380 static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
382 struct pcnet_rx_head *entry;
387 entry = &lp->uc->rx_ring[lp->cur_rx];
389 * If we own the next entry, it's a new packet. Send it up.
391 lp->status = readw(&entry->status);
392 if ((lp->status & 0x8000) != 0)
394 err_status = lp->status >> 8;
396 if (err_status != 0x03) { /* There was an error. */
397 printf("%s: Rx%d", lp->name, lp->cur_rx);
398 PCNET_DEBUG1(" (status=0x%x)", err_status);
399 if (err_status & 0x20)
401 if (err_status & 0x10)
403 if (err_status & 0x08)
405 if (err_status & 0x04)
408 lp->status &= 0x03ff;
412 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
414 printf("%s: Rx%d: invalid packet length %d\n",
415 lp->name, lp->cur_rx, pkt_len);
419 *bufp = lp->rx_buf[lp->cur_rx];
420 invalidate_dcache_range((unsigned long)*bufp,
421 (unsigned long)*bufp + pkt_len);
423 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
424 lp->cur_rx, pkt_len, buf);
429 static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
431 struct pcnet_rx_head *entry;
433 entry = &lp->uc->rx_ring[lp->cur_rx];
435 lp->status |= 0x8000;
436 writew(lp->status, &entry->status);
438 if (++lp->cur_rx >= RX_RING_SIZE)
442 static void pcnet_halt_common(struct pcnet_priv *lp)
446 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
448 /* Reset the PCnet controller */
451 /* Wait for Stop bit */
452 for (i = 1000; i > 0; i--) {
453 if (pcnet_read_csr(lp, 0) & 0x4)
458 printf("%s: TIMEOUT: controller reset failed\n", lp->name);
461 #ifndef CONFIG_DM_ETH
462 static int pcnet_init(struct eth_device *dev, struct bd_info *bis)
464 struct pcnet_priv *lp = dev->priv;
466 return pcnet_init_common(lp);
469 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
471 struct pcnet_priv *lp = dev->priv;
473 return pcnet_send_common(lp, packet, pkt_len);
476 static int pcnet_recv(struct eth_device *dev)
478 struct pcnet_priv *lp = dev->priv;
482 ret = pcnet_recv_common(lp, &packet);
484 net_process_received_packet(packet, ret);
486 pcnet_free_pkt_common(lp, ret);
491 static void pcnet_halt(struct eth_device *dev)
493 struct pcnet_priv *lp = dev->priv;
495 pcnet_halt_common(lp);
498 int pcnet_initialize(struct bd_info *bis)
501 struct eth_device *dev;
502 struct pcnet_priv *lp;
507 PCNET_DEBUG1("\n%s...\n", __func__);
509 for (dev_nr = 0; ; dev_nr++) {
511 * Find the PCnet PCI device(s).
513 devbusfn = pci_find_devices(supported, dev_nr);
518 * Allocate and pre-fill the device structure.
520 dev = calloc(1, sizeof(*dev));
522 printf("pcnet: Can not allocate memory\n");
527 * We only maintain one structure because the drivers will
528 * never be used concurrently. In 32bit mode the RX and TX
529 * ring entries must be aligned on 16-byte boundaries.
531 lp = malloc_cache_aligned(sizeof(*lp));
532 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
533 sizeof(lp->ucp), MAP_NOCACHE);
535 flush_dcache_range((unsigned long)lp,
536 (unsigned long)lp + sizeof(*lp));
538 sprintf(dev->name, "pcnet#%d", dev_nr);
539 lp->name = dev->name;
540 lp->enetaddr = dev->enetaddr;
543 * Setup the PCI device.
545 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
546 lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
548 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
549 lp->name, devbusfn, lp->iobase);
551 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
552 pci_write_config_word(devbusfn, PCI_COMMAND, command);
553 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
554 if ((status & command) != command) {
555 printf("%s: Couldn't enable IO access or Bus Mastering\n",
561 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
564 * Probe the PCnet chip.
566 if (pcnet_probe_common(lp) < 0) {
572 * Setup device structure and register the driver.
574 dev->init = pcnet_init;
575 dev->halt = pcnet_halt;
576 dev->send = pcnet_send;
577 dev->recv = pcnet_recv;
587 static int pcnet_start(struct udevice *dev)
589 struct eth_pdata *plat = dev_get_platdata(dev);
590 struct pcnet_priv *priv = dev_get_priv(dev);
592 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
594 return pcnet_init_common(priv);
597 static void pcnet_stop(struct udevice *dev)
599 struct pcnet_priv *priv = dev_get_priv(dev);
601 pcnet_halt_common(priv);
604 static int pcnet_send(struct udevice *dev, void *packet, int length)
606 struct pcnet_priv *priv = dev_get_priv(dev);
609 ret = pcnet_send_common(priv, packet, length);
611 return ret ? 0 : -ETIMEDOUT;
614 static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
616 struct pcnet_priv *priv = dev_get_priv(dev);
618 return pcnet_recv_common(priv, packetp);
621 static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
623 struct pcnet_priv *priv = dev_get_priv(dev);
625 pcnet_free_pkt_common(priv, length);
630 static int pcnet_bind(struct udevice *dev)
632 static int card_number;
635 sprintf(name, "pcnet#%u", card_number++);
637 return device_set_name(dev, name);
640 static int pcnet_probe(struct udevice *dev)
642 struct eth_pdata *plat = dev_get_platdata(dev);
643 struct pcnet_priv *lp = dev_get_priv(dev);
648 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
651 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
652 sizeof(lp->ucp), MAP_NOCACHE);
654 lp->name = dev->name;
655 lp->enetaddr = plat->enetaddr;
656 lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
658 flush_dcache_range((unsigned long)lp,
659 (unsigned long)lp + sizeof(*lp));
661 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
662 dm_pci_write_config16(dev, PCI_COMMAND, command);
663 dm_pci_read_config16(dev, PCI_COMMAND, &status);
664 if ((status & command) != command) {
665 printf("%s: Couldn't enable IO access or Bus Mastering\n",
670 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
672 ret = pcnet_probe_common(lp);
679 static const struct eth_ops pcnet_ops = {
680 .start = pcnet_start,
684 .free_pkt = pcnet_free_pkt,
687 U_BOOT_DRIVER(eth_pcnet) = {
691 .probe = pcnet_probe,
693 .priv_auto_alloc_size = sizeof(struct pcnet_priv),
694 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
695 .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
698 U_BOOT_PCI_DEVICE(eth_pcnet, supported);