2 * @file IxQMgrAqmIf_p.h
4 * @author Intel Corporation
7 * @brief The IxQMgrAqmIf sub-component provides a number of inline
8 * functions for performing I/O on the AQM.
10 * Because some functions contained in this module are inline and are
11 * used in other modules (within the QMgr component) the definitions are
12 * contained in this header file. The "normal" use of inline functions
13 * is to use the inline functions in the module in which they are
14 * defined. In this case these inline functions are used in external
15 * modules and therefore the use of "inline extern". What this means
16 * is as follows: if a function foo is declared as "inline extern"this
17 * definition is only used for inlining, in no case is the function
18 * compiled on its own. If the compiler cannot inline the function it
19 * becomes an external reference. Therefore in IxQMgrAqmIf.c all
20 * inline functions are defined without the "inline extern" specifier
21 * and so define the external references. In all other modules these
22 * funtions are defined as "inline extern".
26 * IXP400 SW Release version 2.0
28 * -- Copyright Notice --
31 * Copyright 2001-2005, Intel Corporation.
32 * All rights reserved.
35 * SPDX-License-Identifier: BSD-3-Clause
37 * -- End of Copyright Notice --
40 #ifndef IXQMGRAQMIF_P_H
41 #define IXQMGRAQMIF_P_H
43 #include "IxOsalTypes.h"
49 #ifdef IX_OSAL_INLINE_ALL
50 /* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
52 #define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
55 #ifndef IX_QMGR_AQMIF_INLINE
56 #define IX_QMGR_AQMIF_INLINE
59 #ifndef IX_QMGR_AQMIF_INLINE
60 #define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
62 #endif /* IXQMGRAQMIF_C */
63 #endif /* IX_OSAL_INLINE */
67 * User defined include files.
70 #include "IxQMgrLog_p.h"
71 #include "IxQMgrQCfg_p.h"
73 /* Because this file contains inline functions which will be compiled into
74 * other components, we need to ensure that the IX_COMPONENT_NAME define
75 * is set to ix_qmgr while this code is being compiled. This will ensure
76 * that the correct implementation is provided for the memory access macros
77 * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
78 * This must be done before including "IxOsalMemAccess.h"
80 #define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
81 #undef IX_COMPONENT_NAME
82 #define IX_COMPONENT_NAME ix_qmgr
86 * #defines and macros used in this file.
89 /* Number of bytes per word */
90 #define IX_QMGR_NUM_BYTES_PER_WORD 4
92 /* Underflow bit mask */
93 #define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0
95 /* Overflow bit mask */
96 #define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1
98 /* Queue access register, queue 0 */
99 #define IX_QMGR_QUEACC0_OFFSET 0x0000
101 /* Size of queue access register in words */
102 #define IX_QMGR_QUEACC_SIZE 0x4/*words*/
104 /* Queue status register, queues 0-7 */
105 #define IX_QMGR_QUELOWSTAT0_OFFSET (IX_QMGR_QUEACC0_OFFSET +\
106 (IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
108 /* Queue status register, queues 8-15 */
109 #define IX_QMGR_QUELOWSTAT1_OFFSET (IX_QMGR_QUELOWSTAT0_OFFSET +\
110 IX_QMGR_NUM_BYTES_PER_WORD)
112 /* Queue status register, queues 16-23 */
113 #define IX_QMGR_QUELOWSTAT2_OFFSET (IX_QMGR_QUELOWSTAT1_OFFSET +\
114 IX_QMGR_NUM_BYTES_PER_WORD)
116 /* Queue status register, queues 24-31 */
117 #define IX_QMGR_QUELOWSTAT3_OFFSET (IX_QMGR_QUELOWSTAT2_OFFSET +\
118 IX_QMGR_NUM_BYTES_PER_WORD)
120 /* Queue status register Q status bits mask */
121 #define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
123 /* Size of queue 0-31 status register */
124 #define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/
126 /* The number of queues' status specified per word */
127 #define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
129 /* Queue UF/OF status register queues 0-15 */
130 #define IX_QMGR_QUEUOSTAT0_OFFSET (IX_QMGR_QUELOWSTAT3_OFFSET +\
131 IX_QMGR_NUM_BYTES_PER_WORD)
132 /* Queue UF/OF status register queues 16-31 */
133 #define IX_QMGR_QUEUOSTAT1_OFFSET (IX_QMGR_QUEUOSTAT0_OFFSET +\
134 IX_QMGR_NUM_BYTES_PER_WORD)
136 /* The number of queues' underflow/overflow status specified per word */
137 #define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
139 /* Queue NE status register, queues 32-63 */
140 #define IX_QMGR_QUEUPPSTAT0_OFFSET (IX_QMGR_QUEUOSTAT1_OFFSET +\
141 IX_QMGR_NUM_BYTES_PER_WORD)
143 /* Queue F status register, queues 32-63 */
144 #define IX_QMGR_QUEUPPSTAT1_OFFSET (IX_QMGR_QUEUPPSTAT0_OFFSET +\
145 IX_QMGR_NUM_BYTES_PER_WORD)
147 /* Size of queue 32-63 status register */
148 #define IX_QMGR_QUEUPPSTAT_SIZE 0x2 /*words*/
150 /* The number of queues' status specified per word */
151 #define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
153 /* Queue INT source select register, queues 0-7 */
154 #define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET +\
155 IX_QMGR_NUM_BYTES_PER_WORD)
157 /* Queue INT source select register, queues 8-15 */
158 #define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
159 IX_QMGR_NUM_BYTES_PER_WORD)
161 /* Queue INT source select register, queues 16-23 */
162 #define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
163 IX_QMGR_NUM_BYTES_PER_WORD)
165 /* Queue INT source select register, queues 24-31 */
166 #define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
167 IX_QMGR_NUM_BYTES_PER_WORD)
169 /* Size of interrupt source select reegister */
170 #define IX_QMGR_INT0SRCSELREG_SIZE 0x4 /*words*/
172 /* The number of queues' interrupt source select specified per word*/
173 #define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
175 /* Queue INT enable register, queues 0-31 */
176 #define IX_QMGR_QUEIEREG0_OFFSET (IX_QMGR_INT0SRCSELREG3_OFFSET +\
177 IX_QMGR_NUM_BYTES_PER_WORD)
179 /* Queue INT enable register, queues 32-63 */
180 #define IX_QMGR_QUEIEREG1_OFFSET (IX_QMGR_QUEIEREG0_OFFSET +\
181 IX_QMGR_NUM_BYTES_PER_WORD)
183 /* Queue INT register, queues 0-31 */
184 #define IX_QMGR_QINTREG0_OFFSET (IX_QMGR_QUEIEREG1_OFFSET +\
185 IX_QMGR_NUM_BYTES_PER_WORD)
187 /* Queue INT register, queues 32-63 */
188 #define IX_QMGR_QINTREG1_OFFSET (IX_QMGR_QINTREG0_OFFSET +\
189 IX_QMGR_NUM_BYTES_PER_WORD)
191 /* Size of interrupt register */
192 #define IX_QMGR_QINTREG_SIZE 0x2 /*words*/
194 /* Number of queues' status specified per word */
195 #define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
197 /* Number of bits per queue interrupt status */
198 #define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
199 #define IX_QMGR_QINTREG_BIT_OFFSET 0x1
201 /* Size of address space not used by AQM */
202 #define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES 0x1bC0
204 /* Queue config register, queue 0 */
205 #define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
206 IX_QMGR_NUM_BYTES_PER_WORD +\
207 IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
209 /* Total size of configuration words */
210 #define IX_QMGR_QUECONFIG_SIZE 0x100
212 /* Start of SRAM queue buffer space */
213 #define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
214 IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
216 /* Total bits in a word */
217 #define BITS_PER_WORD 32
219 /* Size of queue buffer space */
220 #define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
223 * This macro will return the address of the access register for the
224 * queue specified by qId
226 #define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
227 (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
228 + IX_QMGR_QUEACC0_OFFSET)
231 * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
232 * sticky interrupt register.
234 #define IX_QMGR_INT0SRCSELREG0_BIT3 3
237 * Variable declerations global to this file. Externs are followed by
240 extern UINT32 aqmBaseAddress;
243 * Function declarations.
246 ixQMgrAqmIfInit (void);
249 ixQMgrAqmIfUninit (void);
252 ixQMgrAqmIfLog2 (unsigned number);
255 ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId,
256 UINT32 registerBaseAddrOffset,
257 unsigned queuesPerRegWord,
261 ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
262 IxQMgrSourceId srcSel,
263 unsigned int *statusWordOffset,
267 * The Xscale software allways deals with logical addresses and so the
268 * base address of the AQM memory space is not a hardcoded value. This
269 * function must be called before any other function in this component.
270 * NO CHECKING is performed to ensure that the base address has been
274 ixQMgrAqmIfBaseAddressSet (UINT32 address);
277 * Get the base address of the AQM memory space.
280 ixQMgrAqmIfBaseAddressGet (UINT32 *address);
283 * Get the sram base address
286 ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
289 * Read a queue status
292 ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
293 IxQMgrQStatus* status);
297 * Set INT0SRCSELREG0 Bit3
299 void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
303 * Set the interrupt source
306 ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
307 IxQMgrSourceId sourceId);
310 * Enable interruptson a queue
313 ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
316 * Disable interrupt on a quee
319 ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
322 * Write the config register of the specified queue
325 ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
326 IxQMgrQSizeInWords qSizeInWords,
327 IxQMgrQEntrySizeInWords entrySizeInWords,
328 UINT32 freeSRAMAddress);
331 * read fields from the config of the specified queue.
334 ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
335 unsigned int numEntries,
343 * Set the ne and nf watermark level on a queue.
346 ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
350 /* Inspect an entry without moving the read pointer */
352 ixQMgrAqmIfQPeek (IxQMgrQId qId,
353 unsigned int entryIndex,
354 unsigned int *entry);
356 /* Modify an entry without moving the write pointer */
358 ixQMgrAqmIfQPoke (IxQMgrQId qId,
359 unsigned int entryIndex,
360 unsigned int *entry);
363 * Function prototype for inline functions. For description refers to
364 * the functions defintion below.
366 IX_QMGR_AQMIF_INLINE void
367 ixQMgrAqmIfWordWrite (VUINT32 *address,
370 IX_QMGR_AQMIF_INLINE void
371 ixQMgrAqmIfWordRead (VUINT32 *address,
374 IX_QMGR_AQMIF_INLINE void
375 ixQMgrAqmIfQPop (IxQMgrQId qId,
376 IxQMgrQEntrySizeInWords numWords,
379 IX_QMGR_AQMIF_INLINE void
380 ixQMgrAqmIfQPush (IxQMgrQId qId,
381 IxQMgrQEntrySizeInWords numWords,
384 IX_QMGR_AQMIF_INLINE void
385 ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
386 UINT32 *qStatusWords);
388 IX_QMGR_AQMIF_INLINE BOOL
389 ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
390 UINT32 *newQStatusWords,
391 unsigned int statusWordOffset,
395 IX_QMGR_AQMIF_INLINE BOOL
396 ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
397 UINT32 registerBaseAddrOffset,
398 unsigned queuesPerRegWord,
399 unsigned relativeBitOffset,
402 IX_QMGR_AQMIF_INLINE BOOL
403 ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
405 IX_QMGR_AQMIF_INLINE BOOL
406 ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
408 IX_QMGR_AQMIF_INLINE UINT32
409 ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
410 UINT32 registerBaseAddrOffset,
411 unsigned queuesPerRegWord);
412 IX_QMGR_AQMIF_INLINE void
413 ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
415 IX_QMGR_AQMIF_INLINE void
416 ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
419 IX_QMGR_AQMIF_INLINE void
420 ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
421 IxQMgrQStatus *status);
423 IX_QMGR_AQMIF_INLINE void
424 ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
425 IxQMgrQStatus *status);
427 IX_QMGR_AQMIF_INLINE void
428 ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
429 IxQMgrQStatus *qStatus);
431 IX_QMGR_AQMIF_INLINE unsigned
432 ixQMgrAqmIfPow2NumDivide (unsigned numerator,
433 unsigned denominator);
435 IX_QMGR_AQMIF_INLINE void
436 ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
443 * This inline function is used by other QMgr components to write one
444 * word to the specified address.
446 IX_QMGR_AQMIF_INLINE void
447 ixQMgrAqmIfWordWrite (VUINT32 *address,
450 IX_OSAL_WRITE_LONG(address, word);
454 * This inline function is used by other QMgr components to read a
455 * word from the specified address.
457 IX_QMGR_AQMIF_INLINE void
458 ixQMgrAqmIfWordRead (VUINT32 *address,
461 *word = IX_OSAL_READ_LONG(address);
466 * This inline function is used by other QMgr components to pop an
467 * entry off the specified queue.
469 IX_QMGR_AQMIF_INLINE void
470 ixQMgrAqmIfQPop (IxQMgrQId qId,
471 IxQMgrQEntrySizeInWords numWords,
474 volatile UINT32 *accRegAddr;
476 accRegAddr = (UINT32*)(aqmBaseAddress +
477 IX_QMGR_Q_ACCESS_ADDR_GET(qId));
481 case IX_QMGR_Q_ENTRY_SIZE1:
482 ixQMgrAqmIfWordRead (accRegAddr, entry);
484 case IX_QMGR_Q_ENTRY_SIZE2:
485 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
486 ixQMgrAqmIfWordRead (accRegAddr, entry);
488 case IX_QMGR_Q_ENTRY_SIZE4:
489 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
490 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
491 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
492 ixQMgrAqmIfWordRead (accRegAddr, entry);
495 IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
501 * This inline function is used by other QMgr components to push an
502 * entry to the specified queue.
504 IX_QMGR_AQMIF_INLINE void
505 ixQMgrAqmIfQPush (IxQMgrQId qId,
506 IxQMgrQEntrySizeInWords numWords,
509 volatile UINT32 *accRegAddr;
511 accRegAddr = (UINT32*)(aqmBaseAddress +
512 IX_QMGR_Q_ACCESS_ADDR_GET(qId));
516 case IX_QMGR_Q_ENTRY_SIZE1:
517 ixQMgrAqmIfWordWrite (accRegAddr, *entry);
519 case IX_QMGR_Q_ENTRY_SIZE2:
520 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
521 ixQMgrAqmIfWordWrite (accRegAddr, *entry);
523 case IX_QMGR_Q_ENTRY_SIZE4:
524 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
525 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
526 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
527 ixQMgrAqmIfWordWrite (accRegAddr, *entry);
530 IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
536 * The AQM interrupt registers contains a bit for each AQM queue
537 * specifying the queue (s) that cause an interrupt to fire. This
538 * function is called by IxQMGrDispatcher component.
540 IX_QMGR_AQMIF_INLINE void
541 ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
542 UINT32 *qStatusWords)
544 volatile UINT32 *regAddress = NULL;
546 if (group == IX_QMGR_QUELOW_GROUP)
548 regAddress = (UINT32*)(aqmBaseAddress +
549 IX_QMGR_QUELOWSTAT0_OFFSET);
551 ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
552 ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
553 ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
554 ixQMgrAqmIfWordRead (regAddress, qStatusWords);
556 else /* We have the upper queues */
558 /* Only need to read the Nearly Empty status register for
559 * queues 32-63 as for therse queues the interrtupt source
560 * condition is fixed to Nearly Empty
562 regAddress = (UINT32*)(aqmBaseAddress +
563 IX_QMGR_QUEUPPSTAT0_OFFSET);
564 ixQMgrAqmIfWordRead (regAddress, qStatusWords);
570 * This function check if the status for a queue has changed between
571 * 2 snapshots and if it has, that the status matches a particular
572 * value after masking.
574 IX_QMGR_AQMIF_INLINE BOOL
575 ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
576 UINT32 *newQStatusWords,
577 unsigned int statusWordOffset,
581 if (((oldQStatusWords[statusWordOffset] & mask) !=
582 (newQStatusWords[statusWordOffset] & mask)) &&
583 ((newQStatusWords[statusWordOffset] & mask) == checkValue))
592 * The AQM interrupt register contains a bit for each AQM queue
593 * specifying the queue (s) that cause an interrupt to fire. This
594 * function is called by IxQMgrDispatcher component.
596 IX_QMGR_AQMIF_INLINE void
597 ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
600 volatile UINT32 *regAddress;
602 if (group == IX_QMGR_QUELOW_GROUP)
604 regAddress = (UINT32*)(aqmBaseAddress +
605 IX_QMGR_QINTREG0_OFFSET);
609 regAddress = (UINT32*)(aqmBaseAddress +
610 IX_QMGR_QINTREG1_OFFSET);
613 ixQMgrAqmIfWordRead (regAddress, regVal);
617 * The AQM interrupt enable register contains a bit for each AQM queue.
618 * This function reads the interrupt enable register. This
619 * function is called by IxQMgrDispatcher component.
621 IX_QMGR_AQMIF_INLINE void
622 ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
625 volatile UINT32 *regAddress;
627 if (group == IX_QMGR_QUELOW_GROUP)
629 regAddress = (UINT32*)(aqmBaseAddress +
630 IX_QMGR_QUEIEREG0_OFFSET);
634 regAddress = (UINT32*)(aqmBaseAddress +
635 IX_QMGR_QUEIEREG1_OFFSET);
638 ixQMgrAqmIfWordRead (regAddress, regVal);
643 * This inline function will read the status bit of a queue
644 * specified by qId. If reset is true the bit is cleared.
646 IX_QMGR_AQMIF_INLINE BOOL
647 ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
648 UINT32 registerBaseAddrOffset,
649 unsigned queuesPerRegWord,
650 unsigned relativeBitOffset,
653 UINT32 actualBitOffset;
654 volatile UINT32 *registerAddress;
658 * Calculate the registerAddress
659 * multiple queues split accross registers
661 registerAddress = (UINT32*)(aqmBaseAddress +
662 registerBaseAddrOffset +
663 ((qId / queuesPerRegWord) *
664 IX_QMGR_NUM_BYTES_PER_WORD));
667 * Get the status word
669 ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
672 * Calculate the actualBitOffset
673 * status for multiple queues stored in one register
675 actualBitOffset = (relativeBitOffset + 1) <<
676 ((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
678 /* Check if the status bit is set */
679 if (registerWord & actualBitOffset)
681 /* Clear the bit if reset */
684 ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
695 * @ingroup IxQmgrAqmIfAPI
697 * @brief Read the underflow status of a queue
699 * This inline function will read the underflow status of a queue
703 IX_QMGR_AQMIF_INLINE BOOL
704 ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
706 if (qId < IX_QMGR_MIN_QUEUPP_QID)
708 return (ixQMgrAqmIfRegisterBitCheck (qId,
709 IX_QMGR_QUEUOSTAT0_OFFSET,
710 IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
711 IX_QMGR_UNDERFLOW_BIT_OFFSET,
716 /* Qs 32-63 have no underflow status */
722 * This inline function will read the overflow status of a queue
725 IX_QMGR_AQMIF_INLINE BOOL
726 ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
728 if (qId < IX_QMGR_MIN_QUEUPP_QID)
730 return (ixQMgrAqmIfRegisterBitCheck (qId,
731 IX_QMGR_QUEUOSTAT0_OFFSET,
732 IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
733 IX_QMGR_OVERFLOW_BIT_OFFSET,
738 /* Qs 32-63 have no overflow status */
744 * This inline function will read the status bits of a queue
747 IX_QMGR_AQMIF_INLINE UINT32
748 ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
749 UINT32 registerBaseAddrOffset,
750 unsigned queuesPerRegWord)
752 volatile UINT32 *registerAddress;
754 UINT32 statusBitsMask;
757 bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
760 * Calculate the registerAddress
761 * multiple queues split accross registers
763 registerAddress = (UINT32*)(aqmBaseAddress +
764 registerBaseAddrOffset +
765 ((qId / queuesPerRegWord) *
766 IX_QMGR_NUM_BYTES_PER_WORD));
768 * Read the status word
770 ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
774 * Calculate the mask for the status bits for this queue.
776 statusBitsMask = ((1 << bitsPerQueue) - 1);
779 * Shift the status word so it is right justified
781 registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
784 * Mask out all bar the status bits for this queue
786 return (registerWord &= statusBitsMask);
790 * This function is called by IxQMgrDispatcher to set the contents of
791 * the AQM interrupt register.
793 IX_QMGR_AQMIF_INLINE void
794 ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
797 volatile UINT32 *address;
799 if (group == IX_QMGR_QUELOW_GROUP)
801 address = (UINT32*)(aqmBaseAddress +
802 IX_QMGR_QINTREG0_OFFSET);
806 address = (UINT32*)(aqmBaseAddress +
807 IX_QMGR_QINTREG1_OFFSET);
810 ixQMgrAqmIfWordWrite (address, reg);
814 * Read the status of a queue in the range 0-31.
816 * This function is used by other QMgr components to read the
817 * status of the queue specified by qId.
819 IX_QMGR_AQMIF_INLINE void
820 ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
821 IxQMgrQStatus *status)
823 /* Read the general status bits */
824 *status = ixQMgrAqmIfQRegisterBitsRead (qId,
825 IX_QMGR_QUELOWSTAT0_OFFSET,
826 IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
830 * This function will read the status of the queue specified
833 IX_QMGR_AQMIF_INLINE void
834 ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
835 IxQMgrQStatus *status)
837 /* Reset the status bits */
841 * Check if the queue is nearly empty,
842 * N.b. QUPP stat register contains status for regs 32-63 at each
843 * bit position so subtract 32 to get bit offset
845 if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
846 IX_QMGR_QUEUPPSTAT0_OFFSET,
847 IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
848 0/*relativeBitOffset*/,
851 *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
855 * Check if the queue is full,
856 * N.b. QUPP stat register contains status for regs 32-63 at each
857 * bit position so subtract 32 to get bit offset
859 if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
860 IX_QMGR_QUEUPPSTAT1_OFFSET,
861 IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
862 0/*relativeBitOffset*/,
865 *status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
870 * This function is used by other QMgr components to read the
871 * status of the queue specified by qId.
873 IX_QMGR_AQMIF_INLINE void
874 ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
875 IxQMgrQStatus *qStatus)
877 if (qId < IX_QMGR_MIN_QUEUPP_QID)
879 ixQMgrAqmIfQueLowStatRead (qId, qStatus);
883 ixQMgrAqmIfQueUppStatRead (qId, qStatus);
889 * This function performs a mod division
891 IX_QMGR_AQMIF_INLINE unsigned
892 ixQMgrAqmIfPow2NumDivide (unsigned numerator,
893 unsigned denominator)
895 /* Number is evenly divisable by 2 */
896 return (numerator >> ixQMgrAqmIfLog2 (denominator));
899 /* Restore IX_COMPONENT_NAME */
900 #undef IX_COMPONENT_NAME
901 #define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
903 #endif/*IXQMGRAQMIF_P_H*/