1 #ifndef __doxygen_HIDE /* This file is not part of the API */
8 * @brief Header file for the IXP400 ATM NPE API
12 * IXP400 SW Release version 2.0
14 * -- Copyright Notice --
17 * Copyright 2001-2005, Intel Corporation.
18 * All rights reserved.
21 * SPDX-License-Identifier: BSD-3-Clause
23 * -- End of Copyright Notice --
27 * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
29 * @brief The Public API for the IXP400 NPE-A
39 #include "IxQueueAssignments.h"
41 /* General Message Ids */
46 * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
48 * @brief ATM Message ID command to write the data to the offset in the
49 * Utopia Configuration Table
51 #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE 0x20
54 * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
56 * @brief ATM Message ID command triggers the NPE to copy the Utopia
57 * Configuration Table to the Utopia coprocessor
59 #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD 0x21
62 * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
64 * @brief ATM Message ID command triggers the NPE to read-back the Utopia
65 * status registers and update the Utopia Status Table.
67 #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD 0x22
70 * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
72 * @brief ATM Message ID command to read the Utopia Status Table at the
75 #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ 0x23
78 * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
80 * @brief ATM Message ID command triggers the NPE to re-enable processing
81 * of any entries on the TxVcQ for this port.
83 * This command will be ignored for a port already enabled
85 #define IX_NPE_A_MSSG_ATM_TX_ENABLE 0x25
88 * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
90 * @brief ATM Message ID command triggers the NPE to disable processing on
93 * This command will be ignored for a port already disabled
95 #define IX_NPE_A_MSSG_ATM_TX_DISABLE 0x26
98 * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
100 * @brief ATM Message ID command triggers the NPE to process any received
101 * cells for this VC according to the VC Lookup Table.
103 * Re-issuing this command with different contents for a VC that is not
104 * disabled will cause unpredictable behavior.
106 #define IX_NPE_A_MSSG_ATM_RX_ENABLE 0x27
109 * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
111 * @brief ATM Message ID command triggers the NPE to disable processing for
114 * This command will be ignored for a VC already disabled
116 #define IX_NPE_A_MSSG_ATM_RX_DISABLE 0x28
119 * @def IX_NPE_A_MSSG_ATM_STATUS_READ
121 * @brief ATM Message ID command to read the ATM status. The data is returned via
124 #define IX_NPE_A_MSSG_ATM_STATUS_READ 0x29
126 /*--------------------------------------------------------------------------
128 *--------------------------------------------------------------------------*/
131 * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
133 * @brief HSS Message ID command writes the ConfigWord value to the location
134 * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
136 #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE 0x40
139 * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
141 * @brief HSS Message ID command triggers the NPE to copy the contents of the
142 * HSS Configuration Table to the appropriate configuration registers in the
143 * HSS coprocessor for the port specified by hPort.
145 #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD 0x41
148 * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
150 * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
151 * message for HSS port hPort.
153 #define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ 0x42
156 * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
158 * @brief HSS Message ID command triggers the NPE to reset internal status and
159 * enable the HssChannelized operation on the HSS port specified by hPort.
161 #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE 0x43
164 * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
166 * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
167 * operation on the HSS port specified by hPort.
169 #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE 0x44
172 * @def IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
174 * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
175 * port hPort. (n=hPort)
177 #define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE 0x45
180 * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
182 * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
183 * port hPort. (n=hPort)
185 #define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE 0x46
188 * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
190 * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
191 * port hPort. (n=hPort)
193 #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE 0x47
196 * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
198 * @brief HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and
199 * HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort)
201 #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE 0x48
204 * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
206 * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
207 * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values
208 * for HSS port hPort. (n=hPort)
210 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE 0x49
213 * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
214 * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
215 * port hPort. (n=hPort)
217 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE 0x4A
220 * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
222 * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
223 * port hPort. (n=hPort)
225 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE 0x4B
228 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
230 * @brief HSS Message ID command triggers the NPE to reset internal status and
231 * enable the HssPacketized operation for the flow specified by pPipe on
232 * the HSS port specified by hPort.
234 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE 0x50
237 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
238 * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
239 * operation for the flow specified by pPipe on the HSS port specified by hPort.
241 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE 0x51
244 * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
245 * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
246 * port hPort.(n=hPort)
248 #define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE 0x52
251 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
253 * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
254 * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
256 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
259 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
261 * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
262 * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
265 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE 0x54
268 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
270 * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
271 * for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
273 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
276 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
278 * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
279 * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
281 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE 0x56
284 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
286 * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
287 * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
289 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE 0x57
293 /* Queue Entry Masks */
295 /*--------------------------------------------------------------------------
296 * ATM Descriptor Structure offsets
297 *--------------------------------------------------------------------------*/
300 * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
302 * @brief ATM Descriptor structure offset for Receive Descriptor Status field
304 * It is used for descriptor error reporting.
306 #define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET 0
309 * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
311 * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
313 * It is used to hold an identifier number for this VC
315 #define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET 1
318 * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
320 * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
323 * Number of bytes the current mbuf data buffer can hold
325 #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET 2
328 * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
330 * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
332 #define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET 4
335 * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
337 * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
340 * RX - Initialized to zero. The NPE updates this field as each cell is received and
341 * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
343 #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET 12
346 * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
348 * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
350 * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
352 #define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET 14
355 * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
357 * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
359 * The current mbuf pointer of a chain of mbufs.
361 #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET 20
364 * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
366 * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
368 * Pointer to the next byte to be read or next free location to be written.
370 #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET 24
373 * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
375 * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
377 * Pointer to the next MBuf in a chain of MBufs.
379 #define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET 28
382 * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
384 * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
386 * Total number of bytes written to the chain of MBufs by the NPE
388 #define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET 32
391 * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
393 * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
395 * Current CRC value for a PDU
397 #define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
400 * @def IX_NPE_A_RXDESCRIPTOR_SIZE
402 * @brief ATM Descriptor structure offset for Receive Descriptor Size
404 * The size of the Receive descriptor
406 #define IX_NPE_A_RXDESCRIPTOR_SIZE 40
409 * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
411 * @brief ATM Descriptor structure offset for Transmit Descriptor Port
415 #define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET 0
418 * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
420 * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
422 #define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET 1
425 * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
427 * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
429 * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
430 * The NPE decrements this field for every transmitted cell. Thus, when the NPE writes a
431 * descriptor the TxDone queue, this field will equal zero.
433 #define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET 2
436 * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
437 * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
439 #define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET 4
442 * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
444 * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
446 #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET 8
449 * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
451 * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
453 * Pointer to the next byte to be read or next free location to be written.
455 #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET 12
458 * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
460 * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
462 #define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET 16
465 * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
467 * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
469 * Total number of bytes written to the chain of MBufs by the NPE
471 #define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET 20
474 * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
476 * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
478 * Current CRC value for a PDU
480 #define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
483 * @def IX_NPE_A_TXDESCRIPTOR_SIZE
485 * @brief ATM Descriptor structure offset for Transmit Descriptor Size
487 #define IX_NPE_A_TXDESCRIPTOR_SIZE 28
490 * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
492 * @brief Maximum number of chained MBufs that can be chained together
494 #define IX_NPE_A_CHAIN_DESC_COUNT_MAX 256
497 * Definition of the ATM cell header
499 * This would most conviently be defined as the bit field shown below.
500 * Endian portability prevents this, therefore a set of macros
501 * are defined to access the fields within the cell header assumed to
502 * be passed as a UINT32.
504 * Changes to field sizes or orders must be reflected in the offset
509 * unsigned int gfc:4;
510 * unsigned int vpi:8;
511 * unsigned int vci:16;
512 * unsigned int pti:3;
513 * unsigned int clp:1;
514 * } IxNpeA_AtmCellHeader;
518 /** Mask to acess GFC */
519 #define GFC_MASK 0xf0000000
521 /** return GFC from ATM cell header */
522 #define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
523 (((header) & GFC_MASK) >> 28)
525 /** set GFC into ATM cell header */
526 #define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
528 (header) &= ~GFC_MASK; \
529 (header) |= (((gfc) << 28) & GFC_MASK); \
532 /** Mask to acess VPI */
533 #define VPI_MASK 0x0ff00000
535 /** return VPI from ATM cell header */
536 #define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
537 (((header) & VPI_MASK) >> 20)
539 /** set VPI into ATM cell header */
540 #define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
542 (header) &= ~VPI_MASK; \
543 (header) |= (((vpi) << 20) & VPI_MASK); \
546 /** Mask to acess VCI */
547 #define VCI_MASK 0x000ffff0
549 /** return VCI from ATM cell header */
550 #define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
551 (((header) & VCI_MASK) >> 4)
553 /** set VCI into ATM cell header */
554 #define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
556 (header) &= ~VCI_MASK; \
557 (header) |= (((vci) << 4) & VCI_MASK); \
560 /** Mask to acess PTI */
561 #define PTI_MASK 0x0000000e
563 /** return PTI from ATM cell header */
564 #define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
565 (((header) & PTI_MASK) >> 1)
567 /** set PTI into ATM cell header */
568 #define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
570 (header) &= ~PTI_MASK; \
571 (header) |= (((pti) << 1) & PTI_MASK); \
574 /** Mask to acess CLP */
575 #define CLP_MASK 0x00000001
577 /** return CLP from ATM cell header */
578 #define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
579 ((header) & CLP_MASK)
581 /** set CLP into ATM cell header */
582 #define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
584 (header) &= ~CLP_MASK; \
585 (header) |= ((clp) & CLP_MASK); \
590 * Definition of the Rx bitfield
592 * This would most conviently be defined as the bit field shown below.
593 * Endian portability prevents this, therefore a set of macros
594 * are defined to access the fields within the rxBitfield assumed to
595 * be passed as a UINT32.
597 * Changes to field sizes or orders must be reflected in the offset
602 * { IX_NPEA_RXBITFIELD(
603 * unsigned int status:1,
604 * unsigned int port:7,
605 * unsigned int vcId:8,
606 * unsigned int currMbufSize:16);
611 /** Mask to acess the rxBitField status */
612 #define STATUS_MASK 0x80000000
614 /** return the rxBitField status */
615 #define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
616 (((rxbitfield) & STATUS_MASK) >> 31)
618 /** set the rxBitField status */
619 #define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
621 (rxbitfield) &= ~STATUS_MASK; \
622 (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
625 /** Mask to acess the rxBitField port */
626 #define PORT_MASK 0x7f000000
628 /** return the rxBitField port */
629 #define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
630 (((rxbitfield) & PORT_MASK) >> 24)
632 /** set the rxBitField port */
633 #define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
635 (rxbitfield) &= ~PORT_MASK; \
636 (rxbitfield) |= (((port) << 24) & PORT_MASK); \
639 /** Mask to acess the rxBitField vcId */
640 #define VCID_MASK 0x00ff0000
642 /** return the rxBitField vcId */
643 #define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
644 (((rxbitfield) & VCID_MASK) >> 16)
646 /** set the rxBitField vcId */
647 #define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
649 (rxbitfield) &= ~VCID_MASK; \
650 (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
653 /** Mask to acess the rxBitField mbuf size */
654 #define CURRMBUFSIZE_MASK 0x0000ffff
656 /** return the rxBitField mbuf size */
657 #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
658 ((rxbitfield) & CURRMBUFSIZE_MASK)
660 /** set the rxBitField mbuf size */
661 #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
663 (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
664 (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
670 * @brief Tx Descriptor definition
674 UINT8 port; /**< Tx Port number */
675 UINT8 aalType; /**< AAL Type */
676 UINT16 currMbufLen; /**< mbuf length */
677 UINT32 atmCellHeader; /**< ATM cell header */
678 IX_OSAL_MBUF *pCurrMbuf; /**< pointer to mbuf */
679 unsigned char *pCurrMbufData; /**< Pointer to mbuf->dat */
680 IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
681 UINT32 totalLen; /**< Total Length */
682 UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
685 /* Changes to field sizes or orders must be reflected in the offset
686 * definitions above. */
692 * @brief Rx Descriptor definition
696 UINT32 rxBitField; /**< Received bit field */
697 UINT32 atmCellHeader; /**< ATM Cell Header */
698 UINT32 rsvdWord0; /**< Reserved field */
699 UINT16 currMbufLen; /**< Mbuf Length */
700 UINT8 timeLimit; /**< Payload Reassembly timeLimit (used for aal0_xx only) */
701 UINT8 rsvdByte0; /**< Reserved field */
702 UINT32 rsvdWord1; /**< Reserved field */
703 IX_OSAL_MBUF *pCurrMbuf; /**< Pointer to current mbuf */
704 unsigned char *pCurrMbufData; /**< Pointer to current mbuf->data */
705 IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
706 UINT32 totalLen; /**< Total Length */
707 UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
712 * @brief NPE-A AAL Type
716 IX_NPE_A_AAL_TYPE_INVALID = 0, /**< Invalid AAL type */
717 IX_NPE_A_AAL_TYPE_0_48 = 0x1, /**< AAL0 - 48 byte */
718 IX_NPE_A_AAL_TYPE_0_52 = 0x2, /**< AAL0 - 52 byte */
719 IX_NPE_A_AAL_TYPE_5 = 0x5, /**< AAL5 */
720 IX_NPE_A_AAL_TYPE_OAM = 0xF /**< OAM */
724 * @brief NPE-A Payload format 52-bytes & 48-bytes
728 IX_NPE_A_52_BYTE_PAYLOAD = 0, /**< 52 byte payload */
729 IX_NPE_A_48_BYTE_PAYLOAD /**< 48 byte payload */
730 } IxNpeA_PayloadFormat;
733 * @brief HSS Packetized NpePacket Descriptor Structure
737 UINT8 status; /**< Status of the packet passed to the client */
738 UINT8 errorCount; /**< Number of errors */
739 UINT8 chainCount; /**< Mbuf chain count e.g. 0 - No mbuf chain */
740 UINT8 rsvdByte0; /**< Reserved byte to make the descriptor word align */
742 UINT16 packetLength; /**< Packet Length */
743 UINT16 rsvdShort0; /**< Reserved short to make the descriptor a word align */
745 IX_OSAL_MBUF *pRootMbuf; /**< Pointer to Root mbuf */
746 IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
747 UINT8 *pMbufData; /**< Pointer to the current mbuf->data */
748 UINT32 mbufLength; /**< Current mbuf length */
750 } IxNpeA_NpePacketDescriptor;
758 #endif /* __doxygen_HIDE */