1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/ethtool.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/mii.h>
19 #include <linux/if_ether.h>
20 #include <linux/if_vlan.h>
23 #include <linux/ipv6.h>
24 #include <linux/log2.h>
25 #include <linux/jiffies.h>
26 #include <linux/crc32.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
31 #include <linux/of_device.h>
35 #define DRV_MODULE_NAME "niu"
36 #define DRV_MODULE_VERSION "1.1"
37 #define DRV_MODULE_RELDATE "Apr 22, 2010"
39 static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
48 static u64 readq(void __iomem *reg)
50 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
53 static void writeq(u64 val, void __iomem *reg)
55 writel(val & 0xffffffff, reg);
56 writel(val >> 32, reg + 0x4UL);
60 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
61 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
65 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
67 #define NIU_TX_TIMEOUT (5 * HZ)
69 #define nr64(reg) readq(np->regs + (reg))
70 #define nw64(reg, val) writeq((val), np->regs + (reg))
72 #define nr64_mac(reg) readq(np->mac_regs + (reg))
73 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
75 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
76 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
78 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
79 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
81 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
82 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
84 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
87 static int debug = -1;
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "NIU debug level");
91 #define niu_lock_parent(np, flags) \
92 spin_lock_irqsave(&np->parent->lock, flags)
93 #define niu_unlock_parent(np, flags) \
94 spin_unlock_irqrestore(&np->parent->lock, flags)
96 static int serdes_init_10g_serdes(struct niu *np);
98 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99 u64 bits, int limit, int delay)
101 while (--limit >= 0) {
102 u64 val = nr64_mac(reg);
113 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114 u64 bits, int limit, int delay,
115 const char *reg_name)
120 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
122 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123 (unsigned long long)bits, reg_name,
124 (unsigned long long)nr64_mac(reg));
128 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
133 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay)
136 while (--limit >= 0) {
137 u64 val = nr64_ipp(reg);
148 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149 u64 bits, int limit, int delay,
150 const char *reg_name)
159 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
161 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162 (unsigned long long)bits, reg_name,
163 (unsigned long long)nr64_ipp(reg));
167 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
172 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173 u64 bits, int limit, int delay)
175 while (--limit >= 0) {
187 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
192 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay,
194 const char *reg_name)
199 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
201 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202 (unsigned long long)bits, reg_name,
203 (unsigned long long)nr64(reg));
207 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
212 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
214 u64 val = (u64) lp->timer;
217 val |= LDG_IMGMT_ARM;
219 nw64(LDG_IMGMT(lp->ldg_num), val);
222 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
224 unsigned long mask_reg, bits;
227 if (ldn < 0 || ldn > LDN_MAX)
231 mask_reg = LD_IM0(ldn);
234 mask_reg = LD_IM1(ldn - 64);
238 val = nr64(mask_reg);
248 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
250 struct niu_parent *parent = np->parent;
253 for (i = 0; i <= LDN_MAX; i++) {
256 if (parent->ldg_map[i] != lp->ldg_num)
259 err = niu_ldn_irq_enable(np, i, on);
266 static int niu_enable_interrupts(struct niu *np, int on)
270 for (i = 0; i < np->num_ldg; i++) {
271 struct niu_ldg *lp = &np->ldg[i];
274 err = niu_enable_ldn_in_ldg(np, lp, on);
278 for (i = 0; i < np->num_ldg; i++)
279 niu_ldg_rearm(np, &np->ldg[i], on);
284 static u32 phy_encode(u32 type, int port)
286 return (type << (port * 2));
289 static u32 phy_decode(u32 val, int port)
291 return (val >> (port * 2)) & PORT_TYPE_MASK;
294 static int mdio_wait(struct niu *np)
299 while (--limit > 0) {
300 val = nr64(MIF_FRAME_OUTPUT);
301 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302 return val & MIF_FRAME_OUTPUT_DATA;
310 static int mdio_read(struct niu *np, int port, int dev, int reg)
314 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
319 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320 return mdio_wait(np);
323 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
327 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
332 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
340 static int mii_read(struct niu *np, int port, int reg)
342 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343 return mdio_wait(np);
346 static int mii_write(struct niu *np, int port, int reg, int data)
350 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
358 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
362 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363 ESR2_TI_PLL_TX_CFG_L(channel),
366 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367 ESR2_TI_PLL_TX_CFG_H(channel),
372 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
376 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377 ESR2_TI_PLL_RX_CFG_L(channel),
380 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381 ESR2_TI_PLL_RX_CFG_H(channel),
386 /* Mode is always 10G fiber. */
387 static int serdes_init_niu_10g_fiber(struct niu *np)
389 struct niu_link_config *lp = &np->link_config;
393 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396 PLL_RX_CFG_EQ_LP_ADAPTIVE);
398 if (lp->loopback_mode == LOOPBACK_PHY) {
399 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
401 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
404 tx_cfg |= PLL_TX_CFG_ENTEST;
405 rx_cfg |= PLL_RX_CFG_ENTEST;
408 /* Initialize all 4 lanes of the SERDES. */
409 for (i = 0; i < 4; i++) {
410 int err = esr2_set_tx_cfg(np, i, tx_cfg);
415 for (i = 0; i < 4; i++) {
416 int err = esr2_set_rx_cfg(np, i, rx_cfg);
424 static int serdes_init_niu_1g_serdes(struct niu *np)
426 struct niu_link_config *lp = &np->link_config;
427 u16 pll_cfg, pll_sts;
429 u64 uninitialized_var(sig), mask, val;
434 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435 PLL_TX_CFG_RATE_HALF);
436 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438 PLL_RX_CFG_RATE_HALF);
441 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
443 if (lp->loopback_mode == LOOPBACK_PHY) {
444 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
446 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
449 tx_cfg |= PLL_TX_CFG_ENTEST;
450 rx_cfg |= PLL_RX_CFG_ENTEST;
453 /* Initialize PLL for 1G */
454 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
456 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457 ESR2_TI_PLL_CFG_L, pll_cfg);
459 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
464 pll_sts = PLL_CFG_ENPLL;
466 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467 ESR2_TI_PLL_STS_L, pll_sts);
469 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
476 /* Initialize all 4 lanes of the SERDES. */
477 for (i = 0; i < 4; i++) {
478 err = esr2_set_tx_cfg(np, i, tx_cfg);
483 for (i = 0; i < 4; i++) {
484 err = esr2_set_rx_cfg(np, i, rx_cfg);
491 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
496 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
504 while (max_retry--) {
505 sig = nr64(ESR_INT_SIGNALS);
506 if ((sig & mask) == val)
512 if ((sig & mask) != val) {
513 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514 np->port, (int)(sig & mask), (int)val);
521 static int serdes_init_niu_10g_serdes(struct niu *np)
523 struct niu_link_config *lp = &np->link_config;
524 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
526 u64 uninitialized_var(sig), mask, val;
530 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533 PLL_RX_CFG_EQ_LP_ADAPTIVE);
535 if (lp->loopback_mode == LOOPBACK_PHY) {
536 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
538 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
541 tx_cfg |= PLL_TX_CFG_ENTEST;
542 rx_cfg |= PLL_RX_CFG_ENTEST;
545 /* Initialize PLL for 10G */
546 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
548 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
551 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
556 pll_sts = PLL_CFG_ENPLL;
558 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
561 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
568 /* Initialize all 4 lanes of the SERDES. */
569 for (i = 0; i < 4; i++) {
570 err = esr2_set_tx_cfg(np, i, tx_cfg);
575 for (i = 0; i < 4; i++) {
576 err = esr2_set_rx_cfg(np, i, rx_cfg);
581 /* check if serdes is ready */
585 mask = ESR_INT_SIGNALS_P0_BITS;
586 val = (ESR_INT_SRDY0_P0 |
596 mask = ESR_INT_SIGNALS_P1_BITS;
597 val = (ESR_INT_SRDY0_P1 |
610 while (max_retry--) {
611 sig = nr64(ESR_INT_SIGNALS);
612 if ((sig & mask) == val)
618 if ((sig & mask) != val) {
619 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620 np->port, (int)(sig & mask), (int)val);
622 /* 10G failed, try initializing at 1G */
623 err = serdes_init_niu_1g_serdes(np);
625 np->flags &= ~NIU_FLAGS_10G;
626 np->mac_xcvr = MAC_XCVR_PCS;
628 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
636 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
640 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
642 *val = (err & 0xffff);
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644 ESR_RXTX_CTRL_H(chan));
646 *val |= ((err & 0xffff) << 16);
652 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
656 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657 ESR_GLUE_CTRL0_L(chan));
659 *val = (err & 0xffff);
660 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661 ESR_GLUE_CTRL0_H(chan));
663 *val |= ((err & 0xffff) << 16);
670 static int esr_read_reset(struct niu *np, u32 *val)
674 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675 ESR_RXTX_RESET_CTRL_L);
677 *val = (err & 0xffff);
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679 ESR_RXTX_RESET_CTRL_H);
681 *val |= ((err & 0xffff) << 16);
688 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
692 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693 ESR_RXTX_CTRL_L(chan), val & 0xffff);
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_H(chan), (val >> 16));
700 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
704 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_H(chan), (val >> 16));
712 static int esr_reset(struct niu *np)
714 u32 uninitialized_var(reset);
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718 ESR_RXTX_RESET_CTRL_L, 0x0000);
721 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722 ESR_RXTX_RESET_CTRL_H, 0xffff);
727 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728 ESR_RXTX_RESET_CTRL_L, 0xffff);
733 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734 ESR_RXTX_RESET_CTRL_H, 0x0000);
739 err = esr_read_reset(np, &reset);
743 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
751 static int serdes_init_10g(struct niu *np)
753 struct niu_link_config *lp = &np->link_config;
754 unsigned long ctrl_reg, test_cfg_reg, i;
755 u64 ctrl_val, test_cfg_val, sig, mask, val;
760 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
764 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
771 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772 ENET_SERDES_CTRL_SDET_1 |
773 ENET_SERDES_CTRL_SDET_2 |
774 ENET_SERDES_CTRL_SDET_3 |
775 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
785 if (lp->loopback_mode == LOOPBACK_PHY) {
786 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787 ENET_SERDES_TEST_MD_0_SHIFT) |
788 (ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_1_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_2_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_3_SHIFT));
796 nw64(ctrl_reg, ctrl_val);
797 nw64(test_cfg_reg, test_cfg_val);
799 /* Initialize all 4 lanes of the SERDES. */
800 for (i = 0; i < 4; i++) {
801 u32 rxtx_ctrl, glue0;
803 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
806 err = esr_read_glue0(np, i, &glue0);
810 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
814 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815 ESR_GLUE_CTRL0_THCNT |
816 ESR_GLUE_CTRL0_BLTIME);
817 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820 (BLTIME_300_CYCLES <<
821 ESR_GLUE_CTRL0_BLTIME_SHIFT));
823 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
826 err = esr_write_glue0(np, i, glue0);
835 sig = nr64(ESR_INT_SIGNALS);
838 mask = ESR_INT_SIGNALS_P0_BITS;
839 val = (ESR_INT_SRDY0_P0 |
849 mask = ESR_INT_SIGNALS_P1_BITS;
850 val = (ESR_INT_SRDY0_P1 |
863 if ((sig & mask) != val) {
864 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
868 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869 np->port, (int)(sig & mask), (int)val);
872 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
877 static int serdes_init_1g(struct niu *np)
881 val = nr64(ENET_SERDES_1_PLL_CFG);
882 val &= ~ENET_SERDES_PLL_FBDIV2;
885 val |= ENET_SERDES_PLL_HRATE0;
888 val |= ENET_SERDES_PLL_HRATE1;
891 val |= ENET_SERDES_PLL_HRATE2;
894 val |= ENET_SERDES_PLL_HRATE3;
899 nw64(ENET_SERDES_1_PLL_CFG, val);
904 static int serdes_init_1g_serdes(struct niu *np)
906 struct niu_link_config *lp = &np->link_config;
907 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908 u64 ctrl_val, test_cfg_val, sig, mask, val;
910 u64 reset_val, val_rd;
912 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914 ENET_SERDES_PLL_FBDIV0;
917 reset_val = ENET_SERDES_RESET_0;
918 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920 pll_cfg = ENET_SERDES_0_PLL_CFG;
923 reset_val = ENET_SERDES_RESET_1;
924 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926 pll_cfg = ENET_SERDES_1_PLL_CFG;
932 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933 ENET_SERDES_CTRL_SDET_1 |
934 ENET_SERDES_CTRL_SDET_2 |
935 ENET_SERDES_CTRL_SDET_3 |
936 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
946 if (lp->loopback_mode == LOOPBACK_PHY) {
947 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948 ENET_SERDES_TEST_MD_0_SHIFT) |
949 (ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_1_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_2_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_3_SHIFT));
957 nw64(ENET_SERDES_RESET, reset_val);
959 val_rd = nr64(ENET_SERDES_RESET);
960 val_rd &= ~reset_val;
962 nw64(ctrl_reg, ctrl_val);
963 nw64(test_cfg_reg, test_cfg_val);
964 nw64(ENET_SERDES_RESET, val_rd);
967 /* Initialize all 4 lanes of the SERDES. */
968 for (i = 0; i < 4; i++) {
969 u32 rxtx_ctrl, glue0;
971 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
974 err = esr_read_glue0(np, i, &glue0);
978 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
982 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983 ESR_GLUE_CTRL0_THCNT |
984 ESR_GLUE_CTRL0_BLTIME);
985 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988 (BLTIME_300_CYCLES <<
989 ESR_GLUE_CTRL0_BLTIME_SHIFT));
991 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
994 err = esr_write_glue0(np, i, glue0);
1000 sig = nr64(ESR_INT_SIGNALS);
1003 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1008 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1016 if ((sig & mask) != val) {
1017 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018 np->port, (int)(sig & mask), (int)val);
1025 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1027 struct niu_link_config *lp = &np->link_config;
1031 unsigned long flags;
1035 current_speed = SPEED_INVALID;
1036 current_duplex = DUPLEX_INVALID;
1038 spin_lock_irqsave(&np->lock, flags);
1040 val = nr64_pcs(PCS_MII_STAT);
1042 if (val & PCS_MII_STAT_LINK_STATUS) {
1044 current_speed = SPEED_1000;
1045 current_duplex = DUPLEX_FULL;
1048 lp->active_speed = current_speed;
1049 lp->active_duplex = current_duplex;
1050 spin_unlock_irqrestore(&np->lock, flags);
1052 *link_up_p = link_up;
1056 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1058 unsigned long flags;
1059 struct niu_link_config *lp = &np->link_config;
1066 if (!(np->flags & NIU_FLAGS_10G))
1067 return link_status_1g_serdes(np, link_up_p);
1069 current_speed = SPEED_INVALID;
1070 current_duplex = DUPLEX_INVALID;
1071 spin_lock_irqsave(&np->lock, flags);
1073 val = nr64_xpcs(XPCS_STATUS(0));
1074 val2 = nr64_mac(XMAC_INTER2);
1075 if (val2 & 0x01000000)
1078 if ((val & 0x1000ULL) && link_ok) {
1080 current_speed = SPEED_10000;
1081 current_duplex = DUPLEX_FULL;
1083 lp->active_speed = current_speed;
1084 lp->active_duplex = current_duplex;
1085 spin_unlock_irqrestore(&np->lock, flags);
1086 *link_up_p = link_up;
1090 static int link_status_mii(struct niu *np, int *link_up_p)
1092 struct niu_link_config *lp = &np->link_config;
1094 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095 int supported, advertising, active_speed, active_duplex;
1097 err = mii_read(np, np->phy_addr, MII_BMCR);
1098 if (unlikely(err < 0))
1102 err = mii_read(np, np->phy_addr, MII_BMSR);
1103 if (unlikely(err < 0))
1107 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108 if (unlikely(err < 0))
1112 err = mii_read(np, np->phy_addr, MII_LPA);
1113 if (unlikely(err < 0))
1117 if (likely(bmsr & BMSR_ESTATEN)) {
1118 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119 if (unlikely(err < 0))
1123 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124 if (unlikely(err < 0))
1128 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129 if (unlikely(err < 0))
1133 estatus = ctrl1000 = stat1000 = 0;
1136 if (bmsr & BMSR_ANEGCAPABLE)
1137 supported |= SUPPORTED_Autoneg;
1138 if (bmsr & BMSR_10HALF)
1139 supported |= SUPPORTED_10baseT_Half;
1140 if (bmsr & BMSR_10FULL)
1141 supported |= SUPPORTED_10baseT_Full;
1142 if (bmsr & BMSR_100HALF)
1143 supported |= SUPPORTED_100baseT_Half;
1144 if (bmsr & BMSR_100FULL)
1145 supported |= SUPPORTED_100baseT_Full;
1146 if (estatus & ESTATUS_1000_THALF)
1147 supported |= SUPPORTED_1000baseT_Half;
1148 if (estatus & ESTATUS_1000_TFULL)
1149 supported |= SUPPORTED_1000baseT_Full;
1150 lp->supported = supported;
1153 if (advert & ADVERTISE_10HALF)
1154 advertising |= ADVERTISED_10baseT_Half;
1155 if (advert & ADVERTISE_10FULL)
1156 advertising |= ADVERTISED_10baseT_Full;
1157 if (advert & ADVERTISE_100HALF)
1158 advertising |= ADVERTISED_100baseT_Half;
1159 if (advert & ADVERTISE_100FULL)
1160 advertising |= ADVERTISED_100baseT_Full;
1161 if (ctrl1000 & ADVERTISE_1000HALF)
1162 advertising |= ADVERTISED_1000baseT_Half;
1163 if (ctrl1000 & ADVERTISE_1000FULL)
1164 advertising |= ADVERTISED_1000baseT_Full;
1166 if (bmcr & BMCR_ANENABLE) {
1169 lp->active_autoneg = 1;
1170 advertising |= ADVERTISED_Autoneg;
1173 neg1000 = (ctrl1000 << 2) & stat1000;
1175 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176 active_speed = SPEED_1000;
1177 else if (neg & LPA_100)
1178 active_speed = SPEED_100;
1179 else if (neg & (LPA_10HALF | LPA_10FULL))
1180 active_speed = SPEED_10;
1182 active_speed = SPEED_INVALID;
1184 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185 active_duplex = DUPLEX_FULL;
1186 else if (active_speed != SPEED_INVALID)
1187 active_duplex = DUPLEX_HALF;
1189 active_duplex = DUPLEX_INVALID;
1191 lp->active_autoneg = 0;
1193 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194 active_speed = SPEED_1000;
1195 else if (bmcr & BMCR_SPEED100)
1196 active_speed = SPEED_100;
1198 active_speed = SPEED_10;
1200 if (bmcr & BMCR_FULLDPLX)
1201 active_duplex = DUPLEX_FULL;
1203 active_duplex = DUPLEX_HALF;
1206 lp->active_advertising = advertising;
1207 lp->active_speed = active_speed;
1208 lp->active_duplex = active_duplex;
1209 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1214 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1216 struct niu_link_config *lp = &np->link_config;
1217 u16 current_speed, bmsr;
1218 unsigned long flags;
1223 current_speed = SPEED_INVALID;
1224 current_duplex = DUPLEX_INVALID;
1226 spin_lock_irqsave(&np->lock, flags);
1230 err = mii_read(np, np->phy_addr, MII_BMSR);
1235 if (bmsr & BMSR_LSTATUS) {
1236 u16 adv, lpa, common, estat;
1238 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1243 err = mii_read(np, np->phy_addr, MII_LPA);
1250 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1255 current_speed = SPEED_1000;
1256 current_duplex = DUPLEX_FULL;
1259 lp->active_speed = current_speed;
1260 lp->active_duplex = current_duplex;
1264 spin_unlock_irqrestore(&np->lock, flags);
1266 *link_up_p = link_up;
1270 static int link_status_1g(struct niu *np, int *link_up_p)
1272 struct niu_link_config *lp = &np->link_config;
1273 unsigned long flags;
1276 spin_lock_irqsave(&np->lock, flags);
1278 err = link_status_mii(np, link_up_p);
1279 lp->supported |= SUPPORTED_TP;
1280 lp->active_advertising |= ADVERTISED_TP;
1282 spin_unlock_irqrestore(&np->lock, flags);
1286 static int bcm8704_reset(struct niu *np)
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1292 if (err < 0 || err == 0xffff)
1295 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1301 while (--limit >= 0) {
1302 err = mdio_read(np, np->phy_addr,
1303 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1306 if (!(err & BMCR_RESET))
1310 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1311 np->port, (err & 0xffff));
1317 /* When written, certain PHY registers need to be read back twice
1318 * in order for the bits to settle properly.
1320 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1322 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1325 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1331 static int bcm8706_init_user_dev3(struct niu *np)
1336 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1337 BCM8704_USER_OPT_DIGITAL_CTRL);
1340 err &= ~USER_ODIG_CTRL_GPIOS;
1341 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1342 err |= USER_ODIG_CTRL_RESV2;
1343 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1344 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1353 static int bcm8704_init_user_dev3(struct niu *np)
1357 err = mdio_write(np, np->phy_addr,
1358 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1359 (USER_CONTROL_OPTXRST_LVL |
1360 USER_CONTROL_OPBIASFLT_LVL |
1361 USER_CONTROL_OBTMPFLT_LVL |
1362 USER_CONTROL_OPPRFLT_LVL |
1363 USER_CONTROL_OPTXFLT_LVL |
1364 USER_CONTROL_OPRXLOS_LVL |
1365 USER_CONTROL_OPRXFLT_LVL |
1366 USER_CONTROL_OPTXON_LVL |
1367 (0x3f << USER_CONTROL_RES1_SHIFT)));
1371 err = mdio_write(np, np->phy_addr,
1372 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1373 (USER_PMD_TX_CTL_XFP_CLKEN |
1374 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1375 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1376 USER_PMD_TX_CTL_TSCK_LPWREN));
1380 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1383 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1387 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1388 BCM8704_USER_OPT_DIGITAL_CTRL);
1391 err &= ~USER_ODIG_CTRL_GPIOS;
1392 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1393 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1394 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1403 static int mrvl88x2011_act_led(struct niu *np, int val)
1407 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1408 MRVL88X2011_LED_8_TO_11_CTL);
1412 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1413 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1415 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1416 MRVL88X2011_LED_8_TO_11_CTL, err);
1419 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1423 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1424 MRVL88X2011_LED_BLINK_CTL);
1426 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1429 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1430 MRVL88X2011_LED_BLINK_CTL, err);
1436 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1440 /* Set LED functions */
1441 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1446 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1451 MRVL88X2011_GENERAL_CTL);
1455 err |= MRVL88X2011_ENA_XFPREFCLK;
1457 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1458 MRVL88X2011_GENERAL_CTL, err);
1462 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463 MRVL88X2011_PMA_PMD_CTL_1);
1467 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1468 err |= MRVL88X2011_LOOPBACK;
1470 err &= ~MRVL88X2011_LOOPBACK;
1472 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1473 MRVL88X2011_PMA_PMD_CTL_1, err);
1478 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1479 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1483 static int xcvr_diag_bcm870x(struct niu *np)
1485 u16 analog_stat0, tx_alarm_status;
1489 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1493 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1495 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1498 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1500 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1504 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1507 /* XXX dig this out it might not be so useful XXX */
1508 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1509 BCM8704_USER_ANALOG_STATUS0);
1512 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1513 BCM8704_USER_ANALOG_STATUS0);
1518 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1519 BCM8704_USER_TX_ALARM_STATUS);
1522 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1523 BCM8704_USER_TX_ALARM_STATUS);
1526 tx_alarm_status = err;
1528 if (analog_stat0 != 0x03fc) {
1529 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1530 pr_info("Port %u cable not connected or bad cable\n",
1532 } else if (analog_stat0 == 0x639c) {
1533 pr_info("Port %u optical module is bad or missing\n",
1541 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1543 struct niu_link_config *lp = &np->link_config;
1546 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1551 err &= ~BMCR_LOOPBACK;
1553 if (lp->loopback_mode == LOOPBACK_MAC)
1554 err |= BMCR_LOOPBACK;
1556 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1564 static int xcvr_init_10g_bcm8706(struct niu *np)
1569 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1570 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1573 val = nr64_mac(XMAC_CONFIG);
1574 val &= ~XMAC_CONFIG_LED_POLARITY;
1575 val |= XMAC_CONFIG_FORCE_LED_ON;
1576 nw64_mac(XMAC_CONFIG, val);
1578 val = nr64(MIF_CONFIG);
1579 val |= MIF_CONFIG_INDIRECT_MODE;
1580 nw64(MIF_CONFIG, val);
1582 err = bcm8704_reset(np);
1586 err = xcvr_10g_set_lb_bcm870x(np);
1590 err = bcm8706_init_user_dev3(np);
1594 err = xcvr_diag_bcm870x(np);
1601 static int xcvr_init_10g_bcm8704(struct niu *np)
1605 err = bcm8704_reset(np);
1609 err = bcm8704_init_user_dev3(np);
1613 err = xcvr_10g_set_lb_bcm870x(np);
1617 err = xcvr_diag_bcm870x(np);
1624 static int xcvr_init_10g(struct niu *np)
1629 val = nr64_mac(XMAC_CONFIG);
1630 val &= ~XMAC_CONFIG_LED_POLARITY;
1631 val |= XMAC_CONFIG_FORCE_LED_ON;
1632 nw64_mac(XMAC_CONFIG, val);
1634 /* XXX shared resource, lock parent XXX */
1635 val = nr64(MIF_CONFIG);
1636 val |= MIF_CONFIG_INDIRECT_MODE;
1637 nw64(MIF_CONFIG, val);
1639 phy_id = phy_decode(np->parent->port_phy, np->port);
1640 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1642 /* handle different phy types */
1643 switch (phy_id & NIU_PHY_ID_MASK) {
1644 case NIU_PHY_ID_MRVL88X2011:
1645 err = xcvr_init_10g_mrvl88x2011(np);
1648 default: /* bcom 8704 */
1649 err = xcvr_init_10g_bcm8704(np);
1656 static int mii_reset(struct niu *np)
1660 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1665 while (--limit >= 0) {
1667 err = mii_read(np, np->phy_addr, MII_BMCR);
1670 if (!(err & BMCR_RESET))
1674 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1682 static int xcvr_init_1g_rgmii(struct niu *np)
1686 u16 bmcr, bmsr, estat;
1688 val = nr64(MIF_CONFIG);
1689 val &= ~MIF_CONFIG_INDIRECT_MODE;
1690 nw64(MIF_CONFIG, val);
1692 err = mii_reset(np);
1696 err = mii_read(np, np->phy_addr, MII_BMSR);
1702 if (bmsr & BMSR_ESTATEN) {
1703 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1710 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1714 if (bmsr & BMSR_ESTATEN) {
1717 if (estat & ESTATUS_1000_TFULL)
1718 ctrl1000 |= ADVERTISE_1000FULL;
1719 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1724 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1726 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1730 err = mii_read(np, np->phy_addr, MII_BMCR);
1733 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1735 err = mii_read(np, np->phy_addr, MII_BMSR);
1742 static int mii_init_common(struct niu *np)
1744 struct niu_link_config *lp = &np->link_config;
1745 u16 bmcr, bmsr, adv, estat;
1748 err = mii_reset(np);
1752 err = mii_read(np, np->phy_addr, MII_BMSR);
1758 if (bmsr & BMSR_ESTATEN) {
1759 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1766 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1770 if (lp->loopback_mode == LOOPBACK_MAC) {
1771 bmcr |= BMCR_LOOPBACK;
1772 if (lp->active_speed == SPEED_1000)
1773 bmcr |= BMCR_SPEED1000;
1774 if (lp->active_duplex == DUPLEX_FULL)
1775 bmcr |= BMCR_FULLDPLX;
1778 if (lp->loopback_mode == LOOPBACK_PHY) {
1781 aux = (BCM5464R_AUX_CTL_EXT_LB |
1782 BCM5464R_AUX_CTL_WRITE_1);
1783 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1791 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1792 if ((bmsr & BMSR_10HALF) &&
1793 (lp->advertising & ADVERTISED_10baseT_Half))
1794 adv |= ADVERTISE_10HALF;
1795 if ((bmsr & BMSR_10FULL) &&
1796 (lp->advertising & ADVERTISED_10baseT_Full))
1797 adv |= ADVERTISE_10FULL;
1798 if ((bmsr & BMSR_100HALF) &&
1799 (lp->advertising & ADVERTISED_100baseT_Half))
1800 adv |= ADVERTISE_100HALF;
1801 if ((bmsr & BMSR_100FULL) &&
1802 (lp->advertising & ADVERTISED_100baseT_Full))
1803 adv |= ADVERTISE_100FULL;
1804 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1808 if (likely(bmsr & BMSR_ESTATEN)) {
1810 if ((estat & ESTATUS_1000_THALF) &&
1811 (lp->advertising & ADVERTISED_1000baseT_Half))
1812 ctrl1000 |= ADVERTISE_1000HALF;
1813 if ((estat & ESTATUS_1000_TFULL) &&
1814 (lp->advertising & ADVERTISED_1000baseT_Full))
1815 ctrl1000 |= ADVERTISE_1000FULL;
1816 err = mii_write(np, np->phy_addr,
1817 MII_CTRL1000, ctrl1000);
1822 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1827 if (lp->duplex == DUPLEX_FULL) {
1828 bmcr |= BMCR_FULLDPLX;
1830 } else if (lp->duplex == DUPLEX_HALF)
1835 if (lp->speed == SPEED_1000) {
1836 /* if X-full requested while not supported, or
1837 X-half requested while not supported... */
1838 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1839 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1841 bmcr |= BMCR_SPEED1000;
1842 } else if (lp->speed == SPEED_100) {
1843 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1844 (!fulldpx && !(bmsr & BMSR_100HALF)))
1846 bmcr |= BMCR_SPEED100;
1847 } else if (lp->speed == SPEED_10) {
1848 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1849 (!fulldpx && !(bmsr & BMSR_10HALF)))
1855 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1860 err = mii_read(np, np->phy_addr, MII_BMCR);
1865 err = mii_read(np, np->phy_addr, MII_BMSR);
1870 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1871 np->port, bmcr, bmsr);
1877 static int xcvr_init_1g(struct niu *np)
1881 /* XXX shared resource, lock parent XXX */
1882 val = nr64(MIF_CONFIG);
1883 val &= ~MIF_CONFIG_INDIRECT_MODE;
1884 nw64(MIF_CONFIG, val);
1886 return mii_init_common(np);
1889 static int niu_xcvr_init(struct niu *np)
1891 const struct niu_phy_ops *ops = np->phy_ops;
1896 err = ops->xcvr_init(np);
1901 static int niu_serdes_init(struct niu *np)
1903 const struct niu_phy_ops *ops = np->phy_ops;
1907 if (ops->serdes_init)
1908 err = ops->serdes_init(np);
1913 static void niu_init_xif(struct niu *);
1914 static void niu_handle_led(struct niu *, int status);
1916 static int niu_link_status_common(struct niu *np, int link_up)
1918 struct niu_link_config *lp = &np->link_config;
1919 struct net_device *dev = np->dev;
1920 unsigned long flags;
1922 if (!netif_carrier_ok(dev) && link_up) {
1923 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1924 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1925 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1926 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1928 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1930 spin_lock_irqsave(&np->lock, flags);
1932 niu_handle_led(np, 1);
1933 spin_unlock_irqrestore(&np->lock, flags);
1935 netif_carrier_on(dev);
1936 } else if (netif_carrier_ok(dev) && !link_up) {
1937 netif_warn(np, link, dev, "Link is down\n");
1938 spin_lock_irqsave(&np->lock, flags);
1939 niu_handle_led(np, 0);
1940 spin_unlock_irqrestore(&np->lock, flags);
1941 netif_carrier_off(dev);
1947 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1949 int err, link_up, pma_status, pcs_status;
1953 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1954 MRVL88X2011_10G_PMD_STATUS_2);
1958 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1960 MRVL88X2011_PMA_PMD_STATUS_1);
1964 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1966 /* Check PMC Register : 3.0001.2 == 1: read twice */
1967 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1968 MRVL88X2011_PMA_PMD_STATUS_1);
1972 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1973 MRVL88X2011_PMA_PMD_STATUS_1);
1977 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1979 /* Check XGXS Register : 4.0018.[0-3,12] */
1980 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1981 MRVL88X2011_10G_XGXS_LANE_STAT);
1985 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1986 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1987 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1989 link_up = (pma_status && pcs_status) ? 1 : 0;
1991 np->link_config.active_speed = SPEED_10000;
1992 np->link_config.active_duplex = DUPLEX_FULL;
1995 mrvl88x2011_act_led(np, (link_up ?
1996 MRVL88X2011_LED_CTL_PCS_ACT :
1997 MRVL88X2011_LED_CTL_OFF));
1999 *link_up_p = link_up;
2003 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2008 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2009 BCM8704_PMD_RCV_SIGDET);
2010 if (err < 0 || err == 0xffff)
2012 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2017 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2018 BCM8704_PCS_10G_R_STATUS);
2022 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2027 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2028 BCM8704_PHYXS_XGXS_LANE_STAT);
2031 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2032 PHYXS_XGXS_LANE_STAT_MAGIC |
2033 PHYXS_XGXS_LANE_STAT_PATTEST |
2034 PHYXS_XGXS_LANE_STAT_LANE3 |
2035 PHYXS_XGXS_LANE_STAT_LANE2 |
2036 PHYXS_XGXS_LANE_STAT_LANE1 |
2037 PHYXS_XGXS_LANE_STAT_LANE0)) {
2039 np->link_config.active_speed = SPEED_INVALID;
2040 np->link_config.active_duplex = DUPLEX_INVALID;
2045 np->link_config.active_speed = SPEED_10000;
2046 np->link_config.active_duplex = DUPLEX_FULL;
2050 *link_up_p = link_up;
2054 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2060 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2061 BCM8704_PMD_RCV_SIGDET);
2064 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2069 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2070 BCM8704_PCS_10G_R_STATUS);
2073 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2078 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2079 BCM8704_PHYXS_XGXS_LANE_STAT);
2083 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2084 PHYXS_XGXS_LANE_STAT_MAGIC |
2085 PHYXS_XGXS_LANE_STAT_LANE3 |
2086 PHYXS_XGXS_LANE_STAT_LANE2 |
2087 PHYXS_XGXS_LANE_STAT_LANE1 |
2088 PHYXS_XGXS_LANE_STAT_LANE0)) {
2094 np->link_config.active_speed = SPEED_10000;
2095 np->link_config.active_duplex = DUPLEX_FULL;
2099 *link_up_p = link_up;
2103 static int link_status_10g(struct niu *np, int *link_up_p)
2105 unsigned long flags;
2108 spin_lock_irqsave(&np->lock, flags);
2110 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2113 phy_id = phy_decode(np->parent->port_phy, np->port);
2114 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2116 /* handle different phy types */
2117 switch (phy_id & NIU_PHY_ID_MASK) {
2118 case NIU_PHY_ID_MRVL88X2011:
2119 err = link_status_10g_mrvl(np, link_up_p);
2122 default: /* bcom 8704 */
2123 err = link_status_10g_bcom(np, link_up_p);
2128 spin_unlock_irqrestore(&np->lock, flags);
2133 static int niu_10g_phy_present(struct niu *np)
2137 sig = nr64(ESR_INT_SIGNALS);
2140 mask = ESR_INT_SIGNALS_P0_BITS;
2141 val = (ESR_INT_SRDY0_P0 |
2144 ESR_INT_XDP_P0_CH3 |
2145 ESR_INT_XDP_P0_CH2 |
2146 ESR_INT_XDP_P0_CH1 |
2147 ESR_INT_XDP_P0_CH0);
2151 mask = ESR_INT_SIGNALS_P1_BITS;
2152 val = (ESR_INT_SRDY0_P1 |
2155 ESR_INT_XDP_P1_CH3 |
2156 ESR_INT_XDP_P1_CH2 |
2157 ESR_INT_XDP_P1_CH1 |
2158 ESR_INT_XDP_P1_CH0);
2165 if ((sig & mask) != val)
2170 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2172 unsigned long flags;
2175 int phy_present_prev;
2177 spin_lock_irqsave(&np->lock, flags);
2179 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2180 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2182 phy_present = niu_10g_phy_present(np);
2183 if (phy_present != phy_present_prev) {
2186 /* A NEM was just plugged in */
2187 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188 if (np->phy_ops->xcvr_init)
2189 err = np->phy_ops->xcvr_init(np);
2191 err = mdio_read(np, np->phy_addr,
2192 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2193 if (err == 0xffff) {
2194 /* No mdio, back-to-back XAUI */
2198 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2201 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2203 netif_warn(np, link, np->dev,
2204 "Hotplug PHY Removed\n");
2208 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2209 err = link_status_10g_bcm8706(np, link_up_p);
2210 if (err == 0xffff) {
2211 /* No mdio, back-to-back XAUI: it is C10NEM */
2213 np->link_config.active_speed = SPEED_10000;
2214 np->link_config.active_duplex = DUPLEX_FULL;
2219 spin_unlock_irqrestore(&np->lock, flags);
2224 static int niu_link_status(struct niu *np, int *link_up_p)
2226 const struct niu_phy_ops *ops = np->phy_ops;
2230 if (ops->link_status)
2231 err = ops->link_status(np, link_up_p);
2236 static void niu_timer(unsigned long __opaque)
2238 struct niu *np = (struct niu *) __opaque;
2242 err = niu_link_status(np, &link_up);
2244 niu_link_status_common(np, link_up);
2246 if (netif_carrier_ok(np->dev))
2250 np->timer.expires = jiffies + off;
2252 add_timer(&np->timer);
2255 static const struct niu_phy_ops phy_ops_10g_serdes = {
2256 .serdes_init = serdes_init_10g_serdes,
2257 .link_status = link_status_10g_serdes,
2260 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2261 .serdes_init = serdes_init_niu_10g_serdes,
2262 .link_status = link_status_10g_serdes,
2265 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2266 .serdes_init = serdes_init_niu_1g_serdes,
2267 .link_status = link_status_1g_serdes,
2270 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2271 .xcvr_init = xcvr_init_1g_rgmii,
2272 .link_status = link_status_1g_rgmii,
2275 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2276 .serdes_init = serdes_init_niu_10g_fiber,
2277 .xcvr_init = xcvr_init_10g,
2278 .link_status = link_status_10g,
2281 static const struct niu_phy_ops phy_ops_10g_fiber = {
2282 .serdes_init = serdes_init_10g,
2283 .xcvr_init = xcvr_init_10g,
2284 .link_status = link_status_10g,
2287 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2288 .serdes_init = serdes_init_10g,
2289 .xcvr_init = xcvr_init_10g_bcm8706,
2290 .link_status = link_status_10g_hotplug,
2293 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2294 .serdes_init = serdes_init_niu_10g_fiber,
2295 .xcvr_init = xcvr_init_10g_bcm8706,
2296 .link_status = link_status_10g_hotplug,
2299 static const struct niu_phy_ops phy_ops_10g_copper = {
2300 .serdes_init = serdes_init_10g,
2301 .link_status = link_status_10g, /* XXX */
2304 static const struct niu_phy_ops phy_ops_1g_fiber = {
2305 .serdes_init = serdes_init_1g,
2306 .xcvr_init = xcvr_init_1g,
2307 .link_status = link_status_1g,
2310 static const struct niu_phy_ops phy_ops_1g_copper = {
2311 .xcvr_init = xcvr_init_1g,
2312 .link_status = link_status_1g,
2315 struct niu_phy_template {
2316 const struct niu_phy_ops *ops;
2320 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2321 .ops = &phy_ops_10g_fiber_niu,
2322 .phy_addr_base = 16,
2325 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2326 .ops = &phy_ops_10g_serdes_niu,
2330 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2331 .ops = &phy_ops_1g_serdes_niu,
2335 static const struct niu_phy_template phy_template_10g_fiber = {
2336 .ops = &phy_ops_10g_fiber,
2340 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2341 .ops = &phy_ops_10g_fiber_hotplug,
2345 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2346 .ops = &phy_ops_niu_10g_hotplug,
2350 static const struct niu_phy_template phy_template_10g_copper = {
2351 .ops = &phy_ops_10g_copper,
2352 .phy_addr_base = 10,
2355 static const struct niu_phy_template phy_template_1g_fiber = {
2356 .ops = &phy_ops_1g_fiber,
2360 static const struct niu_phy_template phy_template_1g_copper = {
2361 .ops = &phy_ops_1g_copper,
2365 static const struct niu_phy_template phy_template_1g_rgmii = {
2366 .ops = &phy_ops_1g_rgmii,
2370 static const struct niu_phy_template phy_template_10g_serdes = {
2371 .ops = &phy_ops_10g_serdes,
2375 static int niu_atca_port_num[4] = {
2379 static int serdes_init_10g_serdes(struct niu *np)
2381 struct niu_link_config *lp = &np->link_config;
2382 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2383 u64 ctrl_val, test_cfg_val, sig, mask, val;
2388 reset_val = ENET_SERDES_RESET_0;
2389 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2390 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2391 pll_cfg = ENET_SERDES_0_PLL_CFG;
2394 reset_val = ENET_SERDES_RESET_1;
2395 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2396 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2397 pll_cfg = ENET_SERDES_1_PLL_CFG;
2403 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2404 ENET_SERDES_CTRL_SDET_1 |
2405 ENET_SERDES_CTRL_SDET_2 |
2406 ENET_SERDES_CTRL_SDET_3 |
2407 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2408 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2409 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2410 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2411 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2412 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2413 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2417 if (lp->loopback_mode == LOOPBACK_PHY) {
2418 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_0_SHIFT) |
2420 (ENET_TEST_MD_PAD_LOOPBACK <<
2421 ENET_SERDES_TEST_MD_1_SHIFT) |
2422 (ENET_TEST_MD_PAD_LOOPBACK <<
2423 ENET_SERDES_TEST_MD_2_SHIFT) |
2424 (ENET_TEST_MD_PAD_LOOPBACK <<
2425 ENET_SERDES_TEST_MD_3_SHIFT));
2429 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2430 nw64(ctrl_reg, ctrl_val);
2431 nw64(test_cfg_reg, test_cfg_val);
2433 /* Initialize all 4 lanes of the SERDES. */
2434 for (i = 0; i < 4; i++) {
2435 u32 rxtx_ctrl, glue0;
2438 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2441 err = esr_read_glue0(np, i, &glue0);
2445 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2446 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2447 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2449 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2450 ESR_GLUE_CTRL0_THCNT |
2451 ESR_GLUE_CTRL0_BLTIME);
2452 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2453 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2454 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2455 (BLTIME_300_CYCLES <<
2456 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2458 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2461 err = esr_write_glue0(np, i, glue0);
2467 sig = nr64(ESR_INT_SIGNALS);
2470 mask = ESR_INT_SIGNALS_P0_BITS;
2471 val = (ESR_INT_SRDY0_P0 |
2474 ESR_INT_XDP_P0_CH3 |
2475 ESR_INT_XDP_P0_CH2 |
2476 ESR_INT_XDP_P0_CH1 |
2477 ESR_INT_XDP_P0_CH0);
2481 mask = ESR_INT_SIGNALS_P1_BITS;
2482 val = (ESR_INT_SRDY0_P1 |
2485 ESR_INT_XDP_P1_CH3 |
2486 ESR_INT_XDP_P1_CH2 |
2487 ESR_INT_XDP_P1_CH1 |
2488 ESR_INT_XDP_P1_CH0);
2495 if ((sig & mask) != val) {
2497 err = serdes_init_1g_serdes(np);
2499 np->flags &= ~NIU_FLAGS_10G;
2500 np->mac_xcvr = MAC_XCVR_PCS;
2502 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2511 static int niu_determine_phy_disposition(struct niu *np)
2513 struct niu_parent *parent = np->parent;
2514 u8 plat_type = parent->plat_type;
2515 const struct niu_phy_template *tp;
2516 u32 phy_addr_off = 0;
2518 if (plat_type == PLAT_TYPE_NIU) {
2522 NIU_FLAGS_XCVR_SERDES)) {
2523 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2525 tp = &phy_template_niu_10g_serdes;
2527 case NIU_FLAGS_XCVR_SERDES:
2529 tp = &phy_template_niu_1g_serdes;
2531 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2534 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2535 tp = &phy_template_niu_10g_hotplug;
2541 tp = &phy_template_niu_10g_fiber;
2542 phy_addr_off += np->port;
2550 NIU_FLAGS_XCVR_SERDES)) {
2553 tp = &phy_template_1g_copper;
2554 if (plat_type == PLAT_TYPE_VF_P0)
2556 else if (plat_type == PLAT_TYPE_VF_P1)
2559 phy_addr_off += (np->port ^ 0x3);
2564 tp = &phy_template_10g_copper;
2567 case NIU_FLAGS_FIBER:
2569 tp = &phy_template_1g_fiber;
2572 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2574 tp = &phy_template_10g_fiber;
2575 if (plat_type == PLAT_TYPE_VF_P0 ||
2576 plat_type == PLAT_TYPE_VF_P1)
2578 phy_addr_off += np->port;
2579 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2580 tp = &phy_template_10g_fiber_hotplug;
2588 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2589 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2590 case NIU_FLAGS_XCVR_SERDES:
2594 tp = &phy_template_10g_serdes;
2598 tp = &phy_template_1g_rgmii;
2604 phy_addr_off = niu_atca_port_num[np->port];
2612 np->phy_ops = tp->ops;
2613 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2618 static int niu_init_link(struct niu *np)
2620 struct niu_parent *parent = np->parent;
2623 if (parent->plat_type == PLAT_TYPE_NIU) {
2624 err = niu_xcvr_init(np);
2629 err = niu_serdes_init(np);
2630 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2633 err = niu_xcvr_init(np);
2634 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2635 niu_link_status(np, &ignore);
2639 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2641 u16 reg0 = addr[4] << 8 | addr[5];
2642 u16 reg1 = addr[2] << 8 | addr[3];
2643 u16 reg2 = addr[0] << 8 | addr[1];
2645 if (np->flags & NIU_FLAGS_XMAC) {
2646 nw64_mac(XMAC_ADDR0, reg0);
2647 nw64_mac(XMAC_ADDR1, reg1);
2648 nw64_mac(XMAC_ADDR2, reg2);
2650 nw64_mac(BMAC_ADDR0, reg0);
2651 nw64_mac(BMAC_ADDR1, reg1);
2652 nw64_mac(BMAC_ADDR2, reg2);
2656 static int niu_num_alt_addr(struct niu *np)
2658 if (np->flags & NIU_FLAGS_XMAC)
2659 return XMAC_NUM_ALT_ADDR;
2661 return BMAC_NUM_ALT_ADDR;
2664 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2666 u16 reg0 = addr[4] << 8 | addr[5];
2667 u16 reg1 = addr[2] << 8 | addr[3];
2668 u16 reg2 = addr[0] << 8 | addr[1];
2670 if (index >= niu_num_alt_addr(np))
2673 if (np->flags & NIU_FLAGS_XMAC) {
2674 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2675 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2676 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2678 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2679 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2680 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2686 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2691 if (index >= niu_num_alt_addr(np))
2694 if (np->flags & NIU_FLAGS_XMAC) {
2695 reg = XMAC_ADDR_CMPEN;
2698 reg = BMAC_ADDR_CMPEN;
2699 mask = 1 << (index + 1);
2702 val = nr64_mac(reg);
2712 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2713 int num, int mac_pref)
2715 u64 val = nr64_mac(reg);
2716 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2719 val |= HOST_INFO_MPR;
2723 static int __set_rdc_table_num(struct niu *np,
2724 int xmac_index, int bmac_index,
2725 int rdc_table_num, int mac_pref)
2729 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2731 if (np->flags & NIU_FLAGS_XMAC)
2732 reg = XMAC_HOST_INFO(xmac_index);
2734 reg = BMAC_HOST_INFO(bmac_index);
2735 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2739 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2742 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2745 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2748 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2751 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2752 int table_num, int mac_pref)
2754 if (idx >= niu_num_alt_addr(np))
2756 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2759 static u64 vlan_entry_set_parity(u64 reg_val)
2764 port01_mask = 0x00ff;
2765 port23_mask = 0xff00;
2767 if (hweight64(reg_val & port01_mask) & 1)
2768 reg_val |= ENET_VLAN_TBL_PARITY0;
2770 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2772 if (hweight64(reg_val & port23_mask) & 1)
2773 reg_val |= ENET_VLAN_TBL_PARITY1;
2775 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2780 static void vlan_tbl_write(struct niu *np, unsigned long index,
2781 int port, int vpr, int rdc_table)
2783 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2785 reg_val &= ~((ENET_VLAN_TBL_VPR |
2786 ENET_VLAN_TBL_VLANRDCTBLN) <<
2787 ENET_VLAN_TBL_SHIFT(port));
2789 reg_val |= (ENET_VLAN_TBL_VPR <<
2790 ENET_VLAN_TBL_SHIFT(port));
2791 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2793 reg_val = vlan_entry_set_parity(reg_val);
2795 nw64(ENET_VLAN_TBL(index), reg_val);
2798 static void vlan_tbl_clear(struct niu *np)
2802 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2803 nw64(ENET_VLAN_TBL(i), 0);
2806 static int tcam_wait_bit(struct niu *np, u64 bit)
2810 while (--limit > 0) {
2811 if (nr64(TCAM_CTL) & bit)
2821 static int tcam_flush(struct niu *np, int index)
2823 nw64(TCAM_KEY_0, 0x00);
2824 nw64(TCAM_KEY_MASK_0, 0xff);
2825 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2827 return tcam_wait_bit(np, TCAM_CTL_STAT);
2831 static int tcam_read(struct niu *np, int index,
2832 u64 *key, u64 *mask)
2836 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2837 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2839 key[0] = nr64(TCAM_KEY_0);
2840 key[1] = nr64(TCAM_KEY_1);
2841 key[2] = nr64(TCAM_KEY_2);
2842 key[3] = nr64(TCAM_KEY_3);
2843 mask[0] = nr64(TCAM_KEY_MASK_0);
2844 mask[1] = nr64(TCAM_KEY_MASK_1);
2845 mask[2] = nr64(TCAM_KEY_MASK_2);
2846 mask[3] = nr64(TCAM_KEY_MASK_3);
2852 static int tcam_write(struct niu *np, int index,
2853 u64 *key, u64 *mask)
2855 nw64(TCAM_KEY_0, key[0]);
2856 nw64(TCAM_KEY_1, key[1]);
2857 nw64(TCAM_KEY_2, key[2]);
2858 nw64(TCAM_KEY_3, key[3]);
2859 nw64(TCAM_KEY_MASK_0, mask[0]);
2860 nw64(TCAM_KEY_MASK_1, mask[1]);
2861 nw64(TCAM_KEY_MASK_2, mask[2]);
2862 nw64(TCAM_KEY_MASK_3, mask[3]);
2863 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2865 return tcam_wait_bit(np, TCAM_CTL_STAT);
2869 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2873 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2874 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2876 *data = nr64(TCAM_KEY_1);
2882 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2884 nw64(TCAM_KEY_1, assoc_data);
2885 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2887 return tcam_wait_bit(np, TCAM_CTL_STAT);
2890 static void tcam_enable(struct niu *np, int on)
2892 u64 val = nr64(FFLP_CFG_1);
2895 val &= ~FFLP_CFG_1_TCAM_DIS;
2897 val |= FFLP_CFG_1_TCAM_DIS;
2898 nw64(FFLP_CFG_1, val);
2901 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2903 u64 val = nr64(FFLP_CFG_1);
2905 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2907 FFLP_CFG_1_CAMRATIO);
2908 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2909 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2910 nw64(FFLP_CFG_1, val);
2912 val = nr64(FFLP_CFG_1);
2913 val |= FFLP_CFG_1_FFLPINITDONE;
2914 nw64(FFLP_CFG_1, val);
2917 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2923 if (class < CLASS_CODE_ETHERTYPE1 ||
2924 class > CLASS_CODE_ETHERTYPE2)
2927 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2939 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2945 if (class < CLASS_CODE_ETHERTYPE1 ||
2946 class > CLASS_CODE_ETHERTYPE2 ||
2947 (ether_type & ~(u64)0xffff) != 0)
2950 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2952 val &= ~L2_CLS_ETYPE;
2953 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2960 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2966 if (class < CLASS_CODE_USER_PROG1 ||
2967 class > CLASS_CODE_USER_PROG4)
2970 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2973 val |= L3_CLS_VALID;
2975 val &= ~L3_CLS_VALID;
2981 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2982 int ipv6, u64 protocol_id,
2983 u64 tos_mask, u64 tos_val)
2988 if (class < CLASS_CODE_USER_PROG1 ||
2989 class > CLASS_CODE_USER_PROG4 ||
2990 (protocol_id & ~(u64)0xff) != 0 ||
2991 (tos_mask & ~(u64)0xff) != 0 ||
2992 (tos_val & ~(u64)0xff) != 0)
2995 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2997 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2998 L3_CLS_TOSMASK | L3_CLS_TOS);
3000 val |= L3_CLS_IPVER;
3001 val |= (protocol_id << L3_CLS_PID_SHIFT);
3002 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3003 val |= (tos_val << L3_CLS_TOS_SHIFT);
3009 static int tcam_early_init(struct niu *np)
3015 tcam_set_lat_and_ratio(np,
3016 DEFAULT_TCAM_LATENCY,
3017 DEFAULT_TCAM_ACCESS_RATIO);
3018 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3019 err = tcam_user_eth_class_enable(np, i, 0);
3023 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3024 err = tcam_user_ip_class_enable(np, i, 0);
3032 static int tcam_flush_all(struct niu *np)
3036 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3037 int err = tcam_flush(np, i);
3044 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3046 return ((u64)index | (num_entries == 1 ?
3047 HASH_TBL_ADDR_AUTOINC : 0));
3051 static int hash_read(struct niu *np, unsigned long partition,
3052 unsigned long index, unsigned long num_entries,
3055 u64 val = hash_addr_regval(index, num_entries);
3058 if (partition >= FCRAM_NUM_PARTITIONS ||
3059 index + num_entries > FCRAM_SIZE)
3062 nw64(HASH_TBL_ADDR(partition), val);
3063 for (i = 0; i < num_entries; i++)
3064 data[i] = nr64(HASH_TBL_DATA(partition));
3070 static int hash_write(struct niu *np, unsigned long partition,
3071 unsigned long index, unsigned long num_entries,
3074 u64 val = hash_addr_regval(index, num_entries);
3077 if (partition >= FCRAM_NUM_PARTITIONS ||
3078 index + (num_entries * 8) > FCRAM_SIZE)
3081 nw64(HASH_TBL_ADDR(partition), val);
3082 for (i = 0; i < num_entries; i++)
3083 nw64(HASH_TBL_DATA(partition), data[i]);
3088 static void fflp_reset(struct niu *np)
3092 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3094 nw64(FFLP_CFG_1, 0);
3096 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3097 nw64(FFLP_CFG_1, val);
3100 static void fflp_set_timings(struct niu *np)
3102 u64 val = nr64(FFLP_CFG_1);
3104 val &= ~FFLP_CFG_1_FFLPINITDONE;
3105 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3106 nw64(FFLP_CFG_1, val);
3108 val = nr64(FFLP_CFG_1);
3109 val |= FFLP_CFG_1_FFLPINITDONE;
3110 nw64(FFLP_CFG_1, val);
3112 val = nr64(FCRAM_REF_TMR);
3113 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3114 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3115 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3116 nw64(FCRAM_REF_TMR, val);
3119 static int fflp_set_partition(struct niu *np, u64 partition,
3120 u64 mask, u64 base, int enable)
3125 if (partition >= FCRAM_NUM_PARTITIONS ||
3126 (mask & ~(u64)0x1f) != 0 ||
3127 (base & ~(u64)0x1f) != 0)
3130 reg = FLW_PRT_SEL(partition);
3133 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3134 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3135 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3137 val |= FLW_PRT_SEL_EXT;
3143 static int fflp_disable_all_partitions(struct niu *np)
3147 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3148 int err = fflp_set_partition(np, 0, 0, 0, 0);
3155 static void fflp_llcsnap_enable(struct niu *np, int on)
3157 u64 val = nr64(FFLP_CFG_1);
3160 val |= FFLP_CFG_1_LLCSNAP;
3162 val &= ~FFLP_CFG_1_LLCSNAP;
3163 nw64(FFLP_CFG_1, val);
3166 static void fflp_errors_enable(struct niu *np, int on)
3168 u64 val = nr64(FFLP_CFG_1);
3171 val &= ~FFLP_CFG_1_ERRORDIS;
3173 val |= FFLP_CFG_1_ERRORDIS;
3174 nw64(FFLP_CFG_1, val);
3177 static int fflp_hash_clear(struct niu *np)
3179 struct fcram_hash_ipv4 ent;
3182 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3183 memset(&ent, 0, sizeof(ent));
3184 ent.header = HASH_HEADER_EXT;
3186 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3187 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3194 static int fflp_early_init(struct niu *np)
3196 struct niu_parent *parent;
3197 unsigned long flags;
3200 niu_lock_parent(np, flags);
3202 parent = np->parent;
3204 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3205 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3207 fflp_set_timings(np);
3208 err = fflp_disable_all_partitions(np);
3210 netif_printk(np, probe, KERN_DEBUG, np->dev,
3211 "fflp_disable_all_partitions failed, err=%d\n",
3217 err = tcam_early_init(np);
3219 netif_printk(np, probe, KERN_DEBUG, np->dev,
3220 "tcam_early_init failed, err=%d\n", err);
3223 fflp_llcsnap_enable(np, 1);
3224 fflp_errors_enable(np, 0);
3228 err = tcam_flush_all(np);
3230 netif_printk(np, probe, KERN_DEBUG, np->dev,
3231 "tcam_flush_all failed, err=%d\n", err);
3234 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3235 err = fflp_hash_clear(np);
3237 netif_printk(np, probe, KERN_DEBUG, np->dev,
3238 "fflp_hash_clear failed, err=%d\n",
3246 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3249 niu_unlock_parent(np, flags);
3253 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3255 if (class_code < CLASS_CODE_USER_PROG1 ||
3256 class_code > CLASS_CODE_SCTP_IPV6)
3259 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3263 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3265 if (class_code < CLASS_CODE_USER_PROG1 ||
3266 class_code > CLASS_CODE_SCTP_IPV6)
3269 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3273 /* Entries for the ports are interleaved in the TCAM */
3274 static u16 tcam_get_index(struct niu *np, u16 idx)
3276 /* One entry reserved for IP fragment rule */
3277 if (idx >= (np->clas.tcam_sz - 1))
3279 return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3282 static u16 tcam_get_size(struct niu *np)
3284 /* One entry reserved for IP fragment rule */
3285 return np->clas.tcam_sz - 1;
3288 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3290 /* One entry reserved for IP fragment rule */
3291 return np->clas.tcam_valid_entries - 1;
3294 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3295 u32 offset, u32 size)
3297 int i = skb_shinfo(skb)->nr_frags;
3298 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3301 frag->page_offset = offset;
3305 skb->data_len += size;
3306 skb->truesize += size;
3308 skb_shinfo(skb)->nr_frags = i + 1;
3311 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3314 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3316 return (a & (MAX_RBR_RING_SIZE - 1));
3319 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3320 struct page ***link)
3322 unsigned int h = niu_hash_rxaddr(rp, addr);
3323 struct page *p, **pp;
3326 pp = &rp->rxhash[h];
3327 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3328 if (p->index == addr) {
3339 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3341 unsigned int h = niu_hash_rxaddr(rp, base);
3344 page->mapping = (struct address_space *) rp->rxhash[h];
3345 rp->rxhash[h] = page;
3348 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3349 gfp_t mask, int start_index)
3355 page = alloc_page(mask);
3359 addr = np->ops->map_page(np->device, page, 0,
3360 PAGE_SIZE, DMA_FROM_DEVICE);
3362 niu_hash_page(rp, page, addr);
3363 if (rp->rbr_blocks_per_page > 1)
3364 atomic_add(rp->rbr_blocks_per_page - 1,
3365 &compound_head(page)->_count);
3367 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3368 __le32 *rbr = &rp->rbr[start_index + i];
3370 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3371 addr += rp->rbr_block_size;
3377 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3379 int index = rp->rbr_index;
3382 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3383 int err = niu_rbr_add_page(np, rp, mask, index);
3385 if (unlikely(err)) {
3390 rp->rbr_index += rp->rbr_blocks_per_page;
3391 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3392 if (rp->rbr_index == rp->rbr_table_size)
3395 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3396 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3397 rp->rbr_pending = 0;
3402 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3404 unsigned int index = rp->rcr_index;
3409 struct page *page, **link;
3415 val = le64_to_cpup(&rp->rcr[index]);
3416 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3417 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3418 page = niu_find_rxpage(rp, addr, &link);
3420 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3421 RCR_ENTRY_PKTBUFSZ_SHIFT];
3422 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3423 *link = (struct page *) page->mapping;
3424 np->ops->unmap_page(np->device, page->index,
3425 PAGE_SIZE, DMA_FROM_DEVICE);
3427 page->mapping = NULL;
3429 rp->rbr_refill_pending++;
3432 index = NEXT_RCR(rp, index);
3433 if (!(val & RCR_ENTRY_MULTI))
3437 rp->rcr_index = index;
3442 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3443 struct rx_ring_info *rp)
3445 unsigned int index = rp->rcr_index;
3446 struct rx_pkt_hdr1 *rh;
3447 struct sk_buff *skb;
3450 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3452 return niu_rx_pkt_ignore(np, rp);
3456 struct page *page, **link;
3457 u32 rcr_size, append_size;
3462 val = le64_to_cpup(&rp->rcr[index]);
3464 len = (val & RCR_ENTRY_L2_LEN) >>
3465 RCR_ENTRY_L2_LEN_SHIFT;
3468 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3469 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3470 page = niu_find_rxpage(rp, addr, &link);
3472 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3473 RCR_ENTRY_PKTBUFSZ_SHIFT];
3475 off = addr & ~PAGE_MASK;
3476 append_size = rcr_size;
3480 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3481 if ((ptype == RCR_PKT_TYPE_TCP ||
3482 ptype == RCR_PKT_TYPE_UDP) &&
3483 !(val & (RCR_ENTRY_NOPORT |
3485 skb->ip_summed = CHECKSUM_UNNECESSARY;
3487 skb->ip_summed = CHECKSUM_NONE;
3488 } else if (!(val & RCR_ENTRY_MULTI))
3489 append_size = len - skb->len;
3491 niu_rx_skb_append(skb, page, off, append_size);
3492 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3493 *link = (struct page *) page->mapping;
3494 np->ops->unmap_page(np->device, page->index,
3495 PAGE_SIZE, DMA_FROM_DEVICE);
3497 page->mapping = NULL;
3498 rp->rbr_refill_pending++;
3502 index = NEXT_RCR(rp, index);
3503 if (!(val & RCR_ENTRY_MULTI))
3507 rp->rcr_index = index;
3510 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3511 __pskb_pull_tail(skb, len);
3513 rh = (struct rx_pkt_hdr1 *) skb->data;
3514 if (np->dev->features & NETIF_F_RXHASH)
3515 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3516 (u32)rh->hashval2_1 << 16 |
3517 (u32)rh->hashval1_1 << 8 |
3518 (u32)rh->hashval1_2 << 0);
3519 skb_pull(skb, sizeof(*rh));
3522 rp->rx_bytes += skb->len;
3524 skb->protocol = eth_type_trans(skb, np->dev);
3525 skb_record_rx_queue(skb, rp->rx_channel);
3526 napi_gro_receive(napi, skb);
3531 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3533 int blocks_per_page = rp->rbr_blocks_per_page;
3534 int err, index = rp->rbr_index;
3537 while (index < (rp->rbr_table_size - blocks_per_page)) {
3538 err = niu_rbr_add_page(np, rp, mask, index);
3542 index += blocks_per_page;
3545 rp->rbr_index = index;
3549 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3553 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3556 page = rp->rxhash[i];
3558 struct page *next = (struct page *) page->mapping;
3559 u64 base = page->index;
3561 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3564 page->mapping = NULL;
3572 for (i = 0; i < rp->rbr_table_size; i++)
3573 rp->rbr[i] = cpu_to_le32(0);
3577 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3579 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3580 struct sk_buff *skb = tb->skb;
3581 struct tx_pkt_hdr *tp;
3585 tp = (struct tx_pkt_hdr *) skb->data;
3586 tx_flags = le64_to_cpup(&tp->flags);
3589 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3590 ((tx_flags & TXHDR_PAD) / 2));
3592 len = skb_headlen(skb);
3593 np->ops->unmap_single(np->device, tb->mapping,
3594 len, DMA_TO_DEVICE);
3596 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3601 idx = NEXT_TX(rp, idx);
3602 len -= MAX_TX_DESC_LEN;
3605 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3606 tb = &rp->tx_buffs[idx];
3607 BUG_ON(tb->skb != NULL);
3608 np->ops->unmap_page(np->device, tb->mapping,
3609 skb_shinfo(skb)->frags[i].size,
3611 idx = NEXT_TX(rp, idx);
3619 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3621 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3623 struct netdev_queue *txq;
3628 index = (rp - np->tx_rings);
3629 txq = netdev_get_tx_queue(np->dev, index);
3632 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3635 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3636 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3637 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3639 rp->last_pkt_cnt = tmp;
3643 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3644 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3647 cons = release_tx_packet(np, rp, cons);
3653 if (unlikely(netif_tx_queue_stopped(txq) &&
3654 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3655 __netif_tx_lock(txq, smp_processor_id());
3656 if (netif_tx_queue_stopped(txq) &&
3657 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3658 netif_tx_wake_queue(txq);
3659 __netif_tx_unlock(txq);
3663 static inline void niu_sync_rx_discard_stats(struct niu *np,
3664 struct rx_ring_info *rp,
3667 /* This elaborate scheme is needed for reading the RX discard
3668 * counters, as they are only 16-bit and can overflow quickly,
3669 * and because the overflow indication bit is not usable as
3670 * the counter value does not wrap, but remains at max value
3673 * In theory and in practice counters can be lost in between
3674 * reading nr64() and clearing the counter nw64(). For this
3675 * reason, the number of counter clearings nw64() is
3676 * limited/reduced though the limit parameter.
3678 int rx_channel = rp->rx_channel;
3681 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3682 * following discard events: IPP (Input Port Process),
3683 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3684 * Block Ring) prefetch buffer is empty.
3686 misc = nr64(RXMISC(rx_channel));
3687 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3688 nw64(RXMISC(rx_channel), 0);
3689 rp->rx_errors += misc & RXMISC_COUNT;
3691 if (unlikely(misc & RXMISC_OFLOW))
3692 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3695 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3696 "rx-%d: MISC drop=%u over=%u\n",
3697 rx_channel, misc, misc-limit);
3700 /* WRED (Weighted Random Early Discard) by hardware */
3701 wred = nr64(RED_DIS_CNT(rx_channel));
3702 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3703 nw64(RED_DIS_CNT(rx_channel), 0);
3704 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3706 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3707 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3709 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3710 "rx-%d: WRED drop=%u over=%u\n",
3711 rx_channel, wred, wred-limit);
3715 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3716 struct rx_ring_info *rp, int budget)
3718 int qlen, rcr_done = 0, work_done = 0;
3719 struct rxdma_mailbox *mbox = rp->mbox;
3723 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3724 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3726 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3727 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3729 mbox->rx_dma_ctl_stat = 0;
3730 mbox->rcrstat_a = 0;
3732 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3733 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3734 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3736 rcr_done = work_done = 0;
3737 qlen = min(qlen, budget);
3738 while (work_done < qlen) {
3739 rcr_done += niu_process_rx_pkt(napi, np, rp);
3743 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3746 for (i = 0; i < rp->rbr_refill_pending; i++)
3747 niu_rbr_refill(np, rp, GFP_ATOMIC);
3748 rp->rbr_refill_pending = 0;
3751 stat = (RX_DMA_CTL_STAT_MEX |
3752 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3753 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3755 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3757 /* Only sync discards stats when qlen indicate potential for drops */
3759 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3764 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3767 u32 tx_vec = (v0 >> 32);
3768 u32 rx_vec = (v0 & 0xffffffff);
3769 int i, work_done = 0;
3771 netif_printk(np, intr, KERN_DEBUG, np->dev,
3772 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3774 for (i = 0; i < np->num_tx_rings; i++) {
3775 struct tx_ring_info *rp = &np->tx_rings[i];
3776 if (tx_vec & (1 << rp->tx_channel))
3777 niu_tx_work(np, rp);
3778 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3781 for (i = 0; i < np->num_rx_rings; i++) {
3782 struct rx_ring_info *rp = &np->rx_rings[i];
3784 if (rx_vec & (1 << rp->rx_channel)) {
3787 this_work_done = niu_rx_work(&lp->napi, np, rp,
3790 budget -= this_work_done;
3791 work_done += this_work_done;
3793 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3799 static int niu_poll(struct napi_struct *napi, int budget)
3801 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3802 struct niu *np = lp->np;
3805 work_done = niu_poll_core(np, lp, budget);
3807 if (work_done < budget) {
3808 napi_complete(napi);
3809 niu_ldg_rearm(np, lp, 1);
3814 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3817 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3819 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3820 pr_cont("RBR_TMOUT ");
3821 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3822 pr_cont("RSP_CNT ");
3823 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3824 pr_cont("BYTE_EN_BUS ");
3825 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3826 pr_cont("RSP_DAT ");
3827 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3828 pr_cont("RCR_ACK ");
3829 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3830 pr_cont("RCR_SHA_PAR ");
3831 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3832 pr_cont("RBR_PRE_PAR ");
3833 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3835 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3836 pr_cont("RCRINCON ");
3837 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3838 pr_cont("RCRFULL ");
3839 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3840 pr_cont("RBRFULL ");
3841 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3842 pr_cont("RBRLOGPAGE ");
3843 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3844 pr_cont("CFIGLOGPAGE ");
3845 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3846 pr_cont("DC_FIDO ");
3851 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3853 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3857 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3858 RX_DMA_CTL_STAT_PORT_FATAL))
3862 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3864 (unsigned long long) stat);
3866 niu_log_rxchan_errors(np, rp, stat);
3869 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3870 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3875 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3878 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3880 if (cs & TX_CS_MBOX_ERR)
3882 if (cs & TX_CS_PKT_SIZE_ERR)
3883 pr_cont("PKT_SIZE ");
3884 if (cs & TX_CS_TX_RING_OFLOW)
3885 pr_cont("TX_RING_OFLOW ");
3886 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3887 pr_cont("PREF_BUF_PAR ");
3888 if (cs & TX_CS_NACK_PREF)
3889 pr_cont("NACK_PREF ");
3890 if (cs & TX_CS_NACK_PKT_RD)
3891 pr_cont("NACK_PKT_RD ");
3892 if (cs & TX_CS_CONF_PART_ERR)
3893 pr_cont("CONF_PART ");
3894 if (cs & TX_CS_PKT_PRT_ERR)
3895 pr_cont("PKT_PTR ");
3900 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3904 cs = nr64(TX_CS(rp->tx_channel));
3905 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3906 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3908 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3910 (unsigned long long)cs,
3911 (unsigned long long)logh,
3912 (unsigned long long)logl);
3914 niu_log_txchan_errors(np, rp, cs);
3919 static int niu_mif_interrupt(struct niu *np)
3921 u64 mif_status = nr64(MIF_STATUS);
3924 if (np->flags & NIU_FLAGS_XMAC) {
3925 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3927 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3931 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3932 (unsigned long long)mif_status, phy_mdint);
3937 static void niu_xmac_interrupt(struct niu *np)
3939 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3942 val = nr64_mac(XTXMAC_STATUS);
3943 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3944 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3945 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3946 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3947 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3948 mp->tx_fifo_errors++;
3949 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3950 mp->tx_overflow_errors++;
3951 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3952 mp->tx_max_pkt_size_errors++;
3953 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3954 mp->tx_underflow_errors++;
3956 val = nr64_mac(XRXMAC_STATUS);
3957 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3958 mp->rx_local_faults++;
3959 if (val & XRXMAC_STATUS_RFLT_DET)
3960 mp->rx_remote_faults++;
3961 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3962 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3963 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3964 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3965 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3966 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3967 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3968 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3969 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3970 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3971 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3972 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3973 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3974 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3975 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3976 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3977 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3978 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3979 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3980 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3981 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3982 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3983 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3984 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3985 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3986 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3987 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3988 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3989 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3990 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3991 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3992 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3993 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3994 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3995 if (val & XRXMAC_STATUS_RXUFLOW)
3996 mp->rx_underflows++;
3997 if (val & XRXMAC_STATUS_RXOFLOW)
4000 val = nr64_mac(XMAC_FC_STAT);
4001 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4002 mp->pause_off_state++;
4003 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4004 mp->pause_on_state++;
4005 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4006 mp->pause_received++;
4009 static void niu_bmac_interrupt(struct niu *np)
4011 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4014 val = nr64_mac(BTXMAC_STATUS);
4015 if (val & BTXMAC_STATUS_UNDERRUN)
4016 mp->tx_underflow_errors++;
4017 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4018 mp->tx_max_pkt_size_errors++;
4019 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4020 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4021 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4022 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4024 val = nr64_mac(BRXMAC_STATUS);
4025 if (val & BRXMAC_STATUS_OVERFLOW)
4027 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4028 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4029 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4030 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4031 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4032 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4033 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4034 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4036 val = nr64_mac(BMAC_CTRL_STATUS);
4037 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4038 mp->pause_off_state++;
4039 if (val & BMAC_CTRL_STATUS_PAUSE)
4040 mp->pause_on_state++;
4041 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4042 mp->pause_received++;
4045 static int niu_mac_interrupt(struct niu *np)
4047 if (np->flags & NIU_FLAGS_XMAC)
4048 niu_xmac_interrupt(np);
4050 niu_bmac_interrupt(np);
4055 static void niu_log_device_error(struct niu *np, u64 stat)
4057 netdev_err(np->dev, "Core device errors ( ");
4059 if (stat & SYS_ERR_MASK_META2)
4061 if (stat & SYS_ERR_MASK_META1)
4063 if (stat & SYS_ERR_MASK_PEU)
4065 if (stat & SYS_ERR_MASK_TXC)
4067 if (stat & SYS_ERR_MASK_RDMC)
4069 if (stat & SYS_ERR_MASK_TDMC)
4071 if (stat & SYS_ERR_MASK_ZCP)
4073 if (stat & SYS_ERR_MASK_FFLP)
4075 if (stat & SYS_ERR_MASK_IPP)
4077 if (stat & SYS_ERR_MASK_MAC)
4079 if (stat & SYS_ERR_MASK_SMX)
4085 static int niu_device_error(struct niu *np)
4087 u64 stat = nr64(SYS_ERR_STAT);
4089 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4090 (unsigned long long)stat);
4092 niu_log_device_error(np, stat);
4097 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4098 u64 v0, u64 v1, u64 v2)
4107 if (v1 & 0x00000000ffffffffULL) {
4108 u32 rx_vec = (v1 & 0xffffffff);
4110 for (i = 0; i < np->num_rx_rings; i++) {
4111 struct rx_ring_info *rp = &np->rx_rings[i];
4113 if (rx_vec & (1 << rp->rx_channel)) {
4114 int r = niu_rx_error(np, rp);
4119 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4120 RX_DMA_CTL_STAT_MEX);
4125 if (v1 & 0x7fffffff00000000ULL) {
4126 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4128 for (i = 0; i < np->num_tx_rings; i++) {
4129 struct tx_ring_info *rp = &np->tx_rings[i];
4131 if (tx_vec & (1 << rp->tx_channel)) {
4132 int r = niu_tx_error(np, rp);
4138 if ((v0 | v1) & 0x8000000000000000ULL) {
4139 int r = niu_mif_interrupt(np);
4145 int r = niu_mac_interrupt(np);
4150 int r = niu_device_error(np);
4157 niu_enable_interrupts(np, 0);
4162 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4165 struct rxdma_mailbox *mbox = rp->mbox;
4166 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4168 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4169 RX_DMA_CTL_STAT_RCRTO);
4170 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4172 netif_printk(np, intr, KERN_DEBUG, np->dev,
4173 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4176 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4179 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4181 netif_printk(np, intr, KERN_DEBUG, np->dev,
4182 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4185 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4187 struct niu_parent *parent = np->parent;
4191 tx_vec = (v0 >> 32);
4192 rx_vec = (v0 & 0xffffffff);
4194 for (i = 0; i < np->num_rx_rings; i++) {
4195 struct rx_ring_info *rp = &np->rx_rings[i];
4196 int ldn = LDN_RXDMA(rp->rx_channel);
4198 if (parent->ldg_map[ldn] != ldg)
4201 nw64(LD_IM0(ldn), LD_IM0_MASK);
4202 if (rx_vec & (1 << rp->rx_channel))
4203 niu_rxchan_intr(np, rp, ldn);
4206 for (i = 0; i < np->num_tx_rings; i++) {
4207 struct tx_ring_info *rp = &np->tx_rings[i];
4208 int ldn = LDN_TXDMA(rp->tx_channel);
4210 if (parent->ldg_map[ldn] != ldg)
4213 nw64(LD_IM0(ldn), LD_IM0_MASK);
4214 if (tx_vec & (1 << rp->tx_channel))
4215 niu_txchan_intr(np, rp, ldn);
4219 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4220 u64 v0, u64 v1, u64 v2)
4222 if (likely(napi_schedule_prep(&lp->napi))) {
4226 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4227 __napi_schedule(&lp->napi);
4231 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4233 struct niu_ldg *lp = dev_id;
4234 struct niu *np = lp->np;
4235 int ldg = lp->ldg_num;
4236 unsigned long flags;
4239 if (netif_msg_intr(np))
4240 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4243 spin_lock_irqsave(&np->lock, flags);
4245 v0 = nr64(LDSV0(ldg));
4246 v1 = nr64(LDSV1(ldg));
4247 v2 = nr64(LDSV2(ldg));
4249 if (netif_msg_intr(np))
4250 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4251 (unsigned long long) v0,
4252 (unsigned long long) v1,
4253 (unsigned long long) v2);
4255 if (unlikely(!v0 && !v1 && !v2)) {
4256 spin_unlock_irqrestore(&np->lock, flags);
4260 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4261 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4265 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4266 niu_schedule_napi(np, lp, v0, v1, v2);
4268 niu_ldg_rearm(np, lp, 1);
4270 spin_unlock_irqrestore(&np->lock, flags);
4275 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4278 np->ops->free_coherent(np->device,
4279 sizeof(struct rxdma_mailbox),
4280 rp->mbox, rp->mbox_dma);
4284 np->ops->free_coherent(np->device,
4285 MAX_RCR_RING_SIZE * sizeof(__le64),
4286 rp->rcr, rp->rcr_dma);
4288 rp->rcr_table_size = 0;
4292 niu_rbr_free(np, rp);
4294 np->ops->free_coherent(np->device,
4295 MAX_RBR_RING_SIZE * sizeof(__le32),
4296 rp->rbr, rp->rbr_dma);
4298 rp->rbr_table_size = 0;
4305 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4308 np->ops->free_coherent(np->device,
4309 sizeof(struct txdma_mailbox),
4310 rp->mbox, rp->mbox_dma);
4316 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4317 if (rp->tx_buffs[i].skb)
4318 (void) release_tx_packet(np, rp, i);
4321 np->ops->free_coherent(np->device,
4322 MAX_TX_RING_SIZE * sizeof(__le64),
4323 rp->descr, rp->descr_dma);
4332 static void niu_free_channels(struct niu *np)
4337 for (i = 0; i < np->num_rx_rings; i++) {
4338 struct rx_ring_info *rp = &np->rx_rings[i];
4340 niu_free_rx_ring_info(np, rp);
4342 kfree(np->rx_rings);
4343 np->rx_rings = NULL;
4344 np->num_rx_rings = 0;
4348 for (i = 0; i < np->num_tx_rings; i++) {
4349 struct tx_ring_info *rp = &np->tx_rings[i];
4351 niu_free_tx_ring_info(np, rp);
4353 kfree(np->tx_rings);
4354 np->tx_rings = NULL;
4355 np->num_tx_rings = 0;
4359 static int niu_alloc_rx_ring_info(struct niu *np,
4360 struct rx_ring_info *rp)
4362 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4364 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4369 rp->mbox = np->ops->alloc_coherent(np->device,
4370 sizeof(struct rxdma_mailbox),
4371 &rp->mbox_dma, GFP_KERNEL);
4374 if ((unsigned long)rp->mbox & (64UL - 1)) {
4375 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4380 rp->rcr = np->ops->alloc_coherent(np->device,
4381 MAX_RCR_RING_SIZE * sizeof(__le64),
4382 &rp->rcr_dma, GFP_KERNEL);
4385 if ((unsigned long)rp->rcr & (64UL - 1)) {
4386 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4390 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4393 rp->rbr = np->ops->alloc_coherent(np->device,
4394 MAX_RBR_RING_SIZE * sizeof(__le32),
4395 &rp->rbr_dma, GFP_KERNEL);
4398 if ((unsigned long)rp->rbr & (64UL - 1)) {
4399 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4403 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4405 rp->rbr_pending = 0;
4410 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4412 int mtu = np->dev->mtu;
4414 /* These values are recommended by the HW designers for fair
4415 * utilization of DRR amongst the rings.
4417 rp->max_burst = mtu + 32;
4418 if (rp->max_burst > 4096)
4419 rp->max_burst = 4096;
4422 static int niu_alloc_tx_ring_info(struct niu *np,
4423 struct tx_ring_info *rp)
4425 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4427 rp->mbox = np->ops->alloc_coherent(np->device,
4428 sizeof(struct txdma_mailbox),
4429 &rp->mbox_dma, GFP_KERNEL);
4432 if ((unsigned long)rp->mbox & (64UL - 1)) {
4433 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4438 rp->descr = np->ops->alloc_coherent(np->device,
4439 MAX_TX_RING_SIZE * sizeof(__le64),
4440 &rp->descr_dma, GFP_KERNEL);
4443 if ((unsigned long)rp->descr & (64UL - 1)) {
4444 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4449 rp->pending = MAX_TX_RING_SIZE;
4454 /* XXX make these configurable... XXX */
4455 rp->mark_freq = rp->pending / 4;
4457 niu_set_max_burst(np, rp);
4462 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4466 bss = min(PAGE_SHIFT, 15);
4468 rp->rbr_block_size = 1 << bss;
4469 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4471 rp->rbr_sizes[0] = 256;
4472 rp->rbr_sizes[1] = 1024;
4473 if (np->dev->mtu > ETH_DATA_LEN) {
4474 switch (PAGE_SIZE) {
4476 rp->rbr_sizes[2] = 4096;
4480 rp->rbr_sizes[2] = 8192;
4484 rp->rbr_sizes[2] = 2048;
4486 rp->rbr_sizes[3] = rp->rbr_block_size;
4489 static int niu_alloc_channels(struct niu *np)
4491 struct niu_parent *parent = np->parent;
4492 int first_rx_channel, first_tx_channel;
4496 first_rx_channel = first_tx_channel = 0;
4497 for (i = 0; i < port; i++) {
4498 first_rx_channel += parent->rxchan_per_port[i];
4499 first_tx_channel += parent->txchan_per_port[i];
4502 np->num_rx_rings = parent->rxchan_per_port[port];
4503 np->num_tx_rings = parent->txchan_per_port[port];
4505 np->dev->real_num_tx_queues = np->num_tx_rings;
4507 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4513 for (i = 0; i < np->num_rx_rings; i++) {
4514 struct rx_ring_info *rp = &np->rx_rings[i];
4517 rp->rx_channel = first_rx_channel + i;
4519 err = niu_alloc_rx_ring_info(np, rp);
4523 niu_size_rbr(np, rp);
4525 /* XXX better defaults, configurable, etc... XXX */
4526 rp->nonsyn_window = 64;
4527 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4528 rp->syn_window = 64;
4529 rp->syn_threshold = rp->rcr_table_size - 64;
4530 rp->rcr_pkt_threshold = 16;
4531 rp->rcr_timeout = 8;
4532 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4533 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4534 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4536 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4541 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4547 for (i = 0; i < np->num_tx_rings; i++) {
4548 struct tx_ring_info *rp = &np->tx_rings[i];
4551 rp->tx_channel = first_tx_channel + i;
4553 err = niu_alloc_tx_ring_info(np, rp);
4561 niu_free_channels(np);
4565 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4569 while (--limit > 0) {
4570 u64 val = nr64(TX_CS(channel));
4571 if (val & TX_CS_SNG_STATE)
4577 static int niu_tx_channel_stop(struct niu *np, int channel)
4579 u64 val = nr64(TX_CS(channel));
4581 val |= TX_CS_STOP_N_GO;
4582 nw64(TX_CS(channel), val);
4584 return niu_tx_cs_sng_poll(np, channel);
4587 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4591 while (--limit > 0) {
4592 u64 val = nr64(TX_CS(channel));
4593 if (!(val & TX_CS_RST))
4599 static int niu_tx_channel_reset(struct niu *np, int channel)
4601 u64 val = nr64(TX_CS(channel));
4605 nw64(TX_CS(channel), val);
4607 err = niu_tx_cs_reset_poll(np, channel);
4609 nw64(TX_RING_KICK(channel), 0);
4614 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4618 nw64(TX_LOG_MASK1(channel), 0);
4619 nw64(TX_LOG_VAL1(channel), 0);
4620 nw64(TX_LOG_MASK2(channel), 0);
4621 nw64(TX_LOG_VAL2(channel), 0);
4622 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4623 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4624 nw64(TX_LOG_PAGE_HDL(channel), 0);
4626 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4627 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4628 nw64(TX_LOG_PAGE_VLD(channel), val);
4630 /* XXX TXDMA 32bit mode? XXX */
4635 static void niu_txc_enable_port(struct niu *np, int on)
4637 unsigned long flags;
4640 niu_lock_parent(np, flags);
4641 val = nr64(TXC_CONTROL);
4642 mask = (u64)1 << np->port;
4644 val |= TXC_CONTROL_ENABLE | mask;
4647 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4648 val &= ~TXC_CONTROL_ENABLE;
4650 nw64(TXC_CONTROL, val);
4651 niu_unlock_parent(np, flags);
4654 static void niu_txc_set_imask(struct niu *np, u64 imask)
4656 unsigned long flags;
4659 niu_lock_parent(np, flags);
4660 val = nr64(TXC_INT_MASK);
4661 val &= ~TXC_INT_MASK_VAL(np->port);
4662 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4663 niu_unlock_parent(np, flags);
4666 static void niu_txc_port_dma_enable(struct niu *np, int on)
4673 for (i = 0; i < np->num_tx_rings; i++)
4674 val |= (1 << np->tx_rings[i].tx_channel);
4676 nw64(TXC_PORT_DMA(np->port), val);
4679 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4681 int err, channel = rp->tx_channel;
4684 err = niu_tx_channel_stop(np, channel);
4688 err = niu_tx_channel_reset(np, channel);
4692 err = niu_tx_channel_lpage_init(np, channel);
4696 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4697 nw64(TX_ENT_MSK(channel), 0);
4699 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4700 TX_RNG_CFIG_STADDR)) {
4701 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4702 channel, (unsigned long long)rp->descr_dma);
4706 /* The length field in TX_RNG_CFIG is measured in 64-byte
4707 * blocks. rp->pending is the number of TX descriptors in
4708 * our ring, 8 bytes each, thus we divide by 8 bytes more
4709 * to get the proper value the chip wants.
4711 ring_len = (rp->pending / 8);
4713 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4715 nw64(TX_RNG_CFIG(channel), val);
4717 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4718 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4719 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4720 channel, (unsigned long long)rp->mbox_dma);
4723 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4724 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4726 nw64(TX_CS(channel), 0);
4728 rp->last_pkt_cnt = 0;
4733 static void niu_init_rdc_groups(struct niu *np)
4735 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4736 int i, first_table_num = tp->first_table_num;
4738 for (i = 0; i < tp->num_tables; i++) {
4739 struct rdc_table *tbl = &tp->tables[i];
4740 int this_table = first_table_num + i;
4743 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4744 nw64(RDC_TBL(this_table, slot),
4745 tbl->rxdma_channel[slot]);
4748 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4751 static void niu_init_drr_weight(struct niu *np)
4753 int type = phy_decode(np->parent->port_phy, np->port);
4758 val = PT_DRR_WEIGHT_DEFAULT_10G;
4763 val = PT_DRR_WEIGHT_DEFAULT_1G;
4766 nw64(PT_DRR_WT(np->port), val);
4769 static int niu_init_hostinfo(struct niu *np)
4771 struct niu_parent *parent = np->parent;
4772 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4773 int i, err, num_alt = niu_num_alt_addr(np);
4774 int first_rdc_table = tp->first_table_num;
4776 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4780 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4784 for (i = 0; i < num_alt; i++) {
4785 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4793 static int niu_rx_channel_reset(struct niu *np, int channel)
4795 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4796 RXDMA_CFIG1_RST, 1000, 10,
4800 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4804 nw64(RX_LOG_MASK1(channel), 0);
4805 nw64(RX_LOG_VAL1(channel), 0);
4806 nw64(RX_LOG_MASK2(channel), 0);
4807 nw64(RX_LOG_VAL2(channel), 0);
4808 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4809 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4810 nw64(RX_LOG_PAGE_HDL(channel), 0);
4812 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4813 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4814 nw64(RX_LOG_PAGE_VLD(channel), val);
4819 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4823 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4824 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4825 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4826 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4827 nw64(RDC_RED_PARA(rp->rx_channel), val);
4830 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4835 switch (rp->rbr_block_size) {
4837 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4840 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4843 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4846 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4851 val |= RBR_CFIG_B_VLD2;
4852 switch (rp->rbr_sizes[2]) {
4854 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4857 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4860 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4863 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4869 val |= RBR_CFIG_B_VLD1;
4870 switch (rp->rbr_sizes[1]) {
4872 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4875 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4878 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4881 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4887 val |= RBR_CFIG_B_VLD0;
4888 switch (rp->rbr_sizes[0]) {
4890 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4893 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4896 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4899 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4910 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4912 u64 val = nr64(RXDMA_CFIG1(channel));
4916 val |= RXDMA_CFIG1_EN;
4918 val &= ~RXDMA_CFIG1_EN;
4919 nw64(RXDMA_CFIG1(channel), val);
4922 while (--limit > 0) {
4923 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4932 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4934 int err, channel = rp->rx_channel;
4937 err = niu_rx_channel_reset(np, channel);
4941 err = niu_rx_channel_lpage_init(np, channel);
4945 niu_rx_channel_wred_init(np, rp);
4947 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4948 nw64(RX_DMA_CTL_STAT(channel),
4949 (RX_DMA_CTL_STAT_MEX |
4950 RX_DMA_CTL_STAT_RCRTHRES |
4951 RX_DMA_CTL_STAT_RCRTO |
4952 RX_DMA_CTL_STAT_RBR_EMPTY));
4953 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4954 nw64(RXDMA_CFIG2(channel),
4955 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4956 RXDMA_CFIG2_FULL_HDR));
4957 nw64(RBR_CFIG_A(channel),
4958 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4959 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4960 err = niu_compute_rbr_cfig_b(rp, &val);
4963 nw64(RBR_CFIG_B(channel), val);
4964 nw64(RCRCFIG_A(channel),
4965 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4966 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4967 nw64(RCRCFIG_B(channel),
4968 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4970 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4972 err = niu_enable_rx_channel(np, channel, 1);
4976 nw64(RBR_KICK(channel), rp->rbr_index);
4978 val = nr64(RX_DMA_CTL_STAT(channel));
4979 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4980 nw64(RX_DMA_CTL_STAT(channel), val);
4985 static int niu_init_rx_channels(struct niu *np)
4987 unsigned long flags;
4988 u64 seed = jiffies_64;
4991 niu_lock_parent(np, flags);
4992 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4993 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4994 niu_unlock_parent(np, flags);
4996 /* XXX RXDMA 32bit mode? XXX */
4998 niu_init_rdc_groups(np);
4999 niu_init_drr_weight(np);
5001 err = niu_init_hostinfo(np);
5005 for (i = 0; i < np->num_rx_rings; i++) {
5006 struct rx_ring_info *rp = &np->rx_rings[i];
5008 err = niu_init_one_rx_channel(np, rp);
5016 static int niu_set_ip_frag_rule(struct niu *np)
5018 struct niu_parent *parent = np->parent;
5019 struct niu_classifier *cp = &np->clas;
5020 struct niu_tcam_entry *tp;
5023 index = cp->tcam_top;
5024 tp = &parent->tcam[index];
5026 /* Note that the noport bit is the same in both ipv4 and
5027 * ipv6 format TCAM entries.
5029 memset(tp, 0, sizeof(*tp));
5030 tp->key[1] = TCAM_V4KEY1_NOPORT;
5031 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5032 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5033 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5034 err = tcam_write(np, index, tp->key, tp->key_mask);
5037 err = tcam_assoc_write(np, index, tp->assoc_data);
5041 cp->tcam_valid_entries++;
5046 static int niu_init_classifier_hw(struct niu *np)
5048 struct niu_parent *parent = np->parent;
5049 struct niu_classifier *cp = &np->clas;
5052 nw64(H1POLY, cp->h1_init);
5053 nw64(H2POLY, cp->h2_init);
5055 err = niu_init_hostinfo(np);
5059 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5060 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5062 vlan_tbl_write(np, i, np->port,
5063 vp->vlan_pref, vp->rdc_num);
5066 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5067 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5069 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5070 ap->rdc_num, ap->mac_pref);
5075 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5076 int index = i - CLASS_CODE_USER_PROG1;
5078 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5081 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5086 err = niu_set_ip_frag_rule(np);
5095 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5097 nw64(ZCP_RAM_DATA0, data[0]);
5098 nw64(ZCP_RAM_DATA1, data[1]);
5099 nw64(ZCP_RAM_DATA2, data[2]);
5100 nw64(ZCP_RAM_DATA3, data[3]);
5101 nw64(ZCP_RAM_DATA4, data[4]);
5102 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5104 (ZCP_RAM_ACC_WRITE |
5105 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5106 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5108 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5112 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5116 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5119 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5120 (unsigned long long)nr64(ZCP_RAM_ACC));
5126 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5127 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5129 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5132 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5133 (unsigned long long)nr64(ZCP_RAM_ACC));
5137 data[0] = nr64(ZCP_RAM_DATA0);
5138 data[1] = nr64(ZCP_RAM_DATA1);
5139 data[2] = nr64(ZCP_RAM_DATA2);
5140 data[3] = nr64(ZCP_RAM_DATA3);
5141 data[4] = nr64(ZCP_RAM_DATA4);
5146 static void niu_zcp_cfifo_reset(struct niu *np)
5148 u64 val = nr64(RESET_CFIFO);
5150 val |= RESET_CFIFO_RST(np->port);
5151 nw64(RESET_CFIFO, val);
5154 val &= ~RESET_CFIFO_RST(np->port);
5155 nw64(RESET_CFIFO, val);
5158 static int niu_init_zcp(struct niu *np)
5160 u64 data[5], rbuf[5];
5163 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5164 if (np->port == 0 || np->port == 1)
5165 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5167 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5169 max = NIU_CFIFO_ENTRIES;
5177 for (i = 0; i < max; i++) {
5178 err = niu_zcp_write(np, i, data);
5181 err = niu_zcp_read(np, i, rbuf);
5186 niu_zcp_cfifo_reset(np);
5187 nw64(CFIFO_ECC(np->port), 0);
5188 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5189 (void) nr64(ZCP_INT_STAT);
5190 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5195 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5197 u64 val = nr64_ipp(IPP_CFIG);
5199 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5200 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5201 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5202 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5203 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5204 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5205 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5206 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5209 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5211 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5212 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5213 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5214 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5215 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5216 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5219 static int niu_ipp_reset(struct niu *np)
5221 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5222 1000, 100, "IPP_CFIG");
5225 static int niu_init_ipp(struct niu *np)
5227 u64 data[5], rbuf[5], val;
5230 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5231 if (np->port == 0 || np->port == 1)
5232 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5234 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5236 max = NIU_DFIFO_ENTRIES;
5244 for (i = 0; i < max; i++) {
5245 niu_ipp_write(np, i, data);
5246 niu_ipp_read(np, i, rbuf);
5249 (void) nr64_ipp(IPP_INT_STAT);
5250 (void) nr64_ipp(IPP_INT_STAT);
5252 err = niu_ipp_reset(np);
5256 (void) nr64_ipp(IPP_PKT_DIS);
5257 (void) nr64_ipp(IPP_BAD_CS_CNT);
5258 (void) nr64_ipp(IPP_ECC);
5260 (void) nr64_ipp(IPP_INT_STAT);
5262 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5264 val = nr64_ipp(IPP_CFIG);
5265 val &= ~IPP_CFIG_IP_MAX_PKT;
5266 val |= (IPP_CFIG_IPP_ENABLE |
5267 IPP_CFIG_DFIFO_ECC_EN |
5268 IPP_CFIG_DROP_BAD_CRC |
5270 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5271 nw64_ipp(IPP_CFIG, val);
5276 static void niu_handle_led(struct niu *np, int status)
5279 val = nr64_mac(XMAC_CONFIG);
5281 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5282 (np->flags & NIU_FLAGS_FIBER) != 0) {
5284 val |= XMAC_CONFIG_LED_POLARITY;
5285 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5287 val |= XMAC_CONFIG_FORCE_LED_ON;
5288 val &= ~XMAC_CONFIG_LED_POLARITY;
5292 nw64_mac(XMAC_CONFIG, val);
5295 static void niu_init_xif_xmac(struct niu *np)
5297 struct niu_link_config *lp = &np->link_config;
5300 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5301 val = nr64(MIF_CONFIG);
5302 val |= MIF_CONFIG_ATCA_GE;
5303 nw64(MIF_CONFIG, val);
5306 val = nr64_mac(XMAC_CONFIG);
5307 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5309 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5311 if (lp->loopback_mode == LOOPBACK_MAC) {
5312 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5313 val |= XMAC_CONFIG_LOOPBACK;
5315 val &= ~XMAC_CONFIG_LOOPBACK;
5318 if (np->flags & NIU_FLAGS_10G) {
5319 val &= ~XMAC_CONFIG_LFS_DISABLE;
5321 val |= XMAC_CONFIG_LFS_DISABLE;
5322 if (!(np->flags & NIU_FLAGS_FIBER) &&
5323 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5324 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5326 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5329 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5331 if (lp->active_speed == SPEED_100)
5332 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5334 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5336 nw64_mac(XMAC_CONFIG, val);
5338 val = nr64_mac(XMAC_CONFIG);
5339 val &= ~XMAC_CONFIG_MODE_MASK;
5340 if (np->flags & NIU_FLAGS_10G) {
5341 val |= XMAC_CONFIG_MODE_XGMII;
5343 if (lp->active_speed == SPEED_1000)
5344 val |= XMAC_CONFIG_MODE_GMII;
5346 val |= XMAC_CONFIG_MODE_MII;
5349 nw64_mac(XMAC_CONFIG, val);
5352 static void niu_init_xif_bmac(struct niu *np)
5354 struct niu_link_config *lp = &np->link_config;
5357 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5359 if (lp->loopback_mode == LOOPBACK_MAC)
5360 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5362 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5364 if (lp->active_speed == SPEED_1000)
5365 val |= BMAC_XIF_CONFIG_GMII_MODE;
5367 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5369 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5370 BMAC_XIF_CONFIG_LED_POLARITY);
5372 if (!(np->flags & NIU_FLAGS_10G) &&
5373 !(np->flags & NIU_FLAGS_FIBER) &&
5374 lp->active_speed == SPEED_100)
5375 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5377 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5379 nw64_mac(BMAC_XIF_CONFIG, val);
5382 static void niu_init_xif(struct niu *np)
5384 if (np->flags & NIU_FLAGS_XMAC)
5385 niu_init_xif_xmac(np);
5387 niu_init_xif_bmac(np);
5390 static void niu_pcs_mii_reset(struct niu *np)
5393 u64 val = nr64_pcs(PCS_MII_CTL);
5394 val |= PCS_MII_CTL_RST;
5395 nw64_pcs(PCS_MII_CTL, val);
5396 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5398 val = nr64_pcs(PCS_MII_CTL);
5402 static void niu_xpcs_reset(struct niu *np)
5405 u64 val = nr64_xpcs(XPCS_CONTROL1);
5406 val |= XPCS_CONTROL1_RESET;
5407 nw64_xpcs(XPCS_CONTROL1, val);
5408 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5410 val = nr64_xpcs(XPCS_CONTROL1);
5414 static int niu_init_pcs(struct niu *np)
5416 struct niu_link_config *lp = &np->link_config;
5419 switch (np->flags & (NIU_FLAGS_10G |
5421 NIU_FLAGS_XCVR_SERDES)) {
5422 case NIU_FLAGS_FIBER:
5424 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5425 nw64_pcs(PCS_DPATH_MODE, 0);
5426 niu_pcs_mii_reset(np);
5430 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5431 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5433 if (!(np->flags & NIU_FLAGS_XMAC))
5436 /* 10G copper or fiber */
5437 val = nr64_mac(XMAC_CONFIG);
5438 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5439 nw64_mac(XMAC_CONFIG, val);
5443 val = nr64_xpcs(XPCS_CONTROL1);
5444 if (lp->loopback_mode == LOOPBACK_PHY)
5445 val |= XPCS_CONTROL1_LOOPBACK;
5447 val &= ~XPCS_CONTROL1_LOOPBACK;
5448 nw64_xpcs(XPCS_CONTROL1, val);
5450 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5451 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5452 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5456 case NIU_FLAGS_XCVR_SERDES:
5458 niu_pcs_mii_reset(np);
5459 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5460 nw64_pcs(PCS_DPATH_MODE, 0);
5465 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5466 /* 1G RGMII FIBER */
5467 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5468 niu_pcs_mii_reset(np);
5478 static int niu_reset_tx_xmac(struct niu *np)
5480 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5481 (XTXMAC_SW_RST_REG_RS |
5482 XTXMAC_SW_RST_SOFT_RST),
5483 1000, 100, "XTXMAC_SW_RST");
5486 static int niu_reset_tx_bmac(struct niu *np)
5490 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5492 while (--limit >= 0) {
5493 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5498 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5500 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5507 static int niu_reset_tx_mac(struct niu *np)
5509 if (np->flags & NIU_FLAGS_XMAC)
5510 return niu_reset_tx_xmac(np);
5512 return niu_reset_tx_bmac(np);
5515 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5519 val = nr64_mac(XMAC_MIN);
5520 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5521 XMAC_MIN_RX_MIN_PKT_SIZE);
5522 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5523 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5524 nw64_mac(XMAC_MIN, val);
5526 nw64_mac(XMAC_MAX, max);
5528 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5530 val = nr64_mac(XMAC_IPG);
5531 if (np->flags & NIU_FLAGS_10G) {
5532 val &= ~XMAC_IPG_IPG_XGMII;
5533 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5535 val &= ~XMAC_IPG_IPG_MII_GMII;
5536 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5538 nw64_mac(XMAC_IPG, val);
5540 val = nr64_mac(XMAC_CONFIG);
5541 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5542 XMAC_CONFIG_STRETCH_MODE |
5543 XMAC_CONFIG_VAR_MIN_IPG_EN |
5544 XMAC_CONFIG_TX_ENABLE);
5545 nw64_mac(XMAC_CONFIG, val);
5547 nw64_mac(TXMAC_FRM_CNT, 0);
5548 nw64_mac(TXMAC_BYTE_CNT, 0);
5551 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5555 nw64_mac(BMAC_MIN_FRAME, min);
5556 nw64_mac(BMAC_MAX_FRAME, max);
5558 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5559 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5560 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5562 val = nr64_mac(BTXMAC_CONFIG);
5563 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5564 BTXMAC_CONFIG_ENABLE);
5565 nw64_mac(BTXMAC_CONFIG, val);
5568 static void niu_init_tx_mac(struct niu *np)
5573 if (np->dev->mtu > ETH_DATA_LEN)
5578 /* The XMAC_MIN register only accepts values for TX min which
5579 * have the low 3 bits cleared.
5583 if (np->flags & NIU_FLAGS_XMAC)
5584 niu_init_tx_xmac(np, min, max);
5586 niu_init_tx_bmac(np, min, max);
5589 static int niu_reset_rx_xmac(struct niu *np)
5593 nw64_mac(XRXMAC_SW_RST,
5594 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5596 while (--limit >= 0) {
5597 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5598 XRXMAC_SW_RST_SOFT_RST)))
5603 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5605 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5612 static int niu_reset_rx_bmac(struct niu *np)
5616 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5618 while (--limit >= 0) {
5619 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5624 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5626 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5633 static int niu_reset_rx_mac(struct niu *np)
5635 if (np->flags & NIU_FLAGS_XMAC)
5636 return niu_reset_rx_xmac(np);
5638 return niu_reset_rx_bmac(np);
5641 static void niu_init_rx_xmac(struct niu *np)
5643 struct niu_parent *parent = np->parent;
5644 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5645 int first_rdc_table = tp->first_table_num;
5649 nw64_mac(XMAC_ADD_FILT0, 0);
5650 nw64_mac(XMAC_ADD_FILT1, 0);
5651 nw64_mac(XMAC_ADD_FILT2, 0);
5652 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5653 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5654 for (i = 0; i < MAC_NUM_HASH; i++)
5655 nw64_mac(XMAC_HASH_TBL(i), 0);
5656 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5657 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5658 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5660 val = nr64_mac(XMAC_CONFIG);
5661 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5662 XMAC_CONFIG_PROMISCUOUS |
5663 XMAC_CONFIG_PROMISC_GROUP |
5664 XMAC_CONFIG_ERR_CHK_DIS |
5665 XMAC_CONFIG_RX_CRC_CHK_DIS |
5666 XMAC_CONFIG_RESERVED_MULTICAST |
5667 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5668 XMAC_CONFIG_ADDR_FILTER_EN |
5669 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5670 XMAC_CONFIG_STRIP_CRC |
5671 XMAC_CONFIG_PASS_FLOW_CTRL |
5672 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5673 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5674 nw64_mac(XMAC_CONFIG, val);
5676 nw64_mac(RXMAC_BT_CNT, 0);
5677 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5678 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5679 nw64_mac(RXMAC_FRAG_CNT, 0);
5680 nw64_mac(RXMAC_HIST_CNT1, 0);
5681 nw64_mac(RXMAC_HIST_CNT2, 0);
5682 nw64_mac(RXMAC_HIST_CNT3, 0);
5683 nw64_mac(RXMAC_HIST_CNT4, 0);
5684 nw64_mac(RXMAC_HIST_CNT5, 0);
5685 nw64_mac(RXMAC_HIST_CNT6, 0);
5686 nw64_mac(RXMAC_HIST_CNT7, 0);
5687 nw64_mac(RXMAC_MPSZER_CNT, 0);
5688 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5689 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5690 nw64_mac(LINK_FAULT_CNT, 0);
5693 static void niu_init_rx_bmac(struct niu *np)
5695 struct niu_parent *parent = np->parent;
5696 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5697 int first_rdc_table = tp->first_table_num;
5701 nw64_mac(BMAC_ADD_FILT0, 0);
5702 nw64_mac(BMAC_ADD_FILT1, 0);
5703 nw64_mac(BMAC_ADD_FILT2, 0);
5704 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5705 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5706 for (i = 0; i < MAC_NUM_HASH; i++)
5707 nw64_mac(BMAC_HASH_TBL(i), 0);
5708 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5709 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5710 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5712 val = nr64_mac(BRXMAC_CONFIG);
5713 val &= ~(BRXMAC_CONFIG_ENABLE |
5714 BRXMAC_CONFIG_STRIP_PAD |
5715 BRXMAC_CONFIG_STRIP_FCS |
5716 BRXMAC_CONFIG_PROMISC |
5717 BRXMAC_CONFIG_PROMISC_GRP |
5718 BRXMAC_CONFIG_ADDR_FILT_EN |
5719 BRXMAC_CONFIG_DISCARD_DIS);
5720 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5721 nw64_mac(BRXMAC_CONFIG, val);
5723 val = nr64_mac(BMAC_ADDR_CMPEN);
5724 val |= BMAC_ADDR_CMPEN_EN0;
5725 nw64_mac(BMAC_ADDR_CMPEN, val);
5728 static void niu_init_rx_mac(struct niu *np)
5730 niu_set_primary_mac(np, np->dev->dev_addr);
5732 if (np->flags & NIU_FLAGS_XMAC)
5733 niu_init_rx_xmac(np);
5735 niu_init_rx_bmac(np);
5738 static void niu_enable_tx_xmac(struct niu *np, int on)
5740 u64 val = nr64_mac(XMAC_CONFIG);
5743 val |= XMAC_CONFIG_TX_ENABLE;
5745 val &= ~XMAC_CONFIG_TX_ENABLE;
5746 nw64_mac(XMAC_CONFIG, val);
5749 static void niu_enable_tx_bmac(struct niu *np, int on)
5751 u64 val = nr64_mac(BTXMAC_CONFIG);
5754 val |= BTXMAC_CONFIG_ENABLE;
5756 val &= ~BTXMAC_CONFIG_ENABLE;
5757 nw64_mac(BTXMAC_CONFIG, val);
5760 static void niu_enable_tx_mac(struct niu *np, int on)
5762 if (np->flags & NIU_FLAGS_XMAC)
5763 niu_enable_tx_xmac(np, on);
5765 niu_enable_tx_bmac(np, on);
5768 static void niu_enable_rx_xmac(struct niu *np, int on)
5770 u64 val = nr64_mac(XMAC_CONFIG);
5772 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5773 XMAC_CONFIG_PROMISCUOUS);
5775 if (np->flags & NIU_FLAGS_MCAST)
5776 val |= XMAC_CONFIG_HASH_FILTER_EN;
5777 if (np->flags & NIU_FLAGS_PROMISC)
5778 val |= XMAC_CONFIG_PROMISCUOUS;
5781 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5783 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5784 nw64_mac(XMAC_CONFIG, val);
5787 static void niu_enable_rx_bmac(struct niu *np, int on)
5789 u64 val = nr64_mac(BRXMAC_CONFIG);
5791 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5792 BRXMAC_CONFIG_PROMISC);
5794 if (np->flags & NIU_FLAGS_MCAST)
5795 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5796 if (np->flags & NIU_FLAGS_PROMISC)
5797 val |= BRXMAC_CONFIG_PROMISC;
5800 val |= BRXMAC_CONFIG_ENABLE;
5802 val &= ~BRXMAC_CONFIG_ENABLE;
5803 nw64_mac(BRXMAC_CONFIG, val);
5806 static void niu_enable_rx_mac(struct niu *np, int on)
5808 if (np->flags & NIU_FLAGS_XMAC)
5809 niu_enable_rx_xmac(np, on);
5811 niu_enable_rx_bmac(np, on);
5814 static int niu_init_mac(struct niu *np)
5819 err = niu_init_pcs(np);
5823 err = niu_reset_tx_mac(np);
5826 niu_init_tx_mac(np);
5827 err = niu_reset_rx_mac(np);
5830 niu_init_rx_mac(np);
5832 /* This looks hookey but the RX MAC reset we just did will
5833 * undo some of the state we setup in niu_init_tx_mac() so we
5834 * have to call it again. In particular, the RX MAC reset will
5835 * set the XMAC_MAX register back to it's default value.
5837 niu_init_tx_mac(np);
5838 niu_enable_tx_mac(np, 1);
5840 niu_enable_rx_mac(np, 1);
5845 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5847 (void) niu_tx_channel_stop(np, rp->tx_channel);
5850 static void niu_stop_tx_channels(struct niu *np)
5854 for (i = 0; i < np->num_tx_rings; i++) {
5855 struct tx_ring_info *rp = &np->tx_rings[i];
5857 niu_stop_one_tx_channel(np, rp);
5861 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5863 (void) niu_tx_channel_reset(np, rp->tx_channel);
5866 static void niu_reset_tx_channels(struct niu *np)
5870 for (i = 0; i < np->num_tx_rings; i++) {
5871 struct tx_ring_info *rp = &np->tx_rings[i];
5873 niu_reset_one_tx_channel(np, rp);
5877 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5879 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5882 static void niu_stop_rx_channels(struct niu *np)
5886 for (i = 0; i < np->num_rx_rings; i++) {
5887 struct rx_ring_info *rp = &np->rx_rings[i];
5889 niu_stop_one_rx_channel(np, rp);
5893 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5895 int channel = rp->rx_channel;
5897 (void) niu_rx_channel_reset(np, channel);
5898 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5899 nw64(RX_DMA_CTL_STAT(channel), 0);
5900 (void) niu_enable_rx_channel(np, channel, 0);
5903 static void niu_reset_rx_channels(struct niu *np)
5907 for (i = 0; i < np->num_rx_rings; i++) {
5908 struct rx_ring_info *rp = &np->rx_rings[i];
5910 niu_reset_one_rx_channel(np, rp);
5914 static void niu_disable_ipp(struct niu *np)
5919 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5920 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5922 while (--limit >= 0 && (rd != wr)) {
5923 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5924 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5927 (rd != 0 && wr != 1)) {
5928 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5929 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5930 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5933 val = nr64_ipp(IPP_CFIG);
5934 val &= ~(IPP_CFIG_IPP_ENABLE |
5935 IPP_CFIG_DFIFO_ECC_EN |
5936 IPP_CFIG_DROP_BAD_CRC |
5938 nw64_ipp(IPP_CFIG, val);
5940 (void) niu_ipp_reset(np);
5943 static int niu_init_hw(struct niu *np)
5947 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5948 niu_txc_enable_port(np, 1);
5949 niu_txc_port_dma_enable(np, 1);
5950 niu_txc_set_imask(np, 0);
5952 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5953 for (i = 0; i < np->num_tx_rings; i++) {
5954 struct tx_ring_info *rp = &np->tx_rings[i];
5956 err = niu_init_one_tx_channel(np, rp);
5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5962 err = niu_init_rx_channels(np);
5964 goto out_uninit_tx_channels;
5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5967 err = niu_init_classifier_hw(np);
5969 goto out_uninit_rx_channels;
5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5972 err = niu_init_zcp(np);
5974 goto out_uninit_rx_channels;
5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5977 err = niu_init_ipp(np);
5979 goto out_uninit_rx_channels;
5981 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5982 err = niu_init_mac(np);
5984 goto out_uninit_ipp;
5989 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5990 niu_disable_ipp(np);
5992 out_uninit_rx_channels:
5993 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5994 niu_stop_rx_channels(np);
5995 niu_reset_rx_channels(np);
5997 out_uninit_tx_channels:
5998 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5999 niu_stop_tx_channels(np);
6000 niu_reset_tx_channels(np);
6005 static void niu_stop_hw(struct niu *np)
6007 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6008 niu_enable_interrupts(np, 0);
6010 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6011 niu_enable_rx_mac(np, 0);
6013 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6014 niu_disable_ipp(np);
6016 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6017 niu_stop_tx_channels(np);
6019 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6020 niu_stop_rx_channels(np);
6022 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6023 niu_reset_tx_channels(np);
6025 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6026 niu_reset_rx_channels(np);
6029 static void niu_set_irq_name(struct niu *np)
6031 int port = np->port;
6034 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6037 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6038 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6042 for (i = 0; i < np->num_ldg - j; i++) {
6043 if (i < np->num_rx_rings)
6044 sprintf(np->irq_name[i+j], "%s-rx-%d",
6046 else if (i < np->num_tx_rings + np->num_rx_rings)
6047 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6048 i - np->num_rx_rings);
6052 static int niu_request_irq(struct niu *np)
6056 niu_set_irq_name(np);
6059 for (i = 0; i < np->num_ldg; i++) {
6060 struct niu_ldg *lp = &np->ldg[i];
6062 err = request_irq(lp->irq, niu_interrupt,
6063 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6064 np->irq_name[i], lp);
6073 for (j = 0; j < i; j++) {
6074 struct niu_ldg *lp = &np->ldg[j];
6076 free_irq(lp->irq, lp);
6081 static void niu_free_irq(struct niu *np)
6085 for (i = 0; i < np->num_ldg; i++) {
6086 struct niu_ldg *lp = &np->ldg[i];
6088 free_irq(lp->irq, lp);
6092 static void niu_enable_napi(struct niu *np)
6096 for (i = 0; i < np->num_ldg; i++)
6097 napi_enable(&np->ldg[i].napi);
6100 static void niu_disable_napi(struct niu *np)
6104 for (i = 0; i < np->num_ldg; i++)
6105 napi_disable(&np->ldg[i].napi);
6108 static int niu_open(struct net_device *dev)
6110 struct niu *np = netdev_priv(dev);
6113 netif_carrier_off(dev);
6115 err = niu_alloc_channels(np);
6119 err = niu_enable_interrupts(np, 0);
6121 goto out_free_channels;
6123 err = niu_request_irq(np);
6125 goto out_free_channels;
6127 niu_enable_napi(np);
6129 spin_lock_irq(&np->lock);
6131 err = niu_init_hw(np);
6133 init_timer(&np->timer);
6134 np->timer.expires = jiffies + HZ;
6135 np->timer.data = (unsigned long) np;
6136 np->timer.function = niu_timer;
6138 err = niu_enable_interrupts(np, 1);
6143 spin_unlock_irq(&np->lock);
6146 niu_disable_napi(np);
6150 netif_tx_start_all_queues(dev);
6152 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6153 netif_carrier_on(dev);
6155 add_timer(&np->timer);
6163 niu_free_channels(np);
6169 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6171 cancel_work_sync(&np->reset_task);
6173 niu_disable_napi(np);
6174 netif_tx_stop_all_queues(dev);
6176 del_timer_sync(&np->timer);
6178 spin_lock_irq(&np->lock);
6182 spin_unlock_irq(&np->lock);
6185 static int niu_close(struct net_device *dev)
6187 struct niu *np = netdev_priv(dev);
6189 niu_full_shutdown(np, dev);
6193 niu_free_channels(np);
6195 niu_handle_led(np, 0);
6200 static void niu_sync_xmac_stats(struct niu *np)
6202 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6204 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6205 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6207 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6208 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6209 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6210 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6211 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6212 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6213 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6214 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6215 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6216 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6217 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6218 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6219 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6220 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6221 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6222 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6225 static void niu_sync_bmac_stats(struct niu *np)
6227 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6229 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6230 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6232 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6233 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6234 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6235 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6238 static void niu_sync_mac_stats(struct niu *np)
6240 if (np->flags & NIU_FLAGS_XMAC)
6241 niu_sync_xmac_stats(np);
6243 niu_sync_bmac_stats(np);
6246 static void niu_get_rx_stats(struct niu *np)
6248 unsigned long pkts, dropped, errors, bytes;
6251 pkts = dropped = errors = bytes = 0;
6252 for (i = 0; i < np->num_rx_rings; i++) {
6253 struct rx_ring_info *rp = &np->rx_rings[i];
6255 niu_sync_rx_discard_stats(np, rp, 0);
6257 pkts += rp->rx_packets;
6258 bytes += rp->rx_bytes;
6259 dropped += rp->rx_dropped;
6260 errors += rp->rx_errors;
6262 np->dev->stats.rx_packets = pkts;
6263 np->dev->stats.rx_bytes = bytes;
6264 np->dev->stats.rx_dropped = dropped;
6265 np->dev->stats.rx_errors = errors;
6268 static void niu_get_tx_stats(struct niu *np)
6270 unsigned long pkts, errors, bytes;
6273 pkts = errors = bytes = 0;
6274 for (i = 0; i < np->num_tx_rings; i++) {
6275 struct tx_ring_info *rp = &np->tx_rings[i];
6277 pkts += rp->tx_packets;
6278 bytes += rp->tx_bytes;
6279 errors += rp->tx_errors;
6281 np->dev->stats.tx_packets = pkts;
6282 np->dev->stats.tx_bytes = bytes;
6283 np->dev->stats.tx_errors = errors;
6286 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6288 struct niu *np = netdev_priv(dev);
6290 niu_get_rx_stats(np);
6291 niu_get_tx_stats(np);
6296 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6300 for (i = 0; i < 16; i++)
6301 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6304 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6308 for (i = 0; i < 16; i++)
6309 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6312 static void niu_load_hash(struct niu *np, u16 *hash)
6314 if (np->flags & NIU_FLAGS_XMAC)
6315 niu_load_hash_xmac(np, hash);
6317 niu_load_hash_bmac(np, hash);
6320 static void niu_set_rx_mode(struct net_device *dev)
6322 struct niu *np = netdev_priv(dev);
6323 int i, alt_cnt, err;
6324 struct netdev_hw_addr *ha;
6325 unsigned long flags;
6326 u16 hash[16] = { 0, };
6328 spin_lock_irqsave(&np->lock, flags);
6329 niu_enable_rx_mac(np, 0);
6331 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6332 if (dev->flags & IFF_PROMISC)
6333 np->flags |= NIU_FLAGS_PROMISC;
6334 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6335 np->flags |= NIU_FLAGS_MCAST;
6337 alt_cnt = netdev_uc_count(dev);
6338 if (alt_cnt > niu_num_alt_addr(np)) {
6340 np->flags |= NIU_FLAGS_PROMISC;
6346 netdev_for_each_uc_addr(ha, dev) {
6347 err = niu_set_alt_mac(np, index, ha->addr);
6349 netdev_warn(dev, "Error %d adding alt mac %d\n",
6351 err = niu_enable_alt_mac(np, index, 1);
6353 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6360 if (np->flags & NIU_FLAGS_XMAC)
6364 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6365 err = niu_enable_alt_mac(np, i, 0);
6367 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6371 if (dev->flags & IFF_ALLMULTI) {
6372 for (i = 0; i < 16; i++)
6374 } else if (!netdev_mc_empty(dev)) {
6375 netdev_for_each_mc_addr(ha, dev) {
6376 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6379 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6383 if (np->flags & NIU_FLAGS_MCAST)
6384 niu_load_hash(np, hash);
6386 niu_enable_rx_mac(np, 1);
6387 spin_unlock_irqrestore(&np->lock, flags);
6390 static int niu_set_mac_addr(struct net_device *dev, void *p)
6392 struct niu *np = netdev_priv(dev);
6393 struct sockaddr *addr = p;
6394 unsigned long flags;
6396 if (!is_valid_ether_addr(addr->sa_data))
6399 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6401 if (!netif_running(dev))
6404 spin_lock_irqsave(&np->lock, flags);
6405 niu_enable_rx_mac(np, 0);
6406 niu_set_primary_mac(np, dev->dev_addr);
6407 niu_enable_rx_mac(np, 1);
6408 spin_unlock_irqrestore(&np->lock, flags);
6413 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6418 static void niu_netif_stop(struct niu *np)
6420 np->dev->trans_start = jiffies; /* prevent tx timeout */
6422 niu_disable_napi(np);
6424 netif_tx_disable(np->dev);
6427 static void niu_netif_start(struct niu *np)
6429 /* NOTE: unconditional netif_wake_queue is only appropriate
6430 * so long as all callers are assured to have free tx slots
6431 * (such as after niu_init_hw).
6433 netif_tx_wake_all_queues(np->dev);
6435 niu_enable_napi(np);
6437 niu_enable_interrupts(np, 1);
6440 static void niu_reset_buffers(struct niu *np)
6445 for (i = 0; i < np->num_rx_rings; i++) {
6446 struct rx_ring_info *rp = &np->rx_rings[i];
6448 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6451 page = rp->rxhash[j];
6454 (struct page *) page->mapping;
6455 u64 base = page->index;
6456 base = base >> RBR_DESCR_ADDR_SHIFT;
6457 rp->rbr[k++] = cpu_to_le32(base);
6461 for (; k < MAX_RBR_RING_SIZE; k++) {
6462 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6467 rp->rbr_index = rp->rbr_table_size - 1;
6469 rp->rbr_pending = 0;
6470 rp->rbr_refill_pending = 0;
6474 for (i = 0; i < np->num_tx_rings; i++) {
6475 struct tx_ring_info *rp = &np->tx_rings[i];
6477 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6478 if (rp->tx_buffs[j].skb)
6479 (void) release_tx_packet(np, rp, j);
6482 rp->pending = MAX_TX_RING_SIZE;
6490 static void niu_reset_task(struct work_struct *work)
6492 struct niu *np = container_of(work, struct niu, reset_task);
6493 unsigned long flags;
6496 spin_lock_irqsave(&np->lock, flags);
6497 if (!netif_running(np->dev)) {
6498 spin_unlock_irqrestore(&np->lock, flags);
6502 spin_unlock_irqrestore(&np->lock, flags);
6504 del_timer_sync(&np->timer);
6508 spin_lock_irqsave(&np->lock, flags);
6512 spin_unlock_irqrestore(&np->lock, flags);
6514 niu_reset_buffers(np);
6516 spin_lock_irqsave(&np->lock, flags);
6518 err = niu_init_hw(np);
6520 np->timer.expires = jiffies + HZ;
6521 add_timer(&np->timer);
6522 niu_netif_start(np);
6525 spin_unlock_irqrestore(&np->lock, flags);
6528 static void niu_tx_timeout(struct net_device *dev)
6530 struct niu *np = netdev_priv(dev);
6532 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6535 schedule_work(&np->reset_task);
6538 static void niu_set_txd(struct tx_ring_info *rp, int index,
6539 u64 mapping, u64 len, u64 mark,
6542 __le64 *desc = &rp->descr[index];
6544 *desc = cpu_to_le64(mark |
6545 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6546 (len << TX_DESC_TR_LEN_SHIFT) |
6547 (mapping & TX_DESC_SAD));
6550 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6551 u64 pad_bytes, u64 len)
6553 u16 eth_proto, eth_proto_inner;
6554 u64 csum_bits, l3off, ihl, ret;
6558 eth_proto = be16_to_cpu(ehdr->h_proto);
6559 eth_proto_inner = eth_proto;
6560 if (eth_proto == ETH_P_8021Q) {
6561 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6562 __be16 val = vp->h_vlan_encapsulated_proto;
6564 eth_proto_inner = be16_to_cpu(val);
6568 switch (skb->protocol) {
6569 case cpu_to_be16(ETH_P_IP):
6570 ip_proto = ip_hdr(skb)->protocol;
6571 ihl = ip_hdr(skb)->ihl;
6573 case cpu_to_be16(ETH_P_IPV6):
6574 ip_proto = ipv6_hdr(skb)->nexthdr;
6583 csum_bits = TXHDR_CSUM_NONE;
6584 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6587 csum_bits = (ip_proto == IPPROTO_TCP ?
6589 (ip_proto == IPPROTO_UDP ?
6590 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6592 start = skb_transport_offset(skb) -
6593 (pad_bytes + sizeof(struct tx_pkt_hdr));
6594 stuff = start + skb->csum_offset;
6596 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6597 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6600 l3off = skb_network_offset(skb) -
6601 (pad_bytes + sizeof(struct tx_pkt_hdr));
6603 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6604 (len << TXHDR_LEN_SHIFT) |
6605 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6606 (ihl << TXHDR_IHL_SHIFT) |
6607 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6608 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6609 (ipv6 ? TXHDR_IP_VER : 0) |
6615 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6616 struct net_device *dev)
6618 struct niu *np = netdev_priv(dev);
6619 unsigned long align, headroom;
6620 struct netdev_queue *txq;
6621 struct tx_ring_info *rp;
6622 struct tx_pkt_hdr *tp;
6623 unsigned int len, nfg;
6624 struct ethhdr *ehdr;
6628 i = skb_get_queue_mapping(skb);
6629 rp = &np->tx_rings[i];
6630 txq = netdev_get_tx_queue(dev, i);
6632 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6633 netif_tx_stop_queue(txq);
6634 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6636 return NETDEV_TX_BUSY;
6639 if (skb->len < ETH_ZLEN) {
6640 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6642 if (skb_pad(skb, pad_bytes))
6644 skb_put(skb, pad_bytes);
6647 len = sizeof(struct tx_pkt_hdr) + 15;
6648 if (skb_headroom(skb) < len) {
6649 struct sk_buff *skb_new;
6651 skb_new = skb_realloc_headroom(skb, len);
6661 align = ((unsigned long) skb->data & (16 - 1));
6662 headroom = align + sizeof(struct tx_pkt_hdr);
6664 ehdr = (struct ethhdr *) skb->data;
6665 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6667 len = skb->len - sizeof(struct tx_pkt_hdr);
6668 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6671 len = skb_headlen(skb);
6672 mapping = np->ops->map_single(np->device, skb->data,
6673 len, DMA_TO_DEVICE);
6677 rp->tx_buffs[prod].skb = skb;
6678 rp->tx_buffs[prod].mapping = mapping;
6681 if (++rp->mark_counter == rp->mark_freq) {
6682 rp->mark_counter = 0;
6683 mrk |= TX_DESC_MARK;
6688 nfg = skb_shinfo(skb)->nr_frags;
6690 tlen -= MAX_TX_DESC_LEN;
6695 unsigned int this_len = len;
6697 if (this_len > MAX_TX_DESC_LEN)
6698 this_len = MAX_TX_DESC_LEN;
6700 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6703 prod = NEXT_TX(rp, prod);
6704 mapping += this_len;
6708 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6709 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6712 mapping = np->ops->map_page(np->device, frag->page,
6713 frag->page_offset, len,
6716 rp->tx_buffs[prod].skb = NULL;
6717 rp->tx_buffs[prod].mapping = mapping;
6719 niu_set_txd(rp, prod, mapping, len, 0, 0);
6721 prod = NEXT_TX(rp, prod);
6724 if (prod < rp->prod)
6725 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6728 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6730 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6731 netif_tx_stop_queue(txq);
6732 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6733 netif_tx_wake_queue(txq);
6737 return NETDEV_TX_OK;
6745 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6747 struct niu *np = netdev_priv(dev);
6748 int err, orig_jumbo, new_jumbo;
6750 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6753 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6754 new_jumbo = (new_mtu > ETH_DATA_LEN);
6758 if (!netif_running(dev) ||
6759 (orig_jumbo == new_jumbo))
6762 niu_full_shutdown(np, dev);
6764 niu_free_channels(np);
6766 niu_enable_napi(np);
6768 err = niu_alloc_channels(np);
6772 spin_lock_irq(&np->lock);
6774 err = niu_init_hw(np);
6776 init_timer(&np->timer);
6777 np->timer.expires = jiffies + HZ;
6778 np->timer.data = (unsigned long) np;
6779 np->timer.function = niu_timer;
6781 err = niu_enable_interrupts(np, 1);
6786 spin_unlock_irq(&np->lock);
6789 netif_tx_start_all_queues(dev);
6790 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6791 netif_carrier_on(dev);
6793 add_timer(&np->timer);
6799 static void niu_get_drvinfo(struct net_device *dev,
6800 struct ethtool_drvinfo *info)
6802 struct niu *np = netdev_priv(dev);
6803 struct niu_vpd *vpd = &np->vpd;
6805 strcpy(info->driver, DRV_MODULE_NAME);
6806 strcpy(info->version, DRV_MODULE_VERSION);
6807 sprintf(info->fw_version, "%d.%d",
6808 vpd->fcode_major, vpd->fcode_minor);
6809 if (np->parent->plat_type != PLAT_TYPE_NIU)
6810 strcpy(info->bus_info, pci_name(np->pdev));
6813 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6815 struct niu *np = netdev_priv(dev);
6816 struct niu_link_config *lp;
6818 lp = &np->link_config;
6820 memset(cmd, 0, sizeof(*cmd));
6821 cmd->phy_address = np->phy_addr;
6822 cmd->supported = lp->supported;
6823 cmd->advertising = lp->active_advertising;
6824 cmd->autoneg = lp->active_autoneg;
6825 cmd->speed = lp->active_speed;
6826 cmd->duplex = lp->active_duplex;
6827 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6828 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6829 XCVR_EXTERNAL : XCVR_INTERNAL;
6834 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6836 struct niu *np = netdev_priv(dev);
6837 struct niu_link_config *lp = &np->link_config;
6839 lp->advertising = cmd->advertising;
6840 lp->speed = cmd->speed;
6841 lp->duplex = cmd->duplex;
6842 lp->autoneg = cmd->autoneg;
6843 return niu_init_link(np);
6846 static u32 niu_get_msglevel(struct net_device *dev)
6848 struct niu *np = netdev_priv(dev);
6849 return np->msg_enable;
6852 static void niu_set_msglevel(struct net_device *dev, u32 value)
6854 struct niu *np = netdev_priv(dev);
6855 np->msg_enable = value;
6858 static int niu_nway_reset(struct net_device *dev)
6860 struct niu *np = netdev_priv(dev);
6862 if (np->link_config.autoneg)
6863 return niu_init_link(np);
6868 static int niu_get_eeprom_len(struct net_device *dev)
6870 struct niu *np = netdev_priv(dev);
6872 return np->eeprom_len;
6875 static int niu_get_eeprom(struct net_device *dev,
6876 struct ethtool_eeprom *eeprom, u8 *data)
6878 struct niu *np = netdev_priv(dev);
6879 u32 offset, len, val;
6881 offset = eeprom->offset;
6884 if (offset + len < offset)
6886 if (offset >= np->eeprom_len)
6888 if (offset + len > np->eeprom_len)
6889 len = eeprom->len = np->eeprom_len - offset;
6892 u32 b_offset, b_count;
6894 b_offset = offset & 3;
6895 b_count = 4 - b_offset;
6899 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6900 memcpy(data, ((char *)&val) + b_offset, b_count);
6906 val = nr64(ESPC_NCR(offset / 4));
6907 memcpy(data, &val, 4);
6913 val = nr64(ESPC_NCR(offset / 4));
6914 memcpy(data, &val, len);
6919 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6921 switch (flow_type) {
6932 *pid = IPPROTO_SCTP;
6948 static int niu_class_to_ethflow(u64 class, int *flow_type)
6951 case CLASS_CODE_TCP_IPV4:
6952 *flow_type = TCP_V4_FLOW;
6954 case CLASS_CODE_UDP_IPV4:
6955 *flow_type = UDP_V4_FLOW;
6957 case CLASS_CODE_AH_ESP_IPV4:
6958 *flow_type = AH_V4_FLOW;
6960 case CLASS_CODE_SCTP_IPV4:
6961 *flow_type = SCTP_V4_FLOW;
6963 case CLASS_CODE_TCP_IPV6:
6964 *flow_type = TCP_V6_FLOW;
6966 case CLASS_CODE_UDP_IPV6:
6967 *flow_type = UDP_V6_FLOW;
6969 case CLASS_CODE_AH_ESP_IPV6:
6970 *flow_type = AH_V6_FLOW;
6972 case CLASS_CODE_SCTP_IPV6:
6973 *flow_type = SCTP_V6_FLOW;
6975 case CLASS_CODE_USER_PROG1:
6976 case CLASS_CODE_USER_PROG2:
6977 case CLASS_CODE_USER_PROG3:
6978 case CLASS_CODE_USER_PROG4:
6979 *flow_type = IP_USER_FLOW;
6988 static int niu_ethflow_to_class(int flow_type, u64 *class)
6990 switch (flow_type) {
6992 *class = CLASS_CODE_TCP_IPV4;
6995 *class = CLASS_CODE_UDP_IPV4;
6999 *class = CLASS_CODE_AH_ESP_IPV4;
7002 *class = CLASS_CODE_SCTP_IPV4;
7005 *class = CLASS_CODE_TCP_IPV6;
7008 *class = CLASS_CODE_UDP_IPV6;
7012 *class = CLASS_CODE_AH_ESP_IPV6;
7015 *class = CLASS_CODE_SCTP_IPV6;
7024 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7028 if (flow_key & FLOW_KEY_L2DA)
7029 ethflow |= RXH_L2DA;
7030 if (flow_key & FLOW_KEY_VLAN)
7031 ethflow |= RXH_VLAN;
7032 if (flow_key & FLOW_KEY_IPSA)
7033 ethflow |= RXH_IP_SRC;
7034 if (flow_key & FLOW_KEY_IPDA)
7035 ethflow |= RXH_IP_DST;
7036 if (flow_key & FLOW_KEY_PROTO)
7037 ethflow |= RXH_L3_PROTO;
7038 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7039 ethflow |= RXH_L4_B_0_1;
7040 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7041 ethflow |= RXH_L4_B_2_3;
7047 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7051 if (ethflow & RXH_L2DA)
7052 key |= FLOW_KEY_L2DA;
7053 if (ethflow & RXH_VLAN)
7054 key |= FLOW_KEY_VLAN;
7055 if (ethflow & RXH_IP_SRC)
7056 key |= FLOW_KEY_IPSA;
7057 if (ethflow & RXH_IP_DST)
7058 key |= FLOW_KEY_IPDA;
7059 if (ethflow & RXH_L3_PROTO)
7060 key |= FLOW_KEY_PROTO;
7061 if (ethflow & RXH_L4_B_0_1)
7062 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7063 if (ethflow & RXH_L4_B_2_3)
7064 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7072 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7078 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7081 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7083 nfc->data = RXH_DISCARD;
7085 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7086 CLASS_CODE_USER_PROG1]);
7090 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7091 struct ethtool_rx_flow_spec *fsp)
7094 fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7095 TCAM_V4KEY3_SADDR_SHIFT;
7096 fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7097 TCAM_V4KEY3_DADDR_SHIFT;
7098 fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7099 TCAM_V4KEY3_SADDR_SHIFT;
7100 fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7101 TCAM_V4KEY3_DADDR_SHIFT;
7103 fsp->h_u.tcp_ip4_spec.ip4src =
7104 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7105 fsp->m_u.tcp_ip4_spec.ip4src =
7106 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7107 fsp->h_u.tcp_ip4_spec.ip4dst =
7108 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7109 fsp->m_u.tcp_ip4_spec.ip4dst =
7110 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7112 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7113 TCAM_V4KEY2_TOS_SHIFT;
7114 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7115 TCAM_V4KEY2_TOS_SHIFT;
7117 switch (fsp->flow_type) {
7121 fsp->h_u.tcp_ip4_spec.psrc =
7122 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7123 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7124 fsp->h_u.tcp_ip4_spec.pdst =
7125 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7126 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7127 fsp->m_u.tcp_ip4_spec.psrc =
7128 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7129 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7130 fsp->m_u.tcp_ip4_spec.pdst =
7131 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7132 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7134 fsp->h_u.tcp_ip4_spec.psrc =
7135 cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7136 fsp->h_u.tcp_ip4_spec.pdst =
7137 cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7138 fsp->m_u.tcp_ip4_spec.psrc =
7139 cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7140 fsp->m_u.tcp_ip4_spec.pdst =
7141 cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7145 fsp->h_u.ah_ip4_spec.spi =
7146 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7147 TCAM_V4KEY2_PORT_SPI_SHIFT;
7148 fsp->m_u.ah_ip4_spec.spi =
7149 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7150 TCAM_V4KEY2_PORT_SPI_SHIFT;
7152 fsp->h_u.ah_ip4_spec.spi =
7153 cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7154 fsp->m_u.ah_ip4_spec.spi =
7155 cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7158 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7159 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7160 TCAM_V4KEY2_PORT_SPI_SHIFT;
7161 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7162 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7163 TCAM_V4KEY2_PORT_SPI_SHIFT;
7165 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7166 cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7167 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7168 cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7170 fsp->h_u.usr_ip4_spec.proto =
7171 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7172 TCAM_V4KEY2_PROTO_SHIFT;
7173 fsp->m_u.usr_ip4_spec.proto =
7174 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7175 TCAM_V4KEY2_PROTO_SHIFT;
7177 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7184 static int niu_get_ethtool_tcam_entry(struct niu *np,
7185 struct ethtool_rxnfc *nfc)
7187 struct niu_parent *parent = np->parent;
7188 struct niu_tcam_entry *tp;
7189 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7194 idx = tcam_get_index(np, (u16)nfc->fs.location);
7196 tp = &parent->tcam[idx];
7198 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7199 parent->index, (u16)nfc->fs.location, idx);
7203 /* fill the flow spec entry */
7204 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7205 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7206 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7209 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7215 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7216 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7217 TCAM_V4KEY2_PROTO_SHIFT;
7218 if (proto == IPPROTO_ESP) {
7219 if (fsp->flow_type == AH_V4_FLOW)
7220 fsp->flow_type = ESP_V4_FLOW;
7222 fsp->flow_type = ESP_V6_FLOW;
7226 switch (fsp->flow_type) {
7232 niu_get_ip4fs_from_tcam_key(tp, fsp);
7239 /* Not yet implemented */
7243 niu_get_ip4fs_from_tcam_key(tp, fsp);
7253 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7254 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7256 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7257 TCAM_ASSOCDATA_OFFSET_SHIFT;
7259 /* put the tcam size here */
7260 nfc->data = tcam_get_size(np);
7265 static int niu_get_ethtool_tcam_all(struct niu *np,
7266 struct ethtool_rxnfc *nfc,
7269 struct niu_parent *parent = np->parent;
7270 struct niu_tcam_entry *tp;
7272 unsigned long flags;
7275 /* put the tcam size here */
7276 nfc->data = tcam_get_size(np);
7278 niu_lock_parent(np, flags);
7279 for (cnt = 0, i = 0; i < nfc->data; i++) {
7280 idx = tcam_get_index(np, i);
7281 tp = &parent->tcam[idx];
7284 if (cnt == nfc->rule_cnt) {
7291 niu_unlock_parent(np, flags);
7296 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7299 struct niu *np = netdev_priv(dev);
7304 ret = niu_get_hash_opts(np, cmd);
7306 case ETHTOOL_GRXRINGS:
7307 cmd->data = np->num_rx_rings;
7309 case ETHTOOL_GRXCLSRLCNT:
7310 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7312 case ETHTOOL_GRXCLSRULE:
7313 ret = niu_get_ethtool_tcam_entry(np, cmd);
7315 case ETHTOOL_GRXCLSRLALL:
7316 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7326 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7330 unsigned long flags;
7332 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7335 if (class < CLASS_CODE_USER_PROG1 ||
7336 class > CLASS_CODE_SCTP_IPV6)
7339 if (nfc->data & RXH_DISCARD) {
7340 niu_lock_parent(np, flags);
7341 flow_key = np->parent->tcam_key[class -
7342 CLASS_CODE_USER_PROG1];
7343 flow_key |= TCAM_KEY_DISC;
7344 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7345 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7346 niu_unlock_parent(np, flags);
7349 /* Discard was set before, but is not set now */
7350 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7352 niu_lock_parent(np, flags);
7353 flow_key = np->parent->tcam_key[class -
7354 CLASS_CODE_USER_PROG1];
7355 flow_key &= ~TCAM_KEY_DISC;
7356 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7358 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7360 niu_unlock_parent(np, flags);
7364 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7367 niu_lock_parent(np, flags);
7368 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7369 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7370 niu_unlock_parent(np, flags);
7375 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7376 struct niu_tcam_entry *tp,
7377 int l2_rdc_tab, u64 class)
7380 u32 sip, dip, sipm, dipm, spi, spim;
7381 u16 sport, dport, spm, dpm;
7383 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7384 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7385 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7386 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7388 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7389 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7390 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7391 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7393 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7396 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7397 tp->key_mask[3] |= dipm;
7399 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7400 TCAM_V4KEY2_TOS_SHIFT);
7401 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7402 TCAM_V4KEY2_TOS_SHIFT);
7403 switch (fsp->flow_type) {
7407 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7408 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7409 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7410 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7412 tp->key[2] |= (((u64)sport << 16) | dport);
7413 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7414 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7418 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7419 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7422 tp->key_mask[2] |= spim;
7423 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7426 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7427 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7430 tp->key_mask[2] |= spim;
7431 pid = fsp->h_u.usr_ip4_spec.proto;
7437 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7439 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7443 static int niu_add_ethtool_tcam_entry(struct niu *np,
7444 struct ethtool_rxnfc *nfc)
7446 struct niu_parent *parent = np->parent;
7447 struct niu_tcam_entry *tp;
7448 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7449 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7450 int l2_rdc_table = rdc_table->first_table_num;
7453 unsigned long flags;
7458 idx = nfc->fs.location;
7459 if (idx >= tcam_get_size(np))
7462 if (fsp->flow_type == IP_USER_FLOW) {
7464 int add_usr_cls = 0;
7466 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7467 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7469 niu_lock_parent(np, flags);
7471 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7472 if (parent->l3_cls[i]) {
7473 if (uspec->proto == parent->l3_cls_pid[i]) {
7474 class = parent->l3_cls[i];
7475 parent->l3_cls_refcnt[i]++;
7480 /* Program new user IP class */
7483 class = CLASS_CODE_USER_PROG1;
7486 class = CLASS_CODE_USER_PROG2;
7489 class = CLASS_CODE_USER_PROG3;
7492 class = CLASS_CODE_USER_PROG4;
7497 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7499 ret = tcam_user_ip_class_set(np, class, ipv6,
7506 ret = tcam_user_ip_class_enable(np, class, 1);
7509 parent->l3_cls[i] = class;
7510 parent->l3_cls_pid[i] = uspec->proto;
7511 parent->l3_cls_refcnt[i]++;
7517 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7518 parent->index, __func__, uspec->proto);
7522 niu_unlock_parent(np, flags);
7524 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7529 niu_lock_parent(np, flags);
7531 idx = tcam_get_index(np, idx);
7532 tp = &parent->tcam[idx];
7534 memset(tp, 0, sizeof(*tp));
7536 /* fill in the tcam key and mask */
7537 switch (fsp->flow_type) {
7543 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7550 /* Not yet implemented */
7551 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7552 parent->index, __func__, fsp->flow_type);
7556 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7557 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7560 /* Not yet implemented */
7561 netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7562 parent->index, __func__);
7568 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7569 parent->index, __func__, fsp->flow_type);
7574 /* fill in the assoc data */
7575 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7576 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7578 if (fsp->ring_cookie >= np->num_rx_rings) {
7579 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7580 parent->index, __func__,
7581 (long long)fsp->ring_cookie);
7585 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7586 (fsp->ring_cookie <<
7587 TCAM_ASSOCDATA_OFFSET_SHIFT));
7590 err = tcam_write(np, idx, tp->key, tp->key_mask);
7595 err = tcam_assoc_write(np, idx, tp->assoc_data);
7601 /* validate the entry */
7603 np->clas.tcam_valid_entries++;
7605 niu_unlock_parent(np, flags);
7610 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7612 struct niu_parent *parent = np->parent;
7613 struct niu_tcam_entry *tp;
7615 unsigned long flags;
7619 if (loc >= tcam_get_size(np))
7622 niu_lock_parent(np, flags);
7624 idx = tcam_get_index(np, loc);
7625 tp = &parent->tcam[idx];
7627 /* if the entry is of a user defined class, then update*/
7628 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7629 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7631 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7633 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7634 if (parent->l3_cls[i] == class) {
7635 parent->l3_cls_refcnt[i]--;
7636 if (!parent->l3_cls_refcnt[i]) {
7638 ret = tcam_user_ip_class_enable(np,
7643 parent->l3_cls[i] = 0;
7644 parent->l3_cls_pid[i] = 0;
7649 if (i == NIU_L3_PROG_CLS) {
7650 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7651 parent->index, __func__,
7652 (unsigned long long)class);
7658 ret = tcam_flush(np, idx);
7662 /* invalidate the entry */
7664 np->clas.tcam_valid_entries--;
7666 niu_unlock_parent(np, flags);
7671 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7673 struct niu *np = netdev_priv(dev);
7678 ret = niu_set_hash_opts(np, cmd);
7680 case ETHTOOL_SRXCLSRLINS:
7681 ret = niu_add_ethtool_tcam_entry(np, cmd);
7683 case ETHTOOL_SRXCLSRLDEL:
7684 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7694 static const struct {
7695 const char string[ETH_GSTRING_LEN];
7696 } niu_xmac_stat_keys[] = {
7699 { "tx_fifo_errors" },
7700 { "tx_overflow_errors" },
7701 { "tx_max_pkt_size_errors" },
7702 { "tx_underflow_errors" },
7703 { "rx_local_faults" },
7704 { "rx_remote_faults" },
7705 { "rx_link_faults" },
7706 { "rx_align_errors" },
7718 { "rx_code_violations" },
7719 { "rx_len_errors" },
7720 { "rx_crc_errors" },
7721 { "rx_underflows" },
7723 { "pause_off_state" },
7724 { "pause_on_state" },
7725 { "pause_received" },
7728 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7730 static const struct {
7731 const char string[ETH_GSTRING_LEN];
7732 } niu_bmac_stat_keys[] = {
7733 { "tx_underflow_errors" },
7734 { "tx_max_pkt_size_errors" },
7739 { "rx_align_errors" },
7740 { "rx_crc_errors" },
7741 { "rx_len_errors" },
7742 { "pause_off_state" },
7743 { "pause_on_state" },
7744 { "pause_received" },
7747 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7749 static const struct {
7750 const char string[ETH_GSTRING_LEN];
7751 } niu_rxchan_stat_keys[] = {
7759 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7761 static const struct {
7762 const char string[ETH_GSTRING_LEN];
7763 } niu_txchan_stat_keys[] = {
7770 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7772 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7774 struct niu *np = netdev_priv(dev);
7777 if (stringset != ETH_SS_STATS)
7780 if (np->flags & NIU_FLAGS_XMAC) {
7781 memcpy(data, niu_xmac_stat_keys,
7782 sizeof(niu_xmac_stat_keys));
7783 data += sizeof(niu_xmac_stat_keys);
7785 memcpy(data, niu_bmac_stat_keys,
7786 sizeof(niu_bmac_stat_keys));
7787 data += sizeof(niu_bmac_stat_keys);
7789 for (i = 0; i < np->num_rx_rings; i++) {
7790 memcpy(data, niu_rxchan_stat_keys,
7791 sizeof(niu_rxchan_stat_keys));
7792 data += sizeof(niu_rxchan_stat_keys);
7794 for (i = 0; i < np->num_tx_rings; i++) {
7795 memcpy(data, niu_txchan_stat_keys,
7796 sizeof(niu_txchan_stat_keys));
7797 data += sizeof(niu_txchan_stat_keys);
7801 static int niu_get_sset_count(struct net_device *dev, int stringset)
7803 struct niu *np = netdev_priv(dev);
7805 if (stringset != ETH_SS_STATS)
7808 return ((np->flags & NIU_FLAGS_XMAC ?
7809 NUM_XMAC_STAT_KEYS :
7810 NUM_BMAC_STAT_KEYS) +
7811 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7812 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7815 static void niu_get_ethtool_stats(struct net_device *dev,
7816 struct ethtool_stats *stats, u64 *data)
7818 struct niu *np = netdev_priv(dev);
7821 niu_sync_mac_stats(np);
7822 if (np->flags & NIU_FLAGS_XMAC) {
7823 memcpy(data, &np->mac_stats.xmac,
7824 sizeof(struct niu_xmac_stats));
7825 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7827 memcpy(data, &np->mac_stats.bmac,
7828 sizeof(struct niu_bmac_stats));
7829 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7831 for (i = 0; i < np->num_rx_rings; i++) {
7832 struct rx_ring_info *rp = &np->rx_rings[i];
7834 niu_sync_rx_discard_stats(np, rp, 0);
7836 data[0] = rp->rx_channel;
7837 data[1] = rp->rx_packets;
7838 data[2] = rp->rx_bytes;
7839 data[3] = rp->rx_dropped;
7840 data[4] = rp->rx_errors;
7843 for (i = 0; i < np->num_tx_rings; i++) {
7844 struct tx_ring_info *rp = &np->tx_rings[i];
7846 data[0] = rp->tx_channel;
7847 data[1] = rp->tx_packets;
7848 data[2] = rp->tx_bytes;
7849 data[3] = rp->tx_errors;
7854 static u64 niu_led_state_save(struct niu *np)
7856 if (np->flags & NIU_FLAGS_XMAC)
7857 return nr64_mac(XMAC_CONFIG);
7859 return nr64_mac(BMAC_XIF_CONFIG);
7862 static void niu_led_state_restore(struct niu *np, u64 val)
7864 if (np->flags & NIU_FLAGS_XMAC)
7865 nw64_mac(XMAC_CONFIG, val);
7867 nw64_mac(BMAC_XIF_CONFIG, val);
7870 static void niu_force_led(struct niu *np, int on)
7874 if (np->flags & NIU_FLAGS_XMAC) {
7876 bit = XMAC_CONFIG_FORCE_LED_ON;
7878 reg = BMAC_XIF_CONFIG;
7879 bit = BMAC_XIF_CONFIG_LINK_LED;
7882 val = nr64_mac(reg);
7890 static int niu_phys_id(struct net_device *dev, u32 data)
7892 struct niu *np = netdev_priv(dev);
7896 if (!netif_running(dev))
7902 orig_led_state = niu_led_state_save(np);
7903 for (i = 0; i < (data * 2); i++) {
7904 int on = ((i % 2) == 0);
7906 niu_force_led(np, on);
7908 if (msleep_interruptible(500))
7911 niu_led_state_restore(np, orig_led_state);
7916 static int niu_set_flags(struct net_device *dev, u32 data)
7918 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
7921 static const struct ethtool_ops niu_ethtool_ops = {
7922 .get_drvinfo = niu_get_drvinfo,
7923 .get_link = ethtool_op_get_link,
7924 .get_msglevel = niu_get_msglevel,
7925 .set_msglevel = niu_set_msglevel,
7926 .nway_reset = niu_nway_reset,
7927 .get_eeprom_len = niu_get_eeprom_len,
7928 .get_eeprom = niu_get_eeprom,
7929 .get_settings = niu_get_settings,
7930 .set_settings = niu_set_settings,
7931 .get_strings = niu_get_strings,
7932 .get_sset_count = niu_get_sset_count,
7933 .get_ethtool_stats = niu_get_ethtool_stats,
7934 .phys_id = niu_phys_id,
7935 .get_rxnfc = niu_get_nfc,
7936 .set_rxnfc = niu_set_nfc,
7937 .set_flags = niu_set_flags,
7938 .get_flags = ethtool_op_get_flags,
7941 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7944 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7946 if (ldn < 0 || ldn > LDN_MAX)
7949 parent->ldg_map[ldn] = ldg;
7951 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7952 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7953 * the firmware, and we're not supposed to change them.
7954 * Validate the mapping, because if it's wrong we probably
7955 * won't get any interrupts and that's painful to debug.
7957 if (nr64(LDG_NUM(ldn)) != ldg) {
7958 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7960 (unsigned long long) nr64(LDG_NUM(ldn)));
7964 nw64(LDG_NUM(ldn), ldg);
7969 static int niu_set_ldg_timer_res(struct niu *np, int res)
7971 if (res < 0 || res > LDG_TIMER_RES_VAL)
7975 nw64(LDG_TIMER_RES, res);
7980 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7982 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7983 (func < 0 || func > 3) ||
7984 (vector < 0 || vector > 0x1f))
7987 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7992 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7994 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7995 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7998 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
8002 nw64(ESPC_PIO_STAT, frame);
8006 frame = nr64(ESPC_PIO_STAT);
8007 if (frame & ESPC_PIO_STAT_READ_END)
8010 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8011 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8012 (unsigned long long) frame);
8017 nw64(ESPC_PIO_STAT, frame);
8021 frame = nr64(ESPC_PIO_STAT);
8022 if (frame & ESPC_PIO_STAT_READ_END)
8025 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8026 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8027 (unsigned long long) frame);
8031 frame = nr64(ESPC_PIO_STAT);
8032 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8035 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8037 int err = niu_pci_eeprom_read(np, off);
8043 err = niu_pci_eeprom_read(np, off + 1);
8046 val |= (err & 0xff);
8051 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8053 int err = niu_pci_eeprom_read(np, off);
8060 err = niu_pci_eeprom_read(np, off + 1);
8064 val |= (err & 0xff) << 8;
8069 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8076 for (i = 0; i < namebuf_len; i++) {
8077 int err = niu_pci_eeprom_read(np, off + i);
8084 if (i >= namebuf_len)
8090 static void __devinit niu_vpd_parse_version(struct niu *np)
8092 struct niu_vpd *vpd = &np->vpd;
8093 int len = strlen(vpd->version) + 1;
8094 const char *s = vpd->version;
8097 for (i = 0; i < len - 5; i++) {
8098 if (!strncmp(s + i, "FCode ", 6))
8105 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8107 netif_printk(np, probe, KERN_DEBUG, np->dev,
8108 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8109 vpd->fcode_major, vpd->fcode_minor);
8110 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8111 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8112 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8113 np->flags |= NIU_FLAGS_VPD_VALID;
8116 /* ESPC_PIO_EN_ENABLE must be set */
8117 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8120 unsigned int found_mask = 0;
8121 #define FOUND_MASK_MODEL 0x00000001
8122 #define FOUND_MASK_BMODEL 0x00000002
8123 #define FOUND_MASK_VERS 0x00000004
8124 #define FOUND_MASK_MAC 0x00000008
8125 #define FOUND_MASK_NMAC 0x00000010
8126 #define FOUND_MASK_PHY 0x00000020
8127 #define FOUND_MASK_ALL 0x0000003f
8129 netif_printk(np, probe, KERN_DEBUG, np->dev,
8130 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8131 while (start < end) {
8132 int len, err, instance, type, prop_len;
8137 if (found_mask == FOUND_MASK_ALL) {
8138 niu_vpd_parse_version(np);
8142 err = niu_pci_eeprom_read(np, start + 2);
8148 instance = niu_pci_eeprom_read(np, start);
8149 type = niu_pci_eeprom_read(np, start + 3);
8150 prop_len = niu_pci_eeprom_read(np, start + 4);
8151 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8157 if (!strcmp(namebuf, "model")) {
8158 prop_buf = np->vpd.model;
8159 max_len = NIU_VPD_MODEL_MAX;
8160 found_mask |= FOUND_MASK_MODEL;
8161 } else if (!strcmp(namebuf, "board-model")) {
8162 prop_buf = np->vpd.board_model;
8163 max_len = NIU_VPD_BD_MODEL_MAX;
8164 found_mask |= FOUND_MASK_BMODEL;
8165 } else if (!strcmp(namebuf, "version")) {
8166 prop_buf = np->vpd.version;
8167 max_len = NIU_VPD_VERSION_MAX;
8168 found_mask |= FOUND_MASK_VERS;
8169 } else if (!strcmp(namebuf, "local-mac-address")) {
8170 prop_buf = np->vpd.local_mac;
8172 found_mask |= FOUND_MASK_MAC;
8173 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8174 prop_buf = &np->vpd.mac_num;
8176 found_mask |= FOUND_MASK_NMAC;
8177 } else if (!strcmp(namebuf, "phy-type")) {
8178 prop_buf = np->vpd.phy_type;
8179 max_len = NIU_VPD_PHY_TYPE_MAX;
8180 found_mask |= FOUND_MASK_PHY;
8183 if (max_len && prop_len > max_len) {
8184 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8189 u32 off = start + 5 + err;
8192 netif_printk(np, probe, KERN_DEBUG, np->dev,
8193 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8195 for (i = 0; i < prop_len; i++)
8196 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8205 /* ESPC_PIO_EN_ENABLE must be set */
8206 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8211 err = niu_pci_eeprom_read16_swp(np, start + 1);
8217 while (start + offset < ESPC_EEPROM_SIZE) {
8218 u32 here = start + offset;
8221 err = niu_pci_eeprom_read(np, here);
8225 err = niu_pci_eeprom_read16_swp(np, here + 1);
8229 here = start + offset + 3;
8230 end = start + offset + err;
8234 err = niu_pci_vpd_scan_props(np, here, end);
8235 if (err < 0 || err == 1)
8240 /* ESPC_PIO_EN_ENABLE must be set */
8241 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8243 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8246 while (start < end) {
8249 /* ROM header signature? */
8250 err = niu_pci_eeprom_read16(np, start + 0);
8254 /* Apply offset to PCI data structure. */
8255 err = niu_pci_eeprom_read16(np, start + 23);
8260 /* Check for "PCIR" signature. */
8261 err = niu_pci_eeprom_read16(np, start + 0);
8264 err = niu_pci_eeprom_read16(np, start + 2);
8268 /* Check for OBP image type. */
8269 err = niu_pci_eeprom_read(np, start + 20);
8273 err = niu_pci_eeprom_read(np, ret + 2);
8277 start = ret + (err * 512);
8281 err = niu_pci_eeprom_read16_swp(np, start + 8);
8286 err = niu_pci_eeprom_read(np, ret + 0);
8296 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8297 const char *phy_prop)
8299 if (!strcmp(phy_prop, "mif")) {
8300 /* 1G copper, MII */
8301 np->flags &= ~(NIU_FLAGS_FIBER |
8303 np->mac_xcvr = MAC_XCVR_MII;
8304 } else if (!strcmp(phy_prop, "xgf")) {
8305 /* 10G fiber, XPCS */
8306 np->flags |= (NIU_FLAGS_10G |
8308 np->mac_xcvr = MAC_XCVR_XPCS;
8309 } else if (!strcmp(phy_prop, "pcs")) {
8311 np->flags &= ~NIU_FLAGS_10G;
8312 np->flags |= NIU_FLAGS_FIBER;
8313 np->mac_xcvr = MAC_XCVR_PCS;
8314 } else if (!strcmp(phy_prop, "xgc")) {
8315 /* 10G copper, XPCS */
8316 np->flags |= NIU_FLAGS_10G;
8317 np->flags &= ~NIU_FLAGS_FIBER;
8318 np->mac_xcvr = MAC_XCVR_XPCS;
8319 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8320 /* 10G Serdes or 1G Serdes, default to 10G */
8321 np->flags |= NIU_FLAGS_10G;
8322 np->flags &= ~NIU_FLAGS_FIBER;
8323 np->flags |= NIU_FLAGS_XCVR_SERDES;
8324 np->mac_xcvr = MAC_XCVR_XPCS;
8331 static int niu_pci_vpd_get_nports(struct niu *np)
8335 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8336 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8337 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8338 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8339 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8341 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8342 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8343 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8344 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8351 static void __devinit niu_pci_vpd_validate(struct niu *np)
8353 struct net_device *dev = np->dev;
8354 struct niu_vpd *vpd = &np->vpd;
8357 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8358 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8360 np->flags &= ~NIU_FLAGS_VPD_VALID;
8364 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8365 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8366 np->flags |= NIU_FLAGS_10G;
8367 np->flags &= ~NIU_FLAGS_FIBER;
8368 np->flags |= NIU_FLAGS_XCVR_SERDES;
8369 np->mac_xcvr = MAC_XCVR_PCS;
8371 np->flags |= NIU_FLAGS_FIBER;
8372 np->flags &= ~NIU_FLAGS_10G;
8374 if (np->flags & NIU_FLAGS_10G)
8375 np->mac_xcvr = MAC_XCVR_XPCS;
8376 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8377 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8378 NIU_FLAGS_HOTPLUG_PHY);
8379 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8380 dev_err(np->device, "Illegal phy string [%s]\n",
8382 dev_err(np->device, "Falling back to SPROM\n");
8383 np->flags &= ~NIU_FLAGS_VPD_VALID;
8387 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8389 val8 = dev->perm_addr[5];
8390 dev->perm_addr[5] += np->port;
8391 if (dev->perm_addr[5] < val8)
8392 dev->perm_addr[4]++;
8394 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8397 static int __devinit niu_pci_probe_sprom(struct niu *np)
8399 struct net_device *dev = np->dev;
8404 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8405 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8408 np->eeprom_len = len;
8410 netif_printk(np, probe, KERN_DEBUG, np->dev,
8411 "SPROM: Image size %llu\n", (unsigned long long)val);
8414 for (i = 0; i < len; i++) {
8415 val = nr64(ESPC_NCR(i));
8416 sum += (val >> 0) & 0xff;
8417 sum += (val >> 8) & 0xff;
8418 sum += (val >> 16) & 0xff;
8419 sum += (val >> 24) & 0xff;
8421 netif_printk(np, probe, KERN_DEBUG, np->dev,
8422 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8423 if ((sum & 0xff) != 0xab) {
8424 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8428 val = nr64(ESPC_PHY_TYPE);
8431 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8432 ESPC_PHY_TYPE_PORT0_SHIFT;
8435 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8436 ESPC_PHY_TYPE_PORT1_SHIFT;
8439 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8440 ESPC_PHY_TYPE_PORT2_SHIFT;
8443 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8444 ESPC_PHY_TYPE_PORT3_SHIFT;
8447 dev_err(np->device, "Bogus port number %u\n",
8451 netif_printk(np, probe, KERN_DEBUG, np->dev,
8452 "SPROM: PHY type %x\n", val8);
8455 case ESPC_PHY_TYPE_1G_COPPER:
8456 /* 1G copper, MII */
8457 np->flags &= ~(NIU_FLAGS_FIBER |
8459 np->mac_xcvr = MAC_XCVR_MII;
8462 case ESPC_PHY_TYPE_1G_FIBER:
8464 np->flags &= ~NIU_FLAGS_10G;
8465 np->flags |= NIU_FLAGS_FIBER;
8466 np->mac_xcvr = MAC_XCVR_PCS;
8469 case ESPC_PHY_TYPE_10G_COPPER:
8470 /* 10G copper, XPCS */
8471 np->flags |= NIU_FLAGS_10G;
8472 np->flags &= ~NIU_FLAGS_FIBER;
8473 np->mac_xcvr = MAC_XCVR_XPCS;
8476 case ESPC_PHY_TYPE_10G_FIBER:
8477 /* 10G fiber, XPCS */
8478 np->flags |= (NIU_FLAGS_10G |
8480 np->mac_xcvr = MAC_XCVR_XPCS;
8484 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8488 val = nr64(ESPC_MAC_ADDR0);
8489 netif_printk(np, probe, KERN_DEBUG, np->dev,
8490 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8491 dev->perm_addr[0] = (val >> 0) & 0xff;
8492 dev->perm_addr[1] = (val >> 8) & 0xff;
8493 dev->perm_addr[2] = (val >> 16) & 0xff;
8494 dev->perm_addr[3] = (val >> 24) & 0xff;
8496 val = nr64(ESPC_MAC_ADDR1);
8497 netif_printk(np, probe, KERN_DEBUG, np->dev,
8498 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8499 dev->perm_addr[4] = (val >> 0) & 0xff;
8500 dev->perm_addr[5] = (val >> 8) & 0xff;
8502 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8503 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8508 val8 = dev->perm_addr[5];
8509 dev->perm_addr[5] += np->port;
8510 if (dev->perm_addr[5] < val8)
8511 dev->perm_addr[4]++;
8513 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8515 val = nr64(ESPC_MOD_STR_LEN);
8516 netif_printk(np, probe, KERN_DEBUG, np->dev,
8517 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8521 for (i = 0; i < val; i += 4) {
8522 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8524 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8525 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8526 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8527 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8529 np->vpd.model[val] = '\0';
8531 val = nr64(ESPC_BD_MOD_STR_LEN);
8532 netif_printk(np, probe, KERN_DEBUG, np->dev,
8533 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8537 for (i = 0; i < val; i += 4) {
8538 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8540 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8541 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8542 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8543 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8545 np->vpd.board_model[val] = '\0';
8548 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8549 netif_printk(np, probe, KERN_DEBUG, np->dev,
8550 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8555 static int __devinit niu_get_and_validate_port(struct niu *np)
8557 struct niu_parent *parent = np->parent;
8560 np->flags |= NIU_FLAGS_XMAC;
8562 if (!parent->num_ports) {
8563 if (parent->plat_type == PLAT_TYPE_NIU) {
8564 parent->num_ports = 2;
8566 parent->num_ports = niu_pci_vpd_get_nports(np);
8567 if (!parent->num_ports) {
8568 /* Fall back to SPROM as last resort.
8569 * This will fail on most cards.
8571 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8572 ESPC_NUM_PORTS_MACS_VAL;
8574 /* All of the current probing methods fail on
8575 * Maramba on-board parts.
8577 if (!parent->num_ports)
8578 parent->num_ports = 4;
8583 if (np->port >= parent->num_ports)
8589 static int __devinit phy_record(struct niu_parent *parent,
8590 struct phy_probe_info *p,
8591 int dev_id_1, int dev_id_2, u8 phy_port,
8594 u32 id = (dev_id_1 << 16) | dev_id_2;
8597 if (dev_id_1 < 0 || dev_id_2 < 0)
8599 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8600 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8601 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8602 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8605 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8609 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8611 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8612 type == PHY_TYPE_PCS ? "PCS" : "MII",
8615 if (p->cur[type] >= NIU_MAX_PORTS) {
8616 pr_err("Too many PHY ports\n");
8620 p->phy_id[type][idx] = id;
8621 p->phy_port[type][idx] = phy_port;
8622 p->cur[type] = idx + 1;
8626 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8630 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8631 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8634 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8635 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8642 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8648 for (port = 8; port < 32; port++) {
8649 if (port_has_10g(p, port)) {
8659 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8662 if (p->cur[PHY_TYPE_MII])
8663 *lowest = p->phy_port[PHY_TYPE_MII][0];
8665 return p->cur[PHY_TYPE_MII];
8668 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8670 int num_ports = parent->num_ports;
8673 for (i = 0; i < num_ports; i++) {
8674 parent->rxchan_per_port[i] = (16 / num_ports);
8675 parent->txchan_per_port[i] = (16 / num_ports);
8677 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8679 parent->rxchan_per_port[i],
8680 parent->txchan_per_port[i]);
8684 static void __devinit niu_divide_channels(struct niu_parent *parent,
8685 int num_10g, int num_1g)
8687 int num_ports = parent->num_ports;
8688 int rx_chans_per_10g, rx_chans_per_1g;
8689 int tx_chans_per_10g, tx_chans_per_1g;
8690 int i, tot_rx, tot_tx;
8692 if (!num_10g || !num_1g) {
8693 rx_chans_per_10g = rx_chans_per_1g =
8694 (NIU_NUM_RXCHAN / num_ports);
8695 tx_chans_per_10g = tx_chans_per_1g =
8696 (NIU_NUM_TXCHAN / num_ports);
8698 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8699 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8700 (rx_chans_per_1g * num_1g)) /
8703 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8704 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8705 (tx_chans_per_1g * num_1g)) /
8709 tot_rx = tot_tx = 0;
8710 for (i = 0; i < num_ports; i++) {
8711 int type = phy_decode(parent->port_phy, i);
8713 if (type == PORT_TYPE_10G) {
8714 parent->rxchan_per_port[i] = rx_chans_per_10g;
8715 parent->txchan_per_port[i] = tx_chans_per_10g;
8717 parent->rxchan_per_port[i] = rx_chans_per_1g;
8718 parent->txchan_per_port[i] = tx_chans_per_1g;
8720 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8722 parent->rxchan_per_port[i],
8723 parent->txchan_per_port[i]);
8724 tot_rx += parent->rxchan_per_port[i];
8725 tot_tx += parent->txchan_per_port[i];
8728 if (tot_rx > NIU_NUM_RXCHAN) {
8729 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8730 parent->index, tot_rx);
8731 for (i = 0; i < num_ports; i++)
8732 parent->rxchan_per_port[i] = 1;
8734 if (tot_tx > NIU_NUM_TXCHAN) {
8735 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8736 parent->index, tot_tx);
8737 for (i = 0; i < num_ports; i++)
8738 parent->txchan_per_port[i] = 1;
8740 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8741 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8742 parent->index, tot_rx, tot_tx);
8746 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8747 int num_10g, int num_1g)
8749 int i, num_ports = parent->num_ports;
8750 int rdc_group, rdc_groups_per_port;
8751 int rdc_channel_base;
8754 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8756 rdc_channel_base = 0;
8758 for (i = 0; i < num_ports; i++) {
8759 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8760 int grp, num_channels = parent->rxchan_per_port[i];
8761 int this_channel_offset;
8763 tp->first_table_num = rdc_group;
8764 tp->num_tables = rdc_groups_per_port;
8765 this_channel_offset = 0;
8766 for (grp = 0; grp < tp->num_tables; grp++) {
8767 struct rdc_table *rt = &tp->tables[grp];
8770 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8771 parent->index, i, tp->first_table_num + grp);
8772 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8773 rt->rxdma_channel[slot] =
8774 rdc_channel_base + this_channel_offset;
8776 pr_cont("%d ", rt->rxdma_channel[slot]);
8778 if (++this_channel_offset == num_channels)
8779 this_channel_offset = 0;
8784 parent->rdc_default[i] = rdc_channel_base;
8786 rdc_channel_base += num_channels;
8787 rdc_group += rdc_groups_per_port;
8791 static int __devinit fill_phy_probe_info(struct niu *np,
8792 struct niu_parent *parent,
8793 struct phy_probe_info *info)
8795 unsigned long flags;
8798 memset(info, 0, sizeof(*info));
8800 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8801 niu_lock_parent(np, flags);
8803 for (port = 8; port < 32; port++) {
8804 int dev_id_1, dev_id_2;
8806 dev_id_1 = mdio_read(np, port,
8807 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8808 dev_id_2 = mdio_read(np, port,
8809 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8810 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8814 dev_id_1 = mdio_read(np, port,
8815 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8816 dev_id_2 = mdio_read(np, port,
8817 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8818 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8822 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8823 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8824 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8829 niu_unlock_parent(np, flags);
8834 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8836 struct phy_probe_info *info = &parent->phy_probe_info;
8837 int lowest_10g, lowest_1g;
8838 int num_10g, num_1g;
8842 num_10g = num_1g = 0;
8844 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8845 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8848 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8849 parent->num_ports = 4;
8850 val = (phy_encode(PORT_TYPE_1G, 0) |
8851 phy_encode(PORT_TYPE_1G, 1) |
8852 phy_encode(PORT_TYPE_1G, 2) |
8853 phy_encode(PORT_TYPE_1G, 3));
8854 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8857 parent->num_ports = 2;
8858 val = (phy_encode(PORT_TYPE_10G, 0) |
8859 phy_encode(PORT_TYPE_10G, 1));
8860 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8861 (parent->plat_type == PLAT_TYPE_NIU)) {
8862 /* this is the Monza case */
8863 if (np->flags & NIU_FLAGS_10G) {
8864 val = (phy_encode(PORT_TYPE_10G, 0) |
8865 phy_encode(PORT_TYPE_10G, 1));
8867 val = (phy_encode(PORT_TYPE_1G, 0) |
8868 phy_encode(PORT_TYPE_1G, 1));
8871 err = fill_phy_probe_info(np, parent, info);
8875 num_10g = count_10g_ports(info, &lowest_10g);
8876 num_1g = count_1g_ports(info, &lowest_1g);
8878 switch ((num_10g << 4) | num_1g) {
8880 if (lowest_1g == 10)
8881 parent->plat_type = PLAT_TYPE_VF_P0;
8882 else if (lowest_1g == 26)
8883 parent->plat_type = PLAT_TYPE_VF_P1;
8885 goto unknown_vg_1g_port;
8889 val = (phy_encode(PORT_TYPE_10G, 0) |
8890 phy_encode(PORT_TYPE_10G, 1) |
8891 phy_encode(PORT_TYPE_1G, 2) |
8892 phy_encode(PORT_TYPE_1G, 3));
8896 val = (phy_encode(PORT_TYPE_10G, 0) |
8897 phy_encode(PORT_TYPE_10G, 1));
8901 val = phy_encode(PORT_TYPE_10G, np->port);
8905 if (lowest_1g == 10)
8906 parent->plat_type = PLAT_TYPE_VF_P0;
8907 else if (lowest_1g == 26)
8908 parent->plat_type = PLAT_TYPE_VF_P1;
8910 goto unknown_vg_1g_port;
8914 if ((lowest_10g & 0x7) == 0)
8915 val = (phy_encode(PORT_TYPE_10G, 0) |
8916 phy_encode(PORT_TYPE_1G, 1) |
8917 phy_encode(PORT_TYPE_1G, 2) |
8918 phy_encode(PORT_TYPE_1G, 3));
8920 val = (phy_encode(PORT_TYPE_1G, 0) |
8921 phy_encode(PORT_TYPE_10G, 1) |
8922 phy_encode(PORT_TYPE_1G, 2) |
8923 phy_encode(PORT_TYPE_1G, 3));
8927 if (lowest_1g == 10)
8928 parent->plat_type = PLAT_TYPE_VF_P0;
8929 else if (lowest_1g == 26)
8930 parent->plat_type = PLAT_TYPE_VF_P1;
8932 goto unknown_vg_1g_port;
8934 val = (phy_encode(PORT_TYPE_1G, 0) |
8935 phy_encode(PORT_TYPE_1G, 1) |
8936 phy_encode(PORT_TYPE_1G, 2) |
8937 phy_encode(PORT_TYPE_1G, 3));
8941 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8947 parent->port_phy = val;
8949 if (parent->plat_type == PLAT_TYPE_NIU)
8950 niu_n2_divide_channels(parent);
8952 niu_divide_channels(parent, num_10g, num_1g);
8954 niu_divide_rdc_groups(parent, num_10g, num_1g);
8959 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8963 static int __devinit niu_probe_ports(struct niu *np)
8965 struct niu_parent *parent = np->parent;
8968 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8969 err = walk_phys(np, parent);
8973 niu_set_ldg_timer_res(np, 2);
8974 for (i = 0; i <= LDN_MAX; i++)
8975 niu_ldn_irq_enable(np, i, 0);
8978 if (parent->port_phy == PORT_PHY_INVALID)
8984 static int __devinit niu_classifier_swstate_init(struct niu *np)
8986 struct niu_classifier *cp = &np->clas;
8988 cp->tcam_top = (u16) np->port;
8989 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8990 cp->h1_init = 0xffffffff;
8991 cp->h2_init = 0xffff;
8993 return fflp_early_init(np);
8996 static void __devinit niu_link_config_init(struct niu *np)
8998 struct niu_link_config *lp = &np->link_config;
9000 lp->advertising = (ADVERTISED_10baseT_Half |
9001 ADVERTISED_10baseT_Full |
9002 ADVERTISED_100baseT_Half |
9003 ADVERTISED_100baseT_Full |
9004 ADVERTISED_1000baseT_Half |
9005 ADVERTISED_1000baseT_Full |
9006 ADVERTISED_10000baseT_Full |
9007 ADVERTISED_Autoneg);
9008 lp->speed = lp->active_speed = SPEED_INVALID;
9009 lp->duplex = DUPLEX_FULL;
9010 lp->active_duplex = DUPLEX_INVALID;
9013 lp->loopback_mode = LOOPBACK_MAC;
9014 lp->active_speed = SPEED_10000;
9015 lp->active_duplex = DUPLEX_FULL;
9017 lp->loopback_mode = LOOPBACK_DISABLED;
9021 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9025 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9026 np->ipp_off = 0x00000;
9027 np->pcs_off = 0x04000;
9028 np->xpcs_off = 0x02000;
9032 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9033 np->ipp_off = 0x08000;
9034 np->pcs_off = 0x0a000;
9035 np->xpcs_off = 0x08000;
9039 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9040 np->ipp_off = 0x04000;
9041 np->pcs_off = 0x0e000;
9042 np->xpcs_off = ~0UL;
9046 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9047 np->ipp_off = 0x0c000;
9048 np->pcs_off = 0x12000;
9049 np->xpcs_off = ~0UL;
9053 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9060 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9062 struct msix_entry msi_vec[NIU_NUM_LDG];
9063 struct niu_parent *parent = np->parent;
9064 struct pci_dev *pdev = np->pdev;
9065 int i, num_irqs, err;
9068 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9069 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9070 ldg_num_map[i] = first_ldg + i;
9072 num_irqs = (parent->rxchan_per_port[np->port] +
9073 parent->txchan_per_port[np->port] +
9074 (np->port == 0 ? 3 : 1));
9075 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9078 for (i = 0; i < num_irqs; i++) {
9079 msi_vec[i].vector = 0;
9080 msi_vec[i].entry = i;
9083 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9085 np->flags &= ~NIU_FLAGS_MSIX;
9093 np->flags |= NIU_FLAGS_MSIX;
9094 for (i = 0; i < num_irqs; i++)
9095 np->ldg[i].irq = msi_vec[i].vector;
9096 np->num_ldg = num_irqs;
9099 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9101 #ifdef CONFIG_SPARC64
9102 struct platform_device *op = np->op;
9103 const u32 *int_prop;
9106 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9110 for (i = 0; i < op->archdata.num_irqs; i++) {
9111 ldg_num_map[i] = int_prop[i];
9112 np->ldg[i].irq = op->archdata.irqs[i];
9115 np->num_ldg = op->archdata.num_irqs;
9123 static int __devinit niu_ldg_init(struct niu *np)
9125 struct niu_parent *parent = np->parent;
9126 u8 ldg_num_map[NIU_NUM_LDG];
9127 int first_chan, num_chan;
9128 int i, err, ldg_rotor;
9132 np->ldg[0].irq = np->dev->irq;
9133 if (parent->plat_type == PLAT_TYPE_NIU) {
9134 err = niu_n2_irq_init(np, ldg_num_map);
9138 niu_try_msix(np, ldg_num_map);
9141 for (i = 0; i < np->num_ldg; i++) {
9142 struct niu_ldg *lp = &np->ldg[i];
9144 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9147 lp->ldg_num = ldg_num_map[i];
9148 lp->timer = 2; /* XXX */
9150 /* On N2 NIU the firmware has setup the SID mappings so they go
9151 * to the correct values that will route the LDG to the proper
9152 * interrupt in the NCU interrupt table.
9154 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9155 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9161 /* We adopt the LDG assignment ordering used by the N2 NIU
9162 * 'interrupt' properties because that simplifies a lot of
9163 * things. This ordering is:
9166 * MIF (if port zero)
9167 * SYSERR (if port zero)
9174 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9180 if (ldg_rotor == np->num_ldg)
9184 err = niu_ldg_assign_ldn(np, parent,
9185 ldg_num_map[ldg_rotor],
9191 if (ldg_rotor == np->num_ldg)
9194 err = niu_ldg_assign_ldn(np, parent,
9195 ldg_num_map[ldg_rotor],
9201 if (ldg_rotor == np->num_ldg)
9207 for (i = 0; i < port; i++)
9208 first_chan += parent->rxchan_per_port[port];
9209 num_chan = parent->rxchan_per_port[port];
9211 for (i = first_chan; i < (first_chan + num_chan); i++) {
9212 err = niu_ldg_assign_ldn(np, parent,
9213 ldg_num_map[ldg_rotor],
9218 if (ldg_rotor == np->num_ldg)
9223 for (i = 0; i < port; i++)
9224 first_chan += parent->txchan_per_port[port];
9225 num_chan = parent->txchan_per_port[port];
9226 for (i = first_chan; i < (first_chan + num_chan); i++) {
9227 err = niu_ldg_assign_ldn(np, parent,
9228 ldg_num_map[ldg_rotor],
9233 if (ldg_rotor == np->num_ldg)
9240 static void __devexit niu_ldg_free(struct niu *np)
9242 if (np->flags & NIU_FLAGS_MSIX)
9243 pci_disable_msix(np->pdev);
9246 static int __devinit niu_get_of_props(struct niu *np)
9248 #ifdef CONFIG_SPARC64
9249 struct net_device *dev = np->dev;
9250 struct device_node *dp;
9251 const char *phy_type;
9256 if (np->parent->plat_type == PLAT_TYPE_NIU)
9257 dp = np->op->dev.of_node;
9259 dp = pci_device_to_OF_node(np->pdev);
9261 phy_type = of_get_property(dp, "phy-type", &prop_len);
9263 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9268 if (!strcmp(phy_type, "none"))
9271 strcpy(np->vpd.phy_type, phy_type);
9273 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9274 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9275 dp->full_name, np->vpd.phy_type);
9279 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9281 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9285 if (prop_len != dev->addr_len) {
9286 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9287 dp->full_name, prop_len);
9289 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9290 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9291 netdev_err(dev, "%s: OF MAC address is invalid\n",
9293 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9297 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9299 model = of_get_property(dp, "model", &prop_len);
9302 strcpy(np->vpd.model, model);
9304 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9305 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9306 NIU_FLAGS_HOTPLUG_PHY);
9315 static int __devinit niu_get_invariants(struct niu *np)
9317 int err, have_props;
9320 err = niu_get_of_props(np);
9326 err = niu_init_mac_ipp_pcs_base(np);
9331 err = niu_get_and_validate_port(np);
9336 if (np->parent->plat_type == PLAT_TYPE_NIU)
9339 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9340 offset = niu_pci_vpd_offset(np);
9341 netif_printk(np, probe, KERN_DEBUG, np->dev,
9342 "%s() VPD offset [%08x]\n", __func__, offset);
9344 niu_pci_vpd_fetch(np, offset);
9345 nw64(ESPC_PIO_EN, 0);
9347 if (np->flags & NIU_FLAGS_VPD_VALID) {
9348 niu_pci_vpd_validate(np);
9349 err = niu_get_and_validate_port(np);
9354 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9355 err = niu_get_and_validate_port(np);
9358 err = niu_pci_probe_sprom(np);
9364 err = niu_probe_ports(np);
9370 niu_classifier_swstate_init(np);
9371 niu_link_config_init(np);
9373 err = niu_determine_phy_disposition(np);
9375 err = niu_init_link(np);
9380 static LIST_HEAD(niu_parent_list);
9381 static DEFINE_MUTEX(niu_parent_lock);
9382 static int niu_parent_index;
9384 static ssize_t show_port_phy(struct device *dev,
9385 struct device_attribute *attr, char *buf)
9387 struct platform_device *plat_dev = to_platform_device(dev);
9388 struct niu_parent *p = plat_dev->dev.platform_data;
9389 u32 port_phy = p->port_phy;
9390 char *orig_buf = buf;
9393 if (port_phy == PORT_PHY_UNKNOWN ||
9394 port_phy == PORT_PHY_INVALID)
9397 for (i = 0; i < p->num_ports; i++) {
9398 const char *type_str;
9401 type = phy_decode(port_phy, i);
9402 if (type == PORT_TYPE_10G)
9407 (i == 0) ? "%s" : " %s",
9410 buf += sprintf(buf, "\n");
9411 return buf - orig_buf;
9414 static ssize_t show_plat_type(struct device *dev,
9415 struct device_attribute *attr, char *buf)
9417 struct platform_device *plat_dev = to_platform_device(dev);
9418 struct niu_parent *p = plat_dev->dev.platform_data;
9419 const char *type_str;
9421 switch (p->plat_type) {
9422 case PLAT_TYPE_ATLAS:
9428 case PLAT_TYPE_VF_P0:
9431 case PLAT_TYPE_VF_P1:
9435 type_str = "unknown";
9439 return sprintf(buf, "%s\n", type_str);
9442 static ssize_t __show_chan_per_port(struct device *dev,
9443 struct device_attribute *attr, char *buf,
9446 struct platform_device *plat_dev = to_platform_device(dev);
9447 struct niu_parent *p = plat_dev->dev.platform_data;
9448 char *orig_buf = buf;
9452 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9454 for (i = 0; i < p->num_ports; i++) {
9456 (i == 0) ? "%d" : " %d",
9459 buf += sprintf(buf, "\n");
9461 return buf - orig_buf;
9464 static ssize_t show_rxchan_per_port(struct device *dev,
9465 struct device_attribute *attr, char *buf)
9467 return __show_chan_per_port(dev, attr, buf, 1);
9470 static ssize_t show_txchan_per_port(struct device *dev,
9471 struct device_attribute *attr, char *buf)
9473 return __show_chan_per_port(dev, attr, buf, 1);
9476 static ssize_t show_num_ports(struct device *dev,
9477 struct device_attribute *attr, char *buf)
9479 struct platform_device *plat_dev = to_platform_device(dev);
9480 struct niu_parent *p = plat_dev->dev.platform_data;
9482 return sprintf(buf, "%d\n", p->num_ports);
9485 static struct device_attribute niu_parent_attributes[] = {
9486 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9487 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9488 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9489 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9490 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9494 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9495 union niu_parent_id *id,
9498 struct platform_device *plat_dev;
9499 struct niu_parent *p;
9502 plat_dev = platform_device_register_simple("niu", niu_parent_index,
9504 if (IS_ERR(plat_dev))
9507 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9508 int err = device_create_file(&plat_dev->dev,
9509 &niu_parent_attributes[i]);
9511 goto fail_unregister;
9514 p = kzalloc(sizeof(*p), GFP_KERNEL);
9516 goto fail_unregister;
9518 p->index = niu_parent_index++;
9520 plat_dev->dev.platform_data = p;
9521 p->plat_dev = plat_dev;
9523 memcpy(&p->id, id, sizeof(*id));
9524 p->plat_type = ptype;
9525 INIT_LIST_HEAD(&p->list);
9526 atomic_set(&p->refcnt, 0);
9527 list_add(&p->list, &niu_parent_list);
9528 spin_lock_init(&p->lock);
9530 p->rxdma_clock_divider = 7500;
9532 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9533 if (p->plat_type == PLAT_TYPE_NIU)
9534 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9536 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9537 int index = i - CLASS_CODE_USER_PROG1;
9539 p->tcam_key[index] = TCAM_KEY_TSEL;
9540 p->flow_key[index] = (FLOW_KEY_IPSA |
9543 (FLOW_KEY_L4_BYTE12 <<
9544 FLOW_KEY_L4_0_SHIFT) |
9545 (FLOW_KEY_L4_BYTE12 <<
9546 FLOW_KEY_L4_1_SHIFT));
9549 for (i = 0; i < LDN_MAX + 1; i++)
9550 p->ldg_map[i] = LDG_INVALID;
9555 platform_device_unregister(plat_dev);
9559 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9560 union niu_parent_id *id,
9563 struct niu_parent *p, *tmp;
9564 int port = np->port;
9566 mutex_lock(&niu_parent_lock);
9568 list_for_each_entry(tmp, &niu_parent_list, list) {
9569 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9575 p = niu_new_parent(np, id, ptype);
9581 sprintf(port_name, "port%d", port);
9582 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9586 p->ports[port] = np;
9587 atomic_inc(&p->refcnt);
9590 mutex_unlock(&niu_parent_lock);
9595 static void niu_put_parent(struct niu *np)
9597 struct niu_parent *p = np->parent;
9601 BUG_ON(!p || p->ports[port] != np);
9603 netif_printk(np, probe, KERN_DEBUG, np->dev,
9604 "%s() port[%u]\n", __func__, port);
9606 sprintf(port_name, "port%d", port);
9608 mutex_lock(&niu_parent_lock);
9610 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9612 p->ports[port] = NULL;
9615 if (atomic_dec_and_test(&p->refcnt)) {
9617 platform_device_unregister(p->plat_dev);
9620 mutex_unlock(&niu_parent_lock);
9623 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9624 u64 *handle, gfp_t flag)
9629 ret = dma_alloc_coherent(dev, size, &dh, flag);
9635 static void niu_pci_free_coherent(struct device *dev, size_t size,
9636 void *cpu_addr, u64 handle)
9638 dma_free_coherent(dev, size, cpu_addr, handle);
9641 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9642 unsigned long offset, size_t size,
9643 enum dma_data_direction direction)
9645 return dma_map_page(dev, page, offset, size, direction);
9648 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9649 size_t size, enum dma_data_direction direction)
9651 dma_unmap_page(dev, dma_address, size, direction);
9654 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9656 enum dma_data_direction direction)
9658 return dma_map_single(dev, cpu_addr, size, direction);
9661 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9663 enum dma_data_direction direction)
9665 dma_unmap_single(dev, dma_address, size, direction);
9668 static const struct niu_ops niu_pci_ops = {
9669 .alloc_coherent = niu_pci_alloc_coherent,
9670 .free_coherent = niu_pci_free_coherent,
9671 .map_page = niu_pci_map_page,
9672 .unmap_page = niu_pci_unmap_page,
9673 .map_single = niu_pci_map_single,
9674 .unmap_single = niu_pci_unmap_single,
9677 static void __devinit niu_driver_version(void)
9679 static int niu_version_printed;
9681 if (niu_version_printed++ == 0)
9682 pr_info("%s", version);
9685 static struct net_device * __devinit niu_alloc_and_init(
9686 struct device *gen_dev, struct pci_dev *pdev,
9687 struct platform_device *op, const struct niu_ops *ops,
9690 struct net_device *dev;
9693 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9695 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
9699 SET_NETDEV_DEV(dev, gen_dev);
9701 np = netdev_priv(dev);
9705 np->device = gen_dev;
9708 np->msg_enable = niu_debug;
9710 spin_lock_init(&np->lock);
9711 INIT_WORK(&np->reset_task, niu_reset_task);
9718 static const struct net_device_ops niu_netdev_ops = {
9719 .ndo_open = niu_open,
9720 .ndo_stop = niu_close,
9721 .ndo_start_xmit = niu_start_xmit,
9722 .ndo_get_stats = niu_get_stats,
9723 .ndo_set_multicast_list = niu_set_rx_mode,
9724 .ndo_validate_addr = eth_validate_addr,
9725 .ndo_set_mac_address = niu_set_mac_addr,
9726 .ndo_do_ioctl = niu_ioctl,
9727 .ndo_tx_timeout = niu_tx_timeout,
9728 .ndo_change_mtu = niu_change_mtu,
9731 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9733 dev->netdev_ops = &niu_netdev_ops;
9734 dev->ethtool_ops = &niu_ethtool_ops;
9735 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9738 static void __devinit niu_device_announce(struct niu *np)
9740 struct net_device *dev = np->dev;
9742 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9744 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9745 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9747 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9748 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9749 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9750 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9751 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9754 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9756 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9757 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9758 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9759 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9761 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9762 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9767 static void __devinit niu_set_basic_features(struct net_device *dev)
9769 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM |
9770 NETIF_F_GRO | NETIF_F_RXHASH);
9773 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9774 const struct pci_device_id *ent)
9776 union niu_parent_id parent_id;
9777 struct net_device *dev;
9783 niu_driver_version();
9785 err = pci_enable_device(pdev);
9787 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9791 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9792 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9793 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9795 goto err_out_disable_pdev;
9798 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9800 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9801 goto err_out_disable_pdev;
9804 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9806 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9807 goto err_out_free_res;
9810 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9811 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9814 goto err_out_free_res;
9816 np = netdev_priv(dev);
9818 memset(&parent_id, 0, sizeof(parent_id));
9819 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9820 parent_id.pci.bus = pdev->bus->number;
9821 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9823 np->parent = niu_get_parent(np, &parent_id,
9827 goto err_out_free_dev;
9830 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9831 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9832 val16 |= (PCI_EXP_DEVCTL_CERE |
9833 PCI_EXP_DEVCTL_NFERE |
9834 PCI_EXP_DEVCTL_FERE |
9835 PCI_EXP_DEVCTL_URRE |
9836 PCI_EXP_DEVCTL_RELAX_EN);
9837 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9839 dma_mask = DMA_BIT_MASK(44);
9840 err = pci_set_dma_mask(pdev, dma_mask);
9842 dev->features |= NETIF_F_HIGHDMA;
9843 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9845 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9846 goto err_out_release_parent;
9849 if (err || dma_mask == DMA_BIT_MASK(32)) {
9850 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9852 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9853 goto err_out_release_parent;
9857 niu_set_basic_features(dev);
9859 np->regs = pci_ioremap_bar(pdev, 0);
9861 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9863 goto err_out_release_parent;
9866 pci_set_master(pdev);
9867 pci_save_state(pdev);
9869 dev->irq = pdev->irq;
9871 niu_assign_netdev_ops(dev);
9873 err = niu_get_invariants(np);
9876 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9877 goto err_out_iounmap;
9880 err = register_netdev(dev);
9882 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9883 goto err_out_iounmap;
9886 pci_set_drvdata(pdev, dev);
9888 niu_device_announce(np);
9898 err_out_release_parent:
9905 pci_release_regions(pdev);
9907 err_out_disable_pdev:
9908 pci_disable_device(pdev);
9909 pci_set_drvdata(pdev, NULL);
9914 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9916 struct net_device *dev = pci_get_drvdata(pdev);
9919 struct niu *np = netdev_priv(dev);
9921 unregister_netdev(dev);
9932 pci_release_regions(pdev);
9933 pci_disable_device(pdev);
9934 pci_set_drvdata(pdev, NULL);
9938 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9940 struct net_device *dev = pci_get_drvdata(pdev);
9941 struct niu *np = netdev_priv(dev);
9942 unsigned long flags;
9944 if (!netif_running(dev))
9947 flush_scheduled_work();
9950 del_timer_sync(&np->timer);
9952 spin_lock_irqsave(&np->lock, flags);
9953 niu_enable_interrupts(np, 0);
9954 spin_unlock_irqrestore(&np->lock, flags);
9956 netif_device_detach(dev);
9958 spin_lock_irqsave(&np->lock, flags);
9960 spin_unlock_irqrestore(&np->lock, flags);
9962 pci_save_state(pdev);
9967 static int niu_resume(struct pci_dev *pdev)
9969 struct net_device *dev = pci_get_drvdata(pdev);
9970 struct niu *np = netdev_priv(dev);
9971 unsigned long flags;
9974 if (!netif_running(dev))
9977 pci_restore_state(pdev);
9979 netif_device_attach(dev);
9981 spin_lock_irqsave(&np->lock, flags);
9983 err = niu_init_hw(np);
9985 np->timer.expires = jiffies + HZ;
9986 add_timer(&np->timer);
9987 niu_netif_start(np);
9990 spin_unlock_irqrestore(&np->lock, flags);
9995 static struct pci_driver niu_pci_driver = {
9996 .name = DRV_MODULE_NAME,
9997 .id_table = niu_pci_tbl,
9998 .probe = niu_pci_init_one,
9999 .remove = __devexit_p(niu_pci_remove_one),
10000 .suspend = niu_suspend,
10001 .resume = niu_resume,
10004 #ifdef CONFIG_SPARC64
10005 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10006 u64 *dma_addr, gfp_t flag)
10008 unsigned long order = get_order(size);
10009 unsigned long page = __get_free_pages(flag, order);
10013 memset((char *)page, 0, PAGE_SIZE << order);
10014 *dma_addr = __pa(page);
10016 return (void *) page;
10019 static void niu_phys_free_coherent(struct device *dev, size_t size,
10020 void *cpu_addr, u64 handle)
10022 unsigned long order = get_order(size);
10024 free_pages((unsigned long) cpu_addr, order);
10027 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10028 unsigned long offset, size_t size,
10029 enum dma_data_direction direction)
10031 return page_to_phys(page) + offset;
10034 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10035 size_t size, enum dma_data_direction direction)
10037 /* Nothing to do. */
10040 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10042 enum dma_data_direction direction)
10044 return __pa(cpu_addr);
10047 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10049 enum dma_data_direction direction)
10051 /* Nothing to do. */
10054 static const struct niu_ops niu_phys_ops = {
10055 .alloc_coherent = niu_phys_alloc_coherent,
10056 .free_coherent = niu_phys_free_coherent,
10057 .map_page = niu_phys_map_page,
10058 .unmap_page = niu_phys_unmap_page,
10059 .map_single = niu_phys_map_single,
10060 .unmap_single = niu_phys_unmap_single,
10063 static int __devinit niu_of_probe(struct platform_device *op,
10064 const struct of_device_id *match)
10066 union niu_parent_id parent_id;
10067 struct net_device *dev;
10072 niu_driver_version();
10074 reg = of_get_property(op->dev.of_node, "reg", NULL);
10076 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10077 op->dev.of_node->full_name);
10081 dev = niu_alloc_and_init(&op->dev, NULL, op,
10082 &niu_phys_ops, reg[0] & 0x1);
10087 np = netdev_priv(dev);
10089 memset(&parent_id, 0, sizeof(parent_id));
10090 parent_id.of = of_get_parent(op->dev.of_node);
10092 np->parent = niu_get_parent(np, &parent_id,
10096 goto err_out_free_dev;
10099 niu_set_basic_features(dev);
10101 np->regs = of_ioremap(&op->resource[1], 0,
10102 resource_size(&op->resource[1]),
10105 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10107 goto err_out_release_parent;
10110 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10111 resource_size(&op->resource[2]),
10113 if (!np->vir_regs_1) {
10114 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10116 goto err_out_iounmap;
10119 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10120 resource_size(&op->resource[3]),
10122 if (!np->vir_regs_2) {
10123 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10125 goto err_out_iounmap;
10128 niu_assign_netdev_ops(dev);
10130 err = niu_get_invariants(np);
10132 if (err != -ENODEV)
10133 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10134 goto err_out_iounmap;
10137 err = register_netdev(dev);
10139 dev_err(&op->dev, "Cannot register net device, aborting\n");
10140 goto err_out_iounmap;
10143 dev_set_drvdata(&op->dev, dev);
10145 niu_device_announce(np);
10150 if (np->vir_regs_1) {
10151 of_iounmap(&op->resource[2], np->vir_regs_1,
10152 resource_size(&op->resource[2]));
10153 np->vir_regs_1 = NULL;
10156 if (np->vir_regs_2) {
10157 of_iounmap(&op->resource[3], np->vir_regs_2,
10158 resource_size(&op->resource[3]));
10159 np->vir_regs_2 = NULL;
10163 of_iounmap(&op->resource[1], np->regs,
10164 resource_size(&op->resource[1]));
10168 err_out_release_parent:
10169 niu_put_parent(np);
10178 static int __devexit niu_of_remove(struct platform_device *op)
10180 struct net_device *dev = dev_get_drvdata(&op->dev);
10183 struct niu *np = netdev_priv(dev);
10185 unregister_netdev(dev);
10187 if (np->vir_regs_1) {
10188 of_iounmap(&op->resource[2], np->vir_regs_1,
10189 resource_size(&op->resource[2]));
10190 np->vir_regs_1 = NULL;
10193 if (np->vir_regs_2) {
10194 of_iounmap(&op->resource[3], np->vir_regs_2,
10195 resource_size(&op->resource[3]));
10196 np->vir_regs_2 = NULL;
10200 of_iounmap(&op->resource[1], np->regs,
10201 resource_size(&op->resource[1]));
10207 niu_put_parent(np);
10210 dev_set_drvdata(&op->dev, NULL);
10215 static const struct of_device_id niu_match[] = {
10218 .compatible = "SUNW,niusl",
10222 MODULE_DEVICE_TABLE(of, niu_match);
10224 static struct of_platform_driver niu_of_driver = {
10227 .owner = THIS_MODULE,
10228 .of_match_table = niu_match,
10230 .probe = niu_of_probe,
10231 .remove = __devexit_p(niu_of_remove),
10234 #endif /* CONFIG_SPARC64 */
10236 static int __init niu_init(void)
10240 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10242 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10244 #ifdef CONFIG_SPARC64
10245 err = of_register_platform_driver(&niu_of_driver);
10249 err = pci_register_driver(&niu_pci_driver);
10250 #ifdef CONFIG_SPARC64
10252 of_unregister_platform_driver(&niu_of_driver);
10259 static void __exit niu_exit(void)
10261 pci_unregister_driver(&niu_pci_driver);
10262 #ifdef CONFIG_SPARC64
10263 of_unregister_platform_driver(&niu_of_driver);
10267 module_init(niu_init);
10268 module_exit(niu_exit);