2 * Copyright (C) 2004 IMMS gGmbH <www.imms.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * author(s): Thomas Elste, <info@elste.org>
20 * (some parts derived from uCLinux Netarm Ethernet Driver)
27 #include "netarm_eth.h"
28 #include <asm/arch/netarm_registers.h>
30 static int na_mii_poll_busy (void);
32 static void na_get_mac_addr (void)
40 p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
41 p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
42 p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
44 sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
46 m_addr[2], m_addr[3], m_addr[4], m_addr[5]);
48 printf ("HW-MAC Address: %s\n", ethaddr);
50 /* set env, todo: check if already an adress is set */
51 setenv ("ethaddr", ethaddr);
54 static void na_mii_write (int reg, int value)
59 mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
60 SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
62 SET_EADDR (NETARM_ETH_MII_WRITE, value);
66 static unsigned int na_mii_read (int reg)
71 mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
72 SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
73 /* do one management cycle */
74 SET_EADDR (NETARM_ETH_MII_CMD,
75 GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
77 /* Return read value */
78 val = GET_EADDR (NETARM_ETH_MII_READ);
82 static int na_mii_poll_busy (void)
85 /* arm simple, non interrupt dependent timer */
86 start = get_timer(0));
87 while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) {
88 if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
92 printf ("na_mii_busy timeout\n");
96 static int na_mii_identify_phy (void)
100 /* get phy id register */
101 id_reg_a = na_mii_read (MII_PHY_ID);
103 if (id_reg_a == 0x0043) {
104 /* This must be an Enable or a Lucent LU3X31 PHY chip */
106 } else if (id_reg_a == 0x0013) {
107 /* it is an Intel LXT971A */
113 static int na_mii_negotiate (void)
117 /* Enable auto-negotiation */
118 na_mii_write (MII_PHY_AUTONEGADV, 0x01e1);
119 /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */
120 /* Restart auto-negotiation */
121 na_mii_write (MII_PHY_CONTROL, 0x1200);
123 /* status register is 0xffff after setting the autoneg restart bit */
124 while (na_mii_read (MII_PHY_STATUS) == 0xffff) {
128 /* na_mii_read uses the timer already, so we can't use it again for
130 Instead we just try some times.
132 for (i = 0; i < 40000; i++) {
133 if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) {
138 printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS));
143 static unsigned int na_mii_check_speed (void)
147 /* Read Status register */
148 status = na_mii_read (MII_PHY_STATUS);
149 /* Check link status. If 0, default to 100 Mbps. */
150 if ((status & 0x0004) == 0) {
151 printf ("*Warning* no link detected, set default speed to 100Mbs\n");
154 if ((na_mii_read (17) & 0x4000) != 0) {
155 printf ("100Mbs link detected\n");
158 printf ("10Mbs link detected\n");
165 static int reset_eth (void)
171 pt = na_mii_identify_phy ();
174 na_mii_write (MII_PHY_CONTROL, 0x8000);
175 start = get_timer(0);
176 while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) {
177 if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
181 if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY)
182 printf ("phy reset timeout\n");
184 /* set the PCS reg */
185 SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
186 NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
189 na_mii_check_speed ();
191 /* Delay 10 millisecond. (Maybe this should be 1 second.) */
195 Enable statistics register autozero on read.
196 Do not insert MAC address on transmit.
197 Do not enable special test modes. */
198 SET_EADDR (NETARM_ETH_STL_CFG,
199 (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
201 /* Set the inter-packet gap delay to 0.96us for MII.
202 The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG
203 Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG
204 Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
205 SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
206 SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
208 /* Add CRC to end of packets.
209 Pad packets to minimum length of 64 bytes.
210 Allow unlimited length transmit packets.
211 Receive all broadcast packets.
212 NOTE: Multicast addressing is NOT enabled here currently. */
213 SET_EADDR (NETARM_ETH_MAC_CFG,
214 (NETARM_ETH_MACC_CRCEN |
215 NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
216 SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
219 SET_EADDR (NETARM_ETH_GEN_CTRL,
220 (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
226 extern int eth_init (bd_t * bd)
232 extern void eth_halt (void)
234 SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
237 /* Get a data block via Ethernet */
238 extern int eth_rx (void)
241 unsigned short rxlen;
243 unsigned int rxstatus, lastrxlen;
246 /* RXBR is 1, data block was received */
247 if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
250 /* get status register and the length of received block */
251 rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
252 rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
257 /* clear RXBR to make fifo available */
258 SET_EADDR (NETARM_ETH_GEN_STAT,
259 GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
261 /* clear TXBC to make fifo available */
262 /* According to NETARM50 data manual you just have to clear
263 RXBR but that has no effect. Only after clearing TXBC the
264 Fifo becomes readable. */
265 SET_EADDR (NETARM_ETH_GEN_STAT,
266 GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
268 addr = (unsigned int *) NetRxPackets[0];
269 pa = (char *) NetRxPackets[0];
272 for (i = 0; i < rxlen / 4; i++) {
273 *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
277 if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
278 /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
280 (GET_EADDR (NETARM_ETH_GEN_STAT) &
281 NETARM_ETH_GST_RXFDB) >> 28;
282 *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
296 /* Pass the packet up to the protocol layers. */
297 NetReceive (NetRxPackets[0], rxlen);
302 /* Send a data block via Ethernet. */
303 extern int eth_send (volatile void *packet, int length)
307 unsigned int *pa32, lastp = 0, rest;
309 pa = (char *) packet;
310 pa32 = (unsigned int *) packet;
311 length32 = length / 4;
314 /* make sure there's no garbage in the last word */
317 lastp = pa32[length32];
321 lastp = pa32[length32] & 0x000000ff;
324 lastp = pa32[length32] & 0x0000ffff;
327 lastp = pa32[length32] & 0x00ffffff;
331 /* write to the fifo */
332 for (i = 0; i < length32; i++)
333 SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
335 /* the last word is written to an extra register, this
336 starts the transmission */
337 SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
339 /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
340 went fine. But we can't use the timer for a timeout loop because
341 of it is used already in upper layers. So we just try some times. */
344 if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
345 == NETARM_ETH_TXSTAT_TXOK)
350 printf ("eth_send timeout\n");