2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
19 #include <dm/device-internal.h>
26 #include <linux/errno.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/soc.h>
32 #include <linux/compat.h>
33 #include <linux/mbus.h>
34 #include <asm-generic/gpio.h>
35 #include <fdt_support.h>
36 #include <linux/mdio.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 #define __verify_pcpu_ptr(ptr) \
42 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
46 #define VERIFY_PERCPU_PTR(__p) \
48 __verify_pcpu_ptr(__p); \
49 (typeof(*(__p)) __kernel __force *)(__p); \
52 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
53 #define smp_processor_id() 0
54 #define num_present_cpus() 1
55 #define for_each_present_cpu(cpu) \
56 for ((cpu) = 0; (cpu) < 1; (cpu)++)
58 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
60 #define CONFIG_NR_CPUS 1
62 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
63 #define WRAP (2 + ETH_HLEN + 4 + 32)
65 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
67 /* RX Fifo Registers */
68 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
69 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
70 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
71 #define MVPP2_RX_FIFO_INIT_REG 0x64
73 /* RX DMA Top Registers */
74 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
75 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
76 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
77 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
78 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
79 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
80 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
81 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
82 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
83 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
84 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
85 #define MVPP2_RXQ_POOL_LONG_OFFS 24
86 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
87 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
88 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
89 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
90 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
92 /* Parser Registers */
93 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
94 #define MVPP2_PRS_PORT_LU_MAX 0xf
95 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
96 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
97 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
98 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
99 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
100 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
101 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
102 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
103 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
104 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
105 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
106 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
107 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
108 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
109 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
111 /* Classifier Registers */
112 #define MVPP2_CLS_MODE_REG 0x1800
113 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
114 #define MVPP2_CLS_PORT_WAY_REG 0x1810
115 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
116 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
117 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
118 #define MVPP2_CLS_LKP_TBL_REG 0x1818
119 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
120 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
121 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
122 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
123 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
124 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
125 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
126 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
127 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
128 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
129 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
130 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
132 /* Descriptor Manager Top Registers */
133 #define MVPP2_RXQ_NUM_REG 0x2040
134 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
135 #define MVPP22_DESC_ADDR_OFFS 8
136 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
137 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
138 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
139 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
140 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
141 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
142 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
143 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
144 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
145 #define MVPP2_RXQ_THRESH_REG 0x204c
146 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
147 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
148 #define MVPP2_RXQ_INDEX_REG 0x2050
149 #define MVPP2_TXQ_NUM_REG 0x2080
150 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
151 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
152 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
153 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
154 #define MVPP2_TXQ_THRESH_REG 0x2094
155 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
156 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
157 #define MVPP2_TXQ_INDEX_REG 0x2098
158 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
159 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
160 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
161 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
162 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
163 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
164 #define MVPP2_TXQ_PENDING_REG 0x20a0
165 #define MVPP2_TXQ_PENDING_MASK 0x3fff
166 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
167 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
168 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
169 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
170 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
171 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
172 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
173 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
174 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
175 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
176 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
177 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
178 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
179 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
180 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
181 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
182 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
184 /* MBUS bridge registers */
185 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
186 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
187 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
188 #define MVPP2_BASE_ADDR_ENABLE 0x4060
190 /* AXI Bridge Registers */
191 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
192 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
193 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
194 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
195 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
196 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
197 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
198 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
199 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
200 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
201 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
202 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
204 /* Values for AXI Bridge registers */
205 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
206 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
208 #define MVPP22_AXI_CODE_CACHE_OFFS 0
209 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
211 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
212 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
213 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
215 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
216 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
218 /* Interrupt Cause and Mask registers */
219 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
220 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
222 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
223 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
224 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
225 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
227 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
228 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
230 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
231 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
232 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
233 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
235 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
236 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
237 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
238 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
239 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
240 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
241 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
242 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
243 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
244 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
245 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
246 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
247 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
248 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
249 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
250 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
251 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
252 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
254 /* Buffer Manager registers */
255 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
256 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
257 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
258 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
259 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
260 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
261 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
262 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
263 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
264 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
265 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
266 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
267 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
268 #define MVPP2_BM_START_MASK BIT(0)
269 #define MVPP2_BM_STOP_MASK BIT(1)
270 #define MVPP2_BM_STATE_MASK BIT(4)
271 #define MVPP2_BM_LOW_THRESH_OFFS 8
272 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
273 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
274 MVPP2_BM_LOW_THRESH_OFFS)
275 #define MVPP2_BM_HIGH_THRESH_OFFS 16
276 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
277 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
278 MVPP2_BM_HIGH_THRESH_OFFS)
279 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
280 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
281 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
282 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
283 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
284 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
285 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
286 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
287 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
288 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
289 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
290 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
291 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
292 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
293 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
294 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
295 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
296 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
297 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
298 #define MVPP21_BM_MC_RLS_REG 0x64c4
299 #define MVPP2_BM_MC_ID_MASK 0xfff
300 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
301 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
302 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
303 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
304 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
305 #define MVPP22_BM_MC_RLS_REG 0x64d4
306 #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
307 #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
309 /* TX Scheduler registers */
310 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
311 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
312 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
313 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
314 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
315 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
316 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
317 #define MVPP2_TXP_MTU_MAX 0x7FFFF
318 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
319 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
320 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
321 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
322 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
323 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
324 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
325 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
326 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
327 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
328 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
329 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
330 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
331 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
333 /* TX general registers */
334 #define MVPP2_TX_SNOOP_REG 0x8800
335 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
336 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
339 #define MVPP2_SRC_ADDR_MIDDLE 0x24
340 #define MVPP2_SRC_ADDR_HIGH 0x28
341 #define MVPP2_PHY_AN_CFG0_REG 0x34
342 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
343 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
344 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
346 /* Per-port registers */
347 #define MVPP2_GMAC_CTRL_0_REG 0x0
348 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
349 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
350 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
351 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
352 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
353 #define MVPP2_GMAC_CTRL_1_REG 0x4
354 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
355 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
356 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
357 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
358 #define MVPP2_GMAC_SA_LOW_OFFS 7
359 #define MVPP2_GMAC_CTRL_2_REG 0x8
360 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
361 #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
362 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
363 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
364 #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
365 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
366 #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
367 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
368 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
369 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
370 #define MVPP2_GMAC_EN_PCS_AN BIT(2)
371 #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
372 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
373 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
374 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
375 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
376 #define MVPP2_GMAC_EN_FC_AN BIT(11)
377 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
378 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
379 #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
380 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
381 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
382 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
383 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
384 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
385 #define MVPP2_GMAC_CTRL_4_REG 0x90
386 #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
387 #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
388 #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
389 #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
392 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
393 * relative to port->base.
396 /* Port Mac Control0 */
397 #define MVPP22_XLG_CTRL0_REG 0x100
398 #define MVPP22_XLG_PORT_EN BIT(0)
399 #define MVPP22_XLG_MAC_RESETN BIT(1)
400 #define MVPP22_XLG_RX_FC_EN BIT(7)
401 #define MVPP22_XLG_MIBCNT_DIS BIT(13)
402 /* Port Mac Control1 */
403 #define MVPP22_XLG_CTRL1_REG 0x104
404 #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
405 #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
406 /* Port Interrupt Mask */
407 #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
408 #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
409 /* Port Mac Control3 */
410 #define MVPP22_XLG_CTRL3_REG 0x11c
411 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
412 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
413 #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
414 /* Port Mac Control4 */
415 #define MVPP22_XLG_CTRL4_REG 0x184
416 #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
417 #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
418 #define MVPP22_XLG_MODE_DMA_1G BIT(12)
419 #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
423 /* Global Configuration 0 */
424 #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
425 #define MVPP22_XPCS_PCSRESET BIT(0)
426 #define MVPP22_XPCS_PCSMODE_OFFS 3
427 #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
428 MVPP22_XPCS_PCSMODE_OFFS)
429 #define MVPP22_XPCS_LANEACTIVE_OFFS 5
430 #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
431 MVPP22_XPCS_LANEACTIVE_OFFS)
435 #define PCS40G_COMMON_CONTROL 0x14
436 #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
438 #define PCS_CLOCK_RESET 0x14c
439 #define TX_SD_CLK_RESET_MASK BIT(0)
440 #define RX_SD_CLK_RESET_MASK BIT(1)
441 #define MAC_CLK_RESET_MASK BIT(2)
442 #define CLK_DIVISION_RATIO_OFFS 4
443 #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
444 #define CLK_DIV_PHASE_SET_MASK BIT(11)
446 /* System Soft Reset 1 */
447 #define GOP_SOFT_RESET_1_REG 0x108
448 #define NETC_GOP_SOFT_RESET_OFFS 6
449 #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
450 NETC_GOP_SOFT_RESET_OFFS)
452 /* Ports Control 0 */
453 #define NETCOMP_PORTS_CONTROL_0_REG 0x110
454 #define NETC_BUS_WIDTH_SELECT_OFFS 1
455 #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
456 NETC_BUS_WIDTH_SELECT_OFFS)
457 #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
458 #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
459 NETC_GIG_RX_DATA_SAMPLE_OFFS)
460 #define NETC_CLK_DIV_PHASE_OFFS 31
461 #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
462 /* Ports Control 1 */
463 #define NETCOMP_PORTS_CONTROL_1_REG 0x114
464 #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
465 #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
466 NETC_PORTS_ACTIVE_OFFSET(p))
467 #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
468 #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
469 NETC_PORT_GIG_RF_RESET_OFFS(p))
470 #define NETCOMP_CONTROL_0_REG 0x120
471 #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
472 #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
473 NETC_GBE_PORT0_SGMII_MODE_OFFS)
474 #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
475 #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
476 NETC_GBE_PORT1_SGMII_MODE_OFFS)
477 #define NETC_GBE_PORT1_MII_MODE_OFFS 2
478 #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
479 NETC_GBE_PORT1_MII_MODE_OFFS)
481 #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
482 #define MVPP22_SMI_POLLING_EN BIT(10)
484 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
487 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
489 /* Descriptor ring Macros */
490 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
491 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
493 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
494 #define MVPP22_SMI 0x1200
496 /* Additional PPv2.2 offsets */
497 #define MVPP22_MPCS 0x007000
498 #define MVPP22_XPCS 0x007400
499 #define MVPP22_PORT_BASE 0x007e00
500 #define MVPP22_PORT_OFFSET 0x001000
501 #define MVPP22_RFU1 0x318000
503 /* Maximum number of ports */
504 #define MVPP22_GOP_MAC_NUM 4
506 /* Sets the field located at the specified in data */
507 #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
508 #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
509 #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
512 enum mv_netc_topology {
513 MV_NETC_GE_MAC2_SGMII = BIT(0),
514 MV_NETC_GE_MAC3_SGMII = BIT(1),
515 MV_NETC_GE_MAC3_RGMII = BIT(2),
520 MV_NETC_SECOND_PHASE,
523 enum mv_netc_sgmii_xmi_mode {
528 enum mv_netc_mii_mode {
538 /* Various constants */
541 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
542 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
543 #define MVPP2_RX_COAL_PKTS 32
544 #define MVPP2_RX_COAL_USEC 100
546 /* The two bytes Marvell header. Either contains a special value used
547 * by Marvell switches when a specific hardware mode is enabled (not
548 * supported by this driver) or is filled automatically by zeroes on
549 * the RX side. Those two bytes being at the front of the Ethernet
550 * header, they allow to have the IP header aligned on a 4 bytes
551 * boundary automatically: the hardware skips those two bytes on its
554 #define MVPP2_MH_SIZE 2
555 #define MVPP2_ETH_TYPE_LEN 2
556 #define MVPP2_PPPOE_HDR_SIZE 8
557 #define MVPP2_VLAN_TAG_LEN 4
559 /* Lbtd 802.3 type */
560 #define MVPP2_IP_LBDT_TYPE 0xfffa
562 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
563 #define MVPP2_TX_CSUM_MAX_SIZE 9800
565 /* Timeout constants */
566 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
567 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
569 #define MVPP2_TX_MTU_MAX 0x7ffff
571 /* Maximum number of T-CONTs of PON port */
572 #define MVPP2_MAX_TCONT 16
574 /* Maximum number of supported ports */
575 #define MVPP2_MAX_PORTS 4
577 /* Maximum number of TXQs used by single port */
578 #define MVPP2_MAX_TXQ 8
580 /* Default number of TXQs in use */
581 #define MVPP2_DEFAULT_TXQ 1
583 /* Dfault number of RXQs in use */
584 #define MVPP2_DEFAULT_RXQ 1
585 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
587 /* Max number of Rx descriptors */
588 #define MVPP2_MAX_RXD 16
590 /* Max number of Tx descriptors */
591 #define MVPP2_MAX_TXD 16
593 /* Amount of Tx descriptors that can be reserved at once by CPU */
594 #define MVPP2_CPU_DESC_CHUNK 16
596 /* Max number of Tx descriptors in each aggregated queue */
597 #define MVPP2_AGGR_TXQ_SIZE 16
599 /* Descriptor aligned size */
600 #define MVPP2_DESC_ALIGNED_SIZE 32
602 /* Descriptor alignment mask */
603 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
605 /* RX FIFO constants */
606 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
607 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
608 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
609 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
610 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
611 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
612 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
613 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
614 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
616 /* TX general registers */
617 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
618 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
620 /* TX FIFO constants */
621 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
622 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
624 /* RX buffer constants */
625 #define MVPP2_SKB_SHINFO_SIZE \
628 #define MVPP2_RX_PKT_SIZE(mtu) \
629 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
630 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
632 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
633 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
634 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
635 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
637 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
639 /* IPv6 max L3 address size */
640 #define MVPP2_MAX_L3_ADDR_SIZE 16
643 #define MVPP2_F_LOOPBACK BIT(0)
645 /* Marvell tag types */
646 enum mvpp2_tag_type {
647 MVPP2_TAG_TYPE_NONE = 0,
648 MVPP2_TAG_TYPE_MH = 1,
649 MVPP2_TAG_TYPE_DSA = 2,
650 MVPP2_TAG_TYPE_EDSA = 3,
651 MVPP2_TAG_TYPE_VLAN = 4,
652 MVPP2_TAG_TYPE_LAST = 5
655 /* Parser constants */
656 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
657 #define MVPP2_PRS_TCAM_WORDS 6
658 #define MVPP2_PRS_SRAM_WORDS 4
659 #define MVPP2_PRS_FLOW_ID_SIZE 64
660 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
661 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
662 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
663 #define MVPP2_PRS_IPV4_HEAD 0x40
664 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
665 #define MVPP2_PRS_IPV4_MC 0xe0
666 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
667 #define MVPP2_PRS_IPV4_BC_MASK 0xff
668 #define MVPP2_PRS_IPV4_IHL 0x5
669 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
670 #define MVPP2_PRS_IPV6_MC 0xff
671 #define MVPP2_PRS_IPV6_MC_MASK 0xff
672 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
673 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
674 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
675 #define MVPP2_PRS_DBL_VLANS_MAX 100
678 * - lookup ID - 4 bits
680 * - additional information - 1 byte
681 * - header data - 8 bytes
682 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
684 #define MVPP2_PRS_AI_BITS 8
685 #define MVPP2_PRS_PORT_MASK 0xff
686 #define MVPP2_PRS_LU_MASK 0xf
687 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
688 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
689 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
690 (((offs) * 2) - ((offs) % 2) + 2)
691 #define MVPP2_PRS_TCAM_AI_BYTE 16
692 #define MVPP2_PRS_TCAM_PORT_BYTE 17
693 #define MVPP2_PRS_TCAM_LU_BYTE 20
694 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
695 #define MVPP2_PRS_TCAM_INV_WORD 5
696 /* Tcam entries ID */
697 #define MVPP2_PE_DROP_ALL 0
698 #define MVPP2_PE_FIRST_FREE_TID 1
699 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
700 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
701 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
702 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
703 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
704 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
705 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
706 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
707 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
708 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
709 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
710 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
711 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
712 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
713 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
714 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
715 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
716 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
717 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
718 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
719 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
720 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
721 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
722 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
723 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
726 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
728 #define MVPP2_PRS_SRAM_RI_OFFS 0
729 #define MVPP2_PRS_SRAM_RI_WORD 0
730 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
731 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
732 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
733 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
734 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
735 #define MVPP2_PRS_SRAM_UDF_OFFS 73
736 #define MVPP2_PRS_SRAM_UDF_BITS 8
737 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
738 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
739 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
740 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
741 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
742 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
743 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
744 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
745 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
746 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
747 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
748 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
749 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
750 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
751 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
752 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
753 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
754 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
755 #define MVPP2_PRS_SRAM_AI_OFFS 90
756 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
757 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
758 #define MVPP2_PRS_SRAM_AI_MASK 0xff
759 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
760 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
761 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
762 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
764 /* Sram result info bits assignment */
765 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
766 #define MVPP2_PRS_RI_DSA_MASK 0x2
767 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
768 #define MVPP2_PRS_RI_VLAN_NONE 0x0
769 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
770 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
771 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
772 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
773 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
774 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
775 #define MVPP2_PRS_RI_L2_UCAST 0x0
776 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
777 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
778 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
779 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
780 #define MVPP2_PRS_RI_L3_UN 0x0
781 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
782 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
783 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
784 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
785 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
786 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
787 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
788 #define MVPP2_PRS_RI_L3_UCAST 0x0
789 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
790 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
791 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
792 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
793 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
794 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
795 #define MVPP2_PRS_RI_L4_TCP BIT(22)
796 #define MVPP2_PRS_RI_L4_UDP BIT(23)
797 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
798 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
799 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
800 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
802 /* Sram additional info bits assignment */
803 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
804 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
805 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
806 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
807 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
808 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
809 #define MVPP2_PRS_SINGLE_VLAN_AI 0
810 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
813 #define MVPP2_PRS_TAGGED true
814 #define MVPP2_PRS_UNTAGGED false
815 #define MVPP2_PRS_EDSA true
816 #define MVPP2_PRS_DSA false
818 /* MAC entries, shadow udf */
820 MVPP2_PRS_UDF_MAC_DEF,
821 MVPP2_PRS_UDF_MAC_RANGE,
822 MVPP2_PRS_UDF_L2_DEF,
823 MVPP2_PRS_UDF_L2_DEF_COPY,
824 MVPP2_PRS_UDF_L2_USER,
828 enum mvpp2_prs_lookup {
842 enum mvpp2_prs_l3_cast {
843 MVPP2_PRS_L3_UNI_CAST,
844 MVPP2_PRS_L3_MULTI_CAST,
845 MVPP2_PRS_L3_BROAD_CAST
848 /* Classifier constants */
849 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
850 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
851 #define MVPP2_CLS_LKP_TBL_SIZE 64
854 #define MVPP2_BM_POOLS_NUM 1
855 #define MVPP2_BM_LONG_BUF_NUM 16
856 #define MVPP2_BM_SHORT_BUF_NUM 16
857 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
858 #define MVPP2_BM_POOL_PTR_ALIGN 128
859 #define MVPP2_BM_SWF_LONG_POOL(port) 0
861 /* BM cookie (32 bits) definition */
862 #define MVPP2_BM_COOKIE_POOL_OFFS 8
863 #define MVPP2_BM_COOKIE_CPU_OFFS 24
865 /* BM short pool packet size
866 * These value assure that for SWF the total number
867 * of bytes allocated for each buffer will be 512
869 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
879 /* Shared Packet Processor resources */
881 /* Shared registers' base addresses */
883 void __iomem *lms_base;
884 void __iomem *iface_base;
886 void __iomem *mpcs_base;
887 void __iomem *xpcs_base;
888 void __iomem *rfu1_base;
892 /* List of pointers to port structures */
893 struct mvpp2_port **port_list;
895 /* Aggregated TXQs */
896 struct mvpp2_tx_queue *aggr_txqs;
899 struct mvpp2_bm_pool *bm_pools;
901 /* PRS shadow table */
902 struct mvpp2_prs_shadow *prs_shadow;
903 /* PRS auxiliary table for double vlan entries control */
904 bool *prs_double_vlans;
910 enum { MVPP21, MVPP22 } hw_version;
912 /* Maximum number of RXQs per port */
913 unsigned int max_port_rxqs;
919 struct mvpp2_pcpu_stats {
929 /* Index of the port from the "group of ports" complex point
938 /* Per-port registers' base address */
941 struct mvpp2_rx_queue **rxqs;
942 struct mvpp2_tx_queue **txqs;
946 u32 pending_cause_rx;
948 /* Per-CPU port control */
949 struct mvpp2_port_pcpu __percpu *pcpu;
956 struct mvpp2_pcpu_stats __percpu *stats;
958 struct phy_device *phy_dev;
959 phy_interface_t phy_interface;
961 struct udevice *mdio_dev;
963 #if CONFIG_IS_ENABLED(DM_GPIO)
964 struct gpio_desc phy_reset_gpio;
965 struct gpio_desc phy_tx_disable_gpio;
972 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
974 struct mvpp2_bm_pool *pool_long;
975 struct mvpp2_bm_pool *pool_short;
977 /* Index of first port's physical RXQ */
980 u8 dev_addr[ETH_ALEN];
983 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
984 * layout of the transmit and reception DMA descriptors, and their
985 * layout is therefore defined by the hardware design
988 #define MVPP2_TXD_L3_OFF_SHIFT 0
989 #define MVPP2_TXD_IP_HLEN_SHIFT 8
990 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
991 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
992 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
993 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
994 #define MVPP2_TXD_L4_UDP BIT(24)
995 #define MVPP2_TXD_L3_IP6 BIT(26)
996 #define MVPP2_TXD_L_DESC BIT(28)
997 #define MVPP2_TXD_F_DESC BIT(29)
999 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
1000 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1001 #define MVPP2_RXD_ERR_CRC 0x0
1002 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
1003 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1004 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
1005 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1006 #define MVPP2_RXD_HWF_SYNC BIT(21)
1007 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
1008 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1009 #define MVPP2_RXD_L4_TCP BIT(25)
1010 #define MVPP2_RXD_L4_UDP BIT(26)
1011 #define MVPP2_RXD_L3_IP4 BIT(28)
1012 #define MVPP2_RXD_L3_IP6 BIT(30)
1013 #define MVPP2_RXD_BUF_HDR BIT(31)
1015 /* HW TX descriptor for PPv2.1 */
1016 struct mvpp21_tx_desc {
1017 u32 command; /* Options used by HW for packet transmitting.*/
1018 u8 packet_offset; /* the offset from the buffer beginning */
1019 u8 phys_txq; /* destination queue ID */
1020 u16 data_size; /* data size of transmitted packet in bytes */
1021 u32 buf_dma_addr; /* physical addr of transmitted buffer */
1022 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1023 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1024 u32 reserved2; /* reserved (for future use) */
1027 /* HW RX descriptor for PPv2.1 */
1028 struct mvpp21_rx_desc {
1029 u32 status; /* info about received packet */
1030 u16 reserved1; /* parser_info (for future use, PnC) */
1031 u16 data_size; /* size of received packet in bytes */
1032 u32 buf_dma_addr; /* physical address of the buffer */
1033 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1034 u16 reserved2; /* gem_port_id (for future use, PON) */
1035 u16 reserved3; /* csum_l4 (for future use, PnC) */
1036 u8 reserved4; /* bm_qset (for future use, BM) */
1038 u16 reserved6; /* classify_info (for future use, PnC) */
1039 u32 reserved7; /* flow_id (for future use, PnC) */
1043 /* HW TX descriptor for PPv2.2 */
1044 struct mvpp22_tx_desc {
1050 u64 buf_dma_addr_ptp;
1051 u64 buf_cookie_misc;
1054 /* HW RX descriptor for PPv2.2 */
1055 struct mvpp22_rx_desc {
1061 u64 buf_dma_addr_key_hash;
1062 u64 buf_cookie_misc;
1065 /* Opaque type used by the driver to manipulate the HW TX and RX
1068 struct mvpp2_tx_desc {
1070 struct mvpp21_tx_desc pp21;
1071 struct mvpp22_tx_desc pp22;
1075 struct mvpp2_rx_desc {
1077 struct mvpp21_rx_desc pp21;
1078 struct mvpp22_rx_desc pp22;
1082 /* Per-CPU Tx queue control */
1083 struct mvpp2_txq_pcpu {
1086 /* Number of Tx DMA descriptors in the descriptor ring */
1089 /* Number of currently used Tx DMA descriptor in the
1094 /* Number of Tx DMA descriptors reserved for each CPU */
1097 /* Index of last TX DMA descriptor that was inserted */
1100 /* Index of the TX DMA descriptor to be cleaned up */
1104 struct mvpp2_tx_queue {
1105 /* Physical number of this Tx queue */
1108 /* Logical number of this Tx queue */
1111 /* Number of Tx DMA descriptors in the descriptor ring */
1114 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1117 /* Per-CPU control of physical Tx queues */
1118 struct mvpp2_txq_pcpu __percpu *pcpu;
1122 /* Virtual address of thex Tx DMA descriptors array */
1123 struct mvpp2_tx_desc *descs;
1125 /* DMA address of the Tx DMA descriptors array */
1126 dma_addr_t descs_dma;
1128 /* Index of the last Tx DMA descriptor */
1131 /* Index of the next Tx DMA descriptor to process */
1132 int next_desc_to_proc;
1135 struct mvpp2_rx_queue {
1136 /* RX queue number, in the range 0-31 for physical RXQs */
1139 /* Num of rx descriptors in the rx descriptor ring */
1145 /* Virtual address of the RX DMA descriptors array */
1146 struct mvpp2_rx_desc *descs;
1148 /* DMA address of the RX DMA descriptors array */
1149 dma_addr_t descs_dma;
1151 /* Index of the last RX DMA descriptor */
1154 /* Index of the next RX DMA descriptor to process */
1155 int next_desc_to_proc;
1157 /* ID of port to which physical RXQ is mapped */
1160 /* Port's logic RXQ number to which physical RXQ is mapped */
1164 union mvpp2_prs_tcam_entry {
1165 u32 word[MVPP2_PRS_TCAM_WORDS];
1166 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1169 union mvpp2_prs_sram_entry {
1170 u32 word[MVPP2_PRS_SRAM_WORDS];
1171 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1174 struct mvpp2_prs_entry {
1176 union mvpp2_prs_tcam_entry tcam;
1177 union mvpp2_prs_sram_entry sram;
1180 struct mvpp2_prs_shadow {
1187 /* User defined offset */
1195 struct mvpp2_cls_flow_entry {
1197 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1200 struct mvpp2_cls_lookup_entry {
1206 struct mvpp2_bm_pool {
1207 /* Pool number in the range 0-7 */
1209 enum mvpp2_bm_type type;
1211 /* Buffer Pointers Pool External (BPPE) size */
1213 /* Number of buffers for this pool */
1215 /* Pool buffer size */
1220 /* BPPE virtual base address */
1221 unsigned long *virt_addr;
1222 /* BPPE DMA base address */
1223 dma_addr_t dma_addr;
1225 /* Ports using BM pool */
1229 /* Static declaractions */
1231 /* Number of RXQs used by single port */
1232 static int rxq_number = MVPP2_DEFAULT_RXQ;
1233 /* Number of TXQs used by single port */
1234 static int txq_number = MVPP2_DEFAULT_TXQ;
1238 #define MVPP2_DRIVER_NAME "mvpp2"
1239 #define MVPP2_DRIVER_VERSION "1.0"
1242 * U-Boot internal data, mostly uncached buffers for descriptors and data
1244 struct buffer_location {
1245 struct mvpp2_tx_desc *aggr_tx_descs;
1246 struct mvpp2_tx_desc *tx_descs;
1247 struct mvpp2_rx_desc *rx_descs;
1248 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1249 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1254 * All 4 interfaces use the same global buffer, since only one interface
1255 * can be enabled at once
1257 static struct buffer_location buffer_loc;
1260 * Page table entries are set to 1MB, or multiples of 1MB
1261 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1263 #define BD_SPACE (1 << 20)
1265 /* Utility/helper methods */
1267 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1269 writel(data, priv->base + offset);
1272 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1274 return readl(priv->base + offset);
1277 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1278 struct mvpp2_tx_desc *tx_desc,
1279 dma_addr_t dma_addr)
1281 if (port->priv->hw_version == MVPP21) {
1282 tx_desc->pp21.buf_dma_addr = dma_addr;
1284 u64 val = (u64)dma_addr;
1286 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1287 tx_desc->pp22.buf_dma_addr_ptp |= val;
1291 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1292 struct mvpp2_tx_desc *tx_desc,
1295 if (port->priv->hw_version == MVPP21)
1296 tx_desc->pp21.data_size = size;
1298 tx_desc->pp22.data_size = size;
1301 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1302 struct mvpp2_tx_desc *tx_desc,
1305 if (port->priv->hw_version == MVPP21)
1306 tx_desc->pp21.phys_txq = txq;
1308 tx_desc->pp22.phys_txq = txq;
1311 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1312 struct mvpp2_tx_desc *tx_desc,
1313 unsigned int command)
1315 if (port->priv->hw_version == MVPP21)
1316 tx_desc->pp21.command = command;
1318 tx_desc->pp22.command = command;
1321 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1322 struct mvpp2_tx_desc *tx_desc,
1323 unsigned int offset)
1325 if (port->priv->hw_version == MVPP21)
1326 tx_desc->pp21.packet_offset = offset;
1328 tx_desc->pp22.packet_offset = offset;
1331 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1332 struct mvpp2_rx_desc *rx_desc)
1334 if (port->priv->hw_version == MVPP21)
1335 return rx_desc->pp21.buf_dma_addr;
1337 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1340 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1341 struct mvpp2_rx_desc *rx_desc)
1343 if (port->priv->hw_version == MVPP21)
1344 return rx_desc->pp21.buf_cookie;
1346 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1349 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1350 struct mvpp2_rx_desc *rx_desc)
1352 if (port->priv->hw_version == MVPP21)
1353 return rx_desc->pp21.data_size;
1355 return rx_desc->pp22.data_size;
1358 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1359 struct mvpp2_rx_desc *rx_desc)
1361 if (port->priv->hw_version == MVPP21)
1362 return rx_desc->pp21.status;
1364 return rx_desc->pp22.status;
1367 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1369 txq_pcpu->txq_get_index++;
1370 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1371 txq_pcpu->txq_get_index = 0;
1374 /* Get number of physical egress port */
1375 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1377 return MVPP2_MAX_TCONT + port->id;
1380 /* Get number of physical TXQ */
1381 static inline int mvpp2_txq_phys(int port, int txq)
1383 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1386 /* Parser configuration routines */
1388 /* Update parser tcam and sram hw entries */
1389 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1393 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1396 /* Clear entry invalidation bit */
1397 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1399 /* Write tcam index - indirect access */
1400 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1401 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1402 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1404 /* Write sram index - indirect access */
1405 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1406 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1407 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1412 /* Read tcam entry from hw */
1413 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1417 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1420 /* Write tcam index - indirect access */
1421 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1423 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1424 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1425 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1426 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1428 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1429 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1431 /* Write sram index - indirect access */
1432 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1433 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1434 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1439 /* Invalidate tcam hw entry */
1440 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1442 /* Write index - indirect access */
1443 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1444 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1445 MVPP2_PRS_TCAM_INV_MASK);
1448 /* Enable shadow table entry and set its lookup ID */
1449 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1451 priv->prs_shadow[index].valid = true;
1452 priv->prs_shadow[index].lu = lu;
1455 /* Update ri fields in shadow table entry */
1456 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1457 unsigned int ri, unsigned int ri_mask)
1459 priv->prs_shadow[index].ri_mask = ri_mask;
1460 priv->prs_shadow[index].ri = ri;
1463 /* Update lookup field in tcam sw entry */
1464 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1466 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1468 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1469 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1472 /* Update mask for single port in tcam sw entry */
1473 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1474 unsigned int port, bool add)
1476 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1479 pe->tcam.byte[enable_off] &= ~(1 << port);
1481 pe->tcam.byte[enable_off] |= 1 << port;
1484 /* Update port map in tcam sw entry */
1485 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1488 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1489 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1491 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1492 pe->tcam.byte[enable_off] &= ~port_mask;
1493 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1496 /* Obtain port map from tcam sw entry */
1497 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1499 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1501 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1504 /* Set byte of data and its enable bits in tcam sw entry */
1505 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1506 unsigned int offs, unsigned char byte,
1507 unsigned char enable)
1509 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1510 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1513 /* Get byte of data and its enable bits from tcam sw entry */
1514 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1515 unsigned int offs, unsigned char *byte,
1516 unsigned char *enable)
1518 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1519 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1522 /* Set ethertype in tcam sw entry */
1523 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1524 unsigned short ethertype)
1526 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1527 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1530 /* Set bits in sram sw entry */
1531 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1534 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1537 /* Clear bits in sram sw entry */
1538 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1541 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1544 /* Update ri bits in sram sw entry */
1545 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1546 unsigned int bits, unsigned int mask)
1550 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1551 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1553 if (!(mask & BIT(i)))
1557 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1559 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1561 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1565 /* Update ai bits in sram sw entry */
1566 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1567 unsigned int bits, unsigned int mask)
1570 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1572 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1574 if (!(mask & BIT(i)))
1578 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1580 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1582 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1586 /* Read ai bits from sram sw entry */
1587 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1590 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1591 int ai_en_off = ai_off + 1;
1592 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1594 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1595 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1600 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1603 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1606 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1608 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1609 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1610 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1613 /* In the sram sw entry set sign and value of the next lookup offset
1614 * and the offset value generated to the classifier
1616 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1621 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1624 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1628 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1629 (unsigned char)shift;
1631 /* Reset and set operation */
1632 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1633 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1634 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1636 /* Set base offset as current */
1637 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1640 /* In the sram sw entry set sign and value of the user defined offset
1641 * generated to the classifier
1643 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1644 unsigned int type, int offset,
1649 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1650 offset = 0 - offset;
1652 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1656 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1657 MVPP2_PRS_SRAM_UDF_MASK);
1658 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1659 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1660 MVPP2_PRS_SRAM_UDF_BITS)] &=
1661 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1662 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1663 MVPP2_PRS_SRAM_UDF_BITS)] |=
1664 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1666 /* Set offset type */
1667 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1668 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1669 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1671 /* Set offset operation */
1672 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1673 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1674 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1676 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1677 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1678 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1679 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1681 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1682 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1683 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1685 /* Set base offset as current */
1686 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1689 /* Find parser flow entry */
1690 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1692 struct mvpp2_prs_entry *pe;
1695 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1698 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1700 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1701 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1704 if (!priv->prs_shadow[tid].valid ||
1705 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1709 mvpp2_prs_hw_read(priv, pe);
1710 bits = mvpp2_prs_sram_ai_get(pe);
1712 /* Sram store classification lookup ID in AI bits [5:0] */
1713 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1721 /* Return first free tcam index, seeking from start to end */
1722 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1730 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1731 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1733 for (tid = start; tid <= end; tid++) {
1734 if (!priv->prs_shadow[tid].valid)
1741 /* Enable/disable dropping all mac da's */
1742 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1744 struct mvpp2_prs_entry pe;
1746 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1747 /* Entry exist - update port only */
1748 pe.index = MVPP2_PE_DROP_ALL;
1749 mvpp2_prs_hw_read(priv, &pe);
1751 /* Entry doesn't exist - create new */
1752 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1753 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1754 pe.index = MVPP2_PE_DROP_ALL;
1756 /* Non-promiscuous mode for all ports - DROP unknown packets */
1757 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1758 MVPP2_PRS_RI_DROP_MASK);
1760 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1761 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1763 /* Update shadow table */
1764 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1766 /* Mask all ports */
1767 mvpp2_prs_tcam_port_map_set(&pe, 0);
1770 /* Update port mask */
1771 mvpp2_prs_tcam_port_set(&pe, port, add);
1773 mvpp2_prs_hw_write(priv, &pe);
1776 /* Set port to promiscuous mode */
1777 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1779 struct mvpp2_prs_entry pe;
1781 /* Promiscuous mode - Accept unknown packets */
1783 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1784 /* Entry exist - update port only */
1785 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1786 mvpp2_prs_hw_read(priv, &pe);
1788 /* Entry doesn't exist - create new */
1789 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1790 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1791 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1793 /* Continue - set next lookup */
1794 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1796 /* Set result info bits */
1797 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1798 MVPP2_PRS_RI_L2_CAST_MASK);
1800 /* Shift to ethertype */
1801 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1802 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1804 /* Mask all ports */
1805 mvpp2_prs_tcam_port_map_set(&pe, 0);
1807 /* Update shadow table */
1808 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1811 /* Update port mask */
1812 mvpp2_prs_tcam_port_set(&pe, port, add);
1814 mvpp2_prs_hw_write(priv, &pe);
1817 /* Accept multicast */
1818 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1821 struct mvpp2_prs_entry pe;
1822 unsigned char da_mc;
1824 /* Ethernet multicast address first byte is
1825 * 0x01 for IPv4 and 0x33 for IPv6
1827 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1829 if (priv->prs_shadow[index].valid) {
1830 /* Entry exist - update port only */
1832 mvpp2_prs_hw_read(priv, &pe);
1834 /* Entry doesn't exist - create new */
1835 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1836 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1839 /* Continue - set next lookup */
1840 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1842 /* Set result info bits */
1843 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1844 MVPP2_PRS_RI_L2_CAST_MASK);
1846 /* Update tcam entry data first byte */
1847 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1849 /* Shift to ethertype */
1850 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1851 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1853 /* Mask all ports */
1854 mvpp2_prs_tcam_port_map_set(&pe, 0);
1856 /* Update shadow table */
1857 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1860 /* Update port mask */
1861 mvpp2_prs_tcam_port_set(&pe, port, add);
1863 mvpp2_prs_hw_write(priv, &pe);
1866 /* Parser per-port initialization */
1867 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1868 int lu_max, int offset)
1873 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1874 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1875 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1876 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1878 /* Set maximum number of loops for packet received from port */
1879 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1880 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1881 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1882 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1884 /* Set initial offset for packet header extraction for the first
1887 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1888 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1889 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1890 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1893 /* Default flow entries initialization for all ports */
1894 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1896 struct mvpp2_prs_entry pe;
1899 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1900 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1901 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1902 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1904 /* Mask all ports */
1905 mvpp2_prs_tcam_port_map_set(&pe, 0);
1908 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1909 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1911 /* Update shadow table and hw entry */
1912 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1913 mvpp2_prs_hw_write(priv, &pe);
1917 /* Set default entry for Marvell Header field */
1918 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1920 struct mvpp2_prs_entry pe;
1922 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1924 pe.index = MVPP2_PE_MH_DEFAULT;
1925 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1926 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1927 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1928 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1930 /* Unmask all ports */
1931 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1933 /* Update shadow table and hw entry */
1934 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1935 mvpp2_prs_hw_write(priv, &pe);
1938 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1939 * multicast MAC addresses
1941 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1943 struct mvpp2_prs_entry pe;
1945 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1947 /* Non-promiscuous mode for all ports - DROP unknown packets */
1948 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1949 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1951 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1952 MVPP2_PRS_RI_DROP_MASK);
1953 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1954 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1956 /* Unmask all ports */
1957 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1959 /* Update shadow table and hw entry */
1960 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1961 mvpp2_prs_hw_write(priv, &pe);
1963 /* place holders only - no ports */
1964 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1965 mvpp2_prs_mac_promisc_set(priv, 0, false);
1966 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1967 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1970 /* Match basic ethertypes */
1971 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1973 struct mvpp2_prs_entry pe;
1976 /* Ethertype: PPPoE */
1977 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1978 MVPP2_PE_LAST_FREE_TID);
1982 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1983 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1986 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1988 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1989 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1990 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1991 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1992 MVPP2_PRS_RI_PPPOE_MASK);
1994 /* Update shadow table and hw entry */
1995 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1996 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1997 priv->prs_shadow[pe.index].finish = false;
1998 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1999 MVPP2_PRS_RI_PPPOE_MASK);
2000 mvpp2_prs_hw_write(priv, &pe);
2002 /* Ethertype: ARP */
2003 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2004 MVPP2_PE_LAST_FREE_TID);
2008 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2009 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2012 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2014 /* Generate flow in the next iteration*/
2015 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2016 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2017 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2018 MVPP2_PRS_RI_L3_PROTO_MASK);
2020 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2022 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2024 /* Update shadow table and hw entry */
2025 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2026 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2027 priv->prs_shadow[pe.index].finish = true;
2028 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2029 MVPP2_PRS_RI_L3_PROTO_MASK);
2030 mvpp2_prs_hw_write(priv, &pe);
2032 /* Ethertype: LBTD */
2033 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2034 MVPP2_PE_LAST_FREE_TID);
2038 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2039 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2042 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2044 /* Generate flow in the next iteration*/
2045 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2046 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2047 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2048 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2049 MVPP2_PRS_RI_CPU_CODE_MASK |
2050 MVPP2_PRS_RI_UDF3_MASK);
2052 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2054 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2056 /* Update shadow table and hw entry */
2057 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2058 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2059 priv->prs_shadow[pe.index].finish = true;
2060 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2061 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2062 MVPP2_PRS_RI_CPU_CODE_MASK |
2063 MVPP2_PRS_RI_UDF3_MASK);
2064 mvpp2_prs_hw_write(priv, &pe);
2066 /* Ethertype: IPv4 without options */
2067 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2068 MVPP2_PE_LAST_FREE_TID);
2072 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2073 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2076 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2077 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2078 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2079 MVPP2_PRS_IPV4_HEAD_MASK |
2080 MVPP2_PRS_IPV4_IHL_MASK);
2082 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2083 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2084 MVPP2_PRS_RI_L3_PROTO_MASK);
2085 /* Skip eth_type + 4 bytes of IP header */
2086 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2087 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2089 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2091 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2093 /* Update shadow table and hw entry */
2094 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2095 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2096 priv->prs_shadow[pe.index].finish = false;
2097 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2098 MVPP2_PRS_RI_L3_PROTO_MASK);
2099 mvpp2_prs_hw_write(priv, &pe);
2101 /* Ethertype: IPv4 with options */
2102 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2103 MVPP2_PE_LAST_FREE_TID);
2109 /* Clear tcam data before updating */
2110 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2111 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2113 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2114 MVPP2_PRS_IPV4_HEAD,
2115 MVPP2_PRS_IPV4_HEAD_MASK);
2117 /* Clear ri before updating */
2118 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2119 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2120 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2121 MVPP2_PRS_RI_L3_PROTO_MASK);
2123 /* Update shadow table and hw entry */
2124 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2125 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2126 priv->prs_shadow[pe.index].finish = false;
2127 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2128 MVPP2_PRS_RI_L3_PROTO_MASK);
2129 mvpp2_prs_hw_write(priv, &pe);
2131 /* Ethertype: IPv6 without options */
2132 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2133 MVPP2_PE_LAST_FREE_TID);
2137 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2138 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2141 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2143 /* Skip DIP of IPV6 header */
2144 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2145 MVPP2_MAX_L3_ADDR_SIZE,
2146 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2147 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2148 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2149 MVPP2_PRS_RI_L3_PROTO_MASK);
2151 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2153 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2155 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2156 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2157 priv->prs_shadow[pe.index].finish = false;
2158 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2159 MVPP2_PRS_RI_L3_PROTO_MASK);
2160 mvpp2_prs_hw_write(priv, &pe);
2162 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2163 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2164 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2165 pe.index = MVPP2_PE_ETH_TYPE_UN;
2167 /* Unmask all ports */
2168 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2170 /* Generate flow in the next iteration*/
2171 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2172 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2173 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2174 MVPP2_PRS_RI_L3_PROTO_MASK);
2175 /* Set L3 offset even it's unknown L3 */
2176 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2178 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2180 /* Update shadow table and hw entry */
2181 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2182 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2183 priv->prs_shadow[pe.index].finish = true;
2184 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2185 MVPP2_PRS_RI_L3_PROTO_MASK);
2186 mvpp2_prs_hw_write(priv, &pe);
2191 /* Parser default initialization */
2192 static int mvpp2_prs_default_init(struct udevice *dev,
2197 /* Enable tcam table */
2198 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2200 /* Clear all tcam and sram entries */
2201 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2202 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2203 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2204 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2206 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2207 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2208 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2211 /* Invalidate all tcam entries */
2212 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2213 mvpp2_prs_hw_inv(priv, index);
2215 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2216 sizeof(struct mvpp2_prs_shadow),
2218 if (!priv->prs_shadow)
2221 /* Always start from lookup = 0 */
2222 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2223 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2224 MVPP2_PRS_PORT_LU_MAX, 0);
2226 mvpp2_prs_def_flow_init(priv);
2228 mvpp2_prs_mh_init(priv);
2230 mvpp2_prs_mac_init(priv);
2232 err = mvpp2_prs_etype_init(priv);
2239 /* Compare MAC DA with tcam entry data */
2240 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2241 const u8 *da, unsigned char *mask)
2243 unsigned char tcam_byte, tcam_mask;
2246 for (index = 0; index < ETH_ALEN; index++) {
2247 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2248 if (tcam_mask != mask[index])
2251 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2258 /* Find tcam entry with matched pair <MAC DA, port> */
2259 static struct mvpp2_prs_entry *
2260 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2261 unsigned char *mask, int udf_type)
2263 struct mvpp2_prs_entry *pe;
2266 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2269 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2271 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2272 for (tid = MVPP2_PE_FIRST_FREE_TID;
2273 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2274 unsigned int entry_pmap;
2276 if (!priv->prs_shadow[tid].valid ||
2277 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2278 (priv->prs_shadow[tid].udf != udf_type))
2282 mvpp2_prs_hw_read(priv, pe);
2283 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2285 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2294 /* Update parser's mac da entry */
2295 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2296 const u8 *da, bool add)
2298 struct mvpp2_prs_entry *pe;
2299 unsigned int pmap, len, ri;
2300 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2303 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2304 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2305 MVPP2_PRS_UDF_MAC_DEF);
2312 /* Create new TCAM entry */
2313 /* Find first range mac entry*/
2314 for (tid = MVPP2_PE_FIRST_FREE_TID;
2315 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2316 if (priv->prs_shadow[tid].valid &&
2317 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2318 (priv->prs_shadow[tid].udf ==
2319 MVPP2_PRS_UDF_MAC_RANGE))
2322 /* Go through the all entries from first to last */
2323 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2328 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2331 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2334 /* Mask all ports */
2335 mvpp2_prs_tcam_port_map_set(pe, 0);
2338 /* Update port mask */
2339 mvpp2_prs_tcam_port_set(pe, port, add);
2341 /* Invalidate the entry if no ports are left enabled */
2342 pmap = mvpp2_prs_tcam_port_map_get(pe);
2348 mvpp2_prs_hw_inv(priv, pe->index);
2349 priv->prs_shadow[pe->index].valid = false;
2354 /* Continue - set next lookup */
2355 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2357 /* Set match on DA */
2360 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2362 /* Set result info bits */
2363 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2365 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2366 MVPP2_PRS_RI_MAC_ME_MASK);
2367 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2368 MVPP2_PRS_RI_MAC_ME_MASK);
2370 /* Shift to ethertype */
2371 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2372 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2374 /* Update shadow table and hw entry */
2375 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2376 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2377 mvpp2_prs_hw_write(priv, pe);
2384 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2388 /* Remove old parser entry */
2389 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2394 /* Add new parser entry */
2395 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2399 /* Set addr in the device */
2400 memcpy(port->dev_addr, da, ETH_ALEN);
2405 /* Set prs flow for the port */
2406 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2408 struct mvpp2_prs_entry *pe;
2411 pe = mvpp2_prs_flow_find(port->priv, port->id);
2413 /* Such entry not exist */
2415 /* Go through the all entires from last to first */
2416 tid = mvpp2_prs_tcam_first_free(port->priv,
2417 MVPP2_PE_LAST_FREE_TID,
2418 MVPP2_PE_FIRST_FREE_TID);
2422 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2426 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2430 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2431 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2433 /* Update shadow table */
2434 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2437 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2438 mvpp2_prs_hw_write(port->priv, pe);
2444 /* Classifier configuration routines */
2446 /* Update classification flow table registers */
2447 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2448 struct mvpp2_cls_flow_entry *fe)
2450 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2451 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2452 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2453 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2456 /* Update classification lookup table register */
2457 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2458 struct mvpp2_cls_lookup_entry *le)
2462 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2463 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2464 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2467 /* Classifier default initialization */
2468 static void mvpp2_cls_init(struct mvpp2 *priv)
2470 struct mvpp2_cls_lookup_entry le;
2471 struct mvpp2_cls_flow_entry fe;
2474 /* Enable classifier */
2475 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2477 /* Clear classifier flow table */
2478 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2479 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2481 mvpp2_cls_flow_write(priv, &fe);
2484 /* Clear classifier lookup table */
2486 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2489 mvpp2_cls_lookup_write(priv, &le);
2492 mvpp2_cls_lookup_write(priv, &le);
2496 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2498 struct mvpp2_cls_lookup_entry le;
2501 /* Set way for the port */
2502 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2503 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2504 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2506 /* Pick the entry to be accessed in lookup ID decoding table
2507 * according to the way and lkpid.
2509 le.lkpid = port->id;
2513 /* Set initial CPU queue for receiving packets */
2514 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2515 le.data |= port->first_rxq;
2517 /* Disable classification engines */
2518 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2520 /* Update lookup ID table entry */
2521 mvpp2_cls_lookup_write(port->priv, &le);
2524 /* Set CPU queue number for oversize packets */
2525 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2529 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2530 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2532 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2533 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2535 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2536 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2537 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2540 /* Buffer Manager configuration routines */
2543 static int mvpp2_bm_pool_create(struct udevice *dev,
2545 struct mvpp2_bm_pool *bm_pool, int size)
2549 /* Number of buffer pointers must be a multiple of 16, as per
2550 * hardware constraints
2552 if (!IS_ALIGNED(size, 16))
2555 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2556 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2557 if (!bm_pool->virt_addr)
2560 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2561 MVPP2_BM_POOL_PTR_ALIGN)) {
2562 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2563 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2567 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2568 lower_32_bits(bm_pool->dma_addr));
2569 if (priv->hw_version == MVPP22)
2570 mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
2571 (upper_32_bits(bm_pool->dma_addr) &
2572 MVPP22_BM_POOL_BASE_HIGH_MASK));
2573 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2575 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2576 val |= MVPP2_BM_START_MASK;
2577 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2579 bm_pool->type = MVPP2_BM_FREE;
2580 bm_pool->size = size;
2581 bm_pool->pkt_size = 0;
2582 bm_pool->buf_num = 0;
2587 /* Set pool buffer size */
2588 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2589 struct mvpp2_bm_pool *bm_pool,
2594 bm_pool->buf_size = buf_size;
2596 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2597 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2600 /* Free all buffers from the pool */
2601 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2602 struct mvpp2_bm_pool *bm_pool)
2606 for (i = 0; i < bm_pool->buf_num; i++) {
2607 /* Allocate buffer back from the buffer manager */
2608 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2611 bm_pool->buf_num = 0;
2615 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2617 struct mvpp2_bm_pool *bm_pool)
2621 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2622 if (bm_pool->buf_num) {
2623 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2627 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2628 val |= MVPP2_BM_STOP_MASK;
2629 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2634 static int mvpp2_bm_pools_init(struct udevice *dev,
2638 struct mvpp2_bm_pool *bm_pool;
2640 /* Create all pools with maximum size */
2641 size = MVPP2_BM_POOL_SIZE_MAX;
2642 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2643 bm_pool = &priv->bm_pools[i];
2645 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2647 goto err_unroll_pools;
2648 mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
2653 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2654 for (i = i - 1; i >= 0; i--)
2655 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2659 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2663 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2664 /* Mask BM all interrupts */
2665 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2666 /* Clear BM cause register */
2667 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2670 /* Allocate and initialize BM pools */
2671 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2672 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2673 if (!priv->bm_pools)
2676 err = mvpp2_bm_pools_init(dev, priv);
2682 /* Attach long pool to rxq */
2683 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2684 int lrxq, int long_pool)
2689 /* Get queue physical ID */
2690 prxq = port->rxqs[lrxq]->id;
2692 if (port->priv->hw_version == MVPP21)
2693 mask = MVPP21_RXQ_POOL_LONG_MASK;
2695 mask = MVPP22_RXQ_POOL_LONG_MASK;
2697 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2699 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2700 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2703 /* Set pool number in a BM cookie */
2704 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2708 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2709 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2714 /* Get pool number from a BM cookie */
2715 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2717 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2720 /* Release buffer to BM */
2721 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2722 dma_addr_t buf_dma_addr,
2723 unsigned long buf_phys_addr)
2725 if (port->priv->hw_version == MVPP22) {
2728 if (sizeof(dma_addr_t) == 8)
2729 val |= upper_32_bits(buf_dma_addr) &
2730 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2732 if (sizeof(phys_addr_t) == 8)
2733 val |= (upper_32_bits(buf_phys_addr)
2734 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2735 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2737 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2740 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2741 * returned in the "cookie" field of the RX
2742 * descriptor. Instead of storing the virtual address, we
2743 * store the physical address
2745 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2746 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2749 /* Refill BM pool */
2750 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2751 dma_addr_t dma_addr,
2752 phys_addr_t phys_addr)
2754 int pool = mvpp2_bm_cookie_pool_get(bm);
2756 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2759 /* Allocate buffers for the pool */
2760 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2761 struct mvpp2_bm_pool *bm_pool, int buf_num)
2766 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2767 netdev_err(port->dev,
2768 "cannot allocate %d buffers for pool %d\n",
2769 buf_num, bm_pool->id);
2773 for (i = 0; i < buf_num; i++) {
2774 mvpp2_bm_pool_put(port, bm_pool->id,
2775 (dma_addr_t)buffer_loc.rx_buffer[i],
2776 (unsigned long)buffer_loc.rx_buffer[i]);
2780 /* Update BM driver with number of buffers added to pool */
2781 bm_pool->buf_num += i;
2786 /* Notify the driver that BM pool is being used as specific type and return the
2787 * pool pointer on success
2789 static struct mvpp2_bm_pool *
2790 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2793 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2796 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2797 netdev_err(port->dev, "mixing pool types is forbidden\n");
2801 if (new_pool->type == MVPP2_BM_FREE)
2802 new_pool->type = type;
2804 /* Allocate buffers in case BM pool is used as long pool, but packet
2805 * size doesn't match MTU or BM pool hasn't being used yet
2807 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2808 (new_pool->pkt_size == 0)) {
2811 /* Set default buffer number or free all the buffers in case
2812 * the pool is not empty
2814 pkts_num = new_pool->buf_num;
2816 pkts_num = type == MVPP2_BM_SWF_LONG ?
2817 MVPP2_BM_LONG_BUF_NUM :
2818 MVPP2_BM_SHORT_BUF_NUM;
2820 mvpp2_bm_bufs_free(NULL,
2821 port->priv, new_pool);
2823 new_pool->pkt_size = pkt_size;
2825 /* Allocate buffers for this pool */
2826 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2827 if (num != pkts_num) {
2828 dev_err(dev, "pool %d: %d of %d allocated\n",
2829 new_pool->id, num, pkts_num);
2837 /* Initialize pools for swf */
2838 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2842 if (!port->pool_long) {
2844 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2847 if (!port->pool_long)
2850 port->pool_long->port_map |= (1 << port->id);
2852 for (rxq = 0; rxq < rxq_number; rxq++)
2853 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2859 /* Port configuration routines */
2861 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2865 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2867 switch (port->phy_interface) {
2868 case PHY_INTERFACE_MODE_SGMII:
2869 val |= MVPP2_GMAC_INBAND_AN_MASK;
2871 case PHY_INTERFACE_MODE_RGMII:
2872 case PHY_INTERFACE_MODE_RGMII_ID:
2873 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2875 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2878 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2881 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2885 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2886 val |= MVPP2_GMAC_FC_ADV_EN;
2887 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2890 static void mvpp2_port_enable(struct mvpp2_port *port)
2894 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2895 val |= MVPP2_GMAC_PORT_EN_MASK;
2896 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2897 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2900 static void mvpp2_port_disable(struct mvpp2_port *port)
2904 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2905 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2906 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2909 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2910 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2914 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2915 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2916 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2919 /* Configure loopback port */
2920 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2924 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2926 if (port->speed == 1000)
2927 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2929 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2931 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2932 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2934 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2936 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2939 static void mvpp2_port_reset(struct mvpp2_port *port)
2943 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2944 ~MVPP2_GMAC_PORT_RESET_MASK;
2945 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2947 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2948 MVPP2_GMAC_PORT_RESET_MASK)
2952 /* Change maximum receive size of the port */
2953 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2957 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2958 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2959 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2960 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2961 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2964 /* PPv2.2 GoP/GMAC config */
2966 /* Set the MAC to reset or exit from reset */
2967 static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2971 /* read - modify - write */
2972 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2974 val |= MVPP2_GMAC_PORT_RESET_MASK;
2976 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
2977 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2985 * Configure port to working with Gig PCS or don't.
2987 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
2991 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2993 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
2995 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2996 /* enable / disable PCS on this port */
2997 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3002 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3006 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3008 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3010 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3011 /* enable / disable PCS on this port */
3012 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3017 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3022 * Configure minimal level of the Tx FIFO before the lower part
3023 * starts to read a packet
3025 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3026 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3027 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3028 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3029 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3031 /* Disable bypass of sync module */
3032 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3033 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3034 /* configure DP clock select according to mode */
3035 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3036 /* configure QSGMII bypass according to mode */
3037 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3038 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3040 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3042 * Configure GIG MAC to 1000Base-X mode connected to a fiber
3045 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3046 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3048 /* configure AN 0x9268 */
3049 val = MVPP2_GMAC_EN_PCS_AN |
3050 MVPP2_GMAC_AN_BYPASS_EN |
3051 MVPP2_GMAC_CONFIG_MII_SPEED |
3052 MVPP2_GMAC_CONFIG_GMII_SPEED |
3053 MVPP2_GMAC_FC_ADV_EN |
3054 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3055 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3056 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3059 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3064 * Configure minimal level of the Tx FIFO before the lower part
3065 * starts to read a packet
3067 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3068 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3069 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3070 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3071 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3073 /* Disable bypass of sync module */
3074 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3075 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3076 /* configure DP clock select according to mode */
3077 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3078 /* configure QSGMII bypass according to mode */
3079 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3080 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3082 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3083 /* configure GIG MAC to SGMII mode */
3084 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3085 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3088 val = MVPP2_GMAC_EN_PCS_AN |
3089 MVPP2_GMAC_AN_BYPASS_EN |
3090 MVPP2_GMAC_AN_SPEED_EN |
3091 MVPP2_GMAC_EN_FC_AN |
3092 MVPP2_GMAC_AN_DUPLEX_EN |
3093 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3094 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3097 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3102 * Configure minimal level of the Tx FIFO before the lower part
3103 * starts to read a packet
3105 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3106 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3107 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3108 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3109 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3111 /* Disable bypass of sync module */
3112 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3113 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3114 /* configure DP clock select according to mode */
3115 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3116 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3117 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3118 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3120 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3121 /* configure GIG MAC to SGMII mode */
3122 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3123 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3125 /* configure AN 0xb8e8 */
3126 val = MVPP2_GMAC_AN_BYPASS_EN |
3127 MVPP2_GMAC_AN_SPEED_EN |
3128 MVPP2_GMAC_EN_FC_AN |
3129 MVPP2_GMAC_AN_DUPLEX_EN |
3130 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3131 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3134 /* Set the internal mux's to the required MAC in the GOP */
3135 static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3139 /* Set TX FIFO thresholds */
3140 switch (port->phy_interface) {
3141 case PHY_INTERFACE_MODE_SGMII:
3142 if (port->phy_speed == 2500)
3143 gop_gmac_sgmii2_5_cfg(port);
3145 gop_gmac_sgmii_cfg(port);
3148 case PHY_INTERFACE_MODE_RGMII:
3149 case PHY_INTERFACE_MODE_RGMII_ID:
3150 gop_gmac_rgmii_cfg(port);
3157 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3158 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3159 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3160 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3161 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3163 /* PeriodicXonEn disable */
3164 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3165 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3166 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3171 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3175 /* relevant only for MAC0 (XLG0 and GMAC0) */
3176 if (port->gop_id > 0)
3179 /* configure 1Gig MAC mode */
3180 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3181 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3182 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3183 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3186 static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3190 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3192 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3194 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3195 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3200 /* Set the internal mux's to the required PCS in the PI */
3201 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
3206 switch (num_of_lanes) {
3220 /* configure XG MAC mode */
3221 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3222 val &= ~MVPP22_XPCS_PCSMODE_MASK;
3223 val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
3224 val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
3225 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3230 static int gop_mpcs_mode(struct mvpp2_port *port)
3234 /* configure PCS40G COMMON CONTROL */
3235 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3236 val &= ~FORWARD_ERROR_CORRECTION_MASK;
3237 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3239 /* configure PCS CLOCK RESET */
3240 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
3241 val &= ~CLK_DIVISION_RATIO_MASK;
3242 val |= 1 << CLK_DIVISION_RATIO_OFFS;
3243 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3245 val &= ~CLK_DIV_PHASE_SET_MASK;
3246 val |= MAC_CLK_RESET_MASK;
3247 val |= RX_SD_CLK_RESET_MASK;
3248 val |= TX_SD_CLK_RESET_MASK;
3249 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3254 /* Set the internal mux's to the required MAC in the GOP */
3255 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3259 /* configure 10G MAC mode */
3260 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3261 val |= MVPP22_XLG_RX_FC_EN;
3262 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3264 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3265 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3266 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3267 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3269 /* read - modify - write */
3270 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3271 val &= ~MVPP22_XLG_MODE_DMA_1G;
3272 val |= MVPP22_XLG_FORWARD_PFC_EN;
3273 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3274 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3275 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3277 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3278 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3279 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3280 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3281 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3283 /* unmask link change interrupt */
3284 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3285 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3286 val |= 1; /* unmask summary bit */
3287 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3292 /* Set PCS to reset or exit from reset */
3293 static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
3297 /* read - modify - write */
3298 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3300 val &= ~MVPP22_XPCS_PCSRESET;
3302 val |= MVPP22_XPCS_PCSRESET;
3303 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3308 /* Set the MAC to reset or exit from reset */
3309 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3313 /* read - modify - write */
3314 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3316 val &= ~MVPP22_XLG_MAC_RESETN;
3318 val |= MVPP22_XLG_MAC_RESETN;
3319 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3327 * Init physical port. Configures the port mode and all it's elements
3329 * Does not verify that the selected mode/port number is valid at the
3332 static int gop_port_init(struct mvpp2_port *port)
3334 int mac_num = port->gop_id;
3335 int num_of_act_lanes;
3337 if (mac_num >= MVPP22_GOP_MAC_NUM) {
3338 netdev_err(NULL, "%s: illegal port number %d", __func__,
3343 switch (port->phy_interface) {
3344 case PHY_INTERFACE_MODE_RGMII:
3345 case PHY_INTERFACE_MODE_RGMII_ID:
3346 gop_gmac_reset(port, 1);
3349 gop_gpcs_mode_cfg(port, 0);
3350 gop_bypass_clk_cfg(port, 1);
3353 gop_gmac_mode_cfg(port);
3355 gop_gpcs_reset(port, 0);
3358 gop_gmac_reset(port, 0);
3361 case PHY_INTERFACE_MODE_SGMII:
3363 gop_gpcs_mode_cfg(port, 1);
3366 gop_gmac_mode_cfg(port);
3367 /* select proper Mac mode */
3368 gop_xlg_2_gig_mac_cfg(port);
3371 gop_gpcs_reset(port, 0);
3373 gop_gmac_reset(port, 0);
3376 case PHY_INTERFACE_MODE_SFI:
3377 num_of_act_lanes = 2;
3380 gop_xpcs_mode(port, num_of_act_lanes);
3381 gop_mpcs_mode(port);
3383 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3386 gop_xpcs_reset(port, 0);
3389 gop_xlg_mac_reset(port, 0);
3393 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
3394 __func__, port->phy_interface);
3401 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3405 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3407 /* Enable port and MIB counters update */
3408 val |= MVPP22_XLG_PORT_EN;
3409 val &= ~MVPP22_XLG_MIBCNT_DIS;
3412 val &= ~MVPP22_XLG_PORT_EN;
3414 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3417 static void gop_port_enable(struct mvpp2_port *port, int enable)
3419 switch (port->phy_interface) {
3420 case PHY_INTERFACE_MODE_RGMII:
3421 case PHY_INTERFACE_MODE_RGMII_ID:
3422 case PHY_INTERFACE_MODE_SGMII:
3424 mvpp2_port_enable(port);
3426 mvpp2_port_disable(port);
3429 case PHY_INTERFACE_MODE_SFI:
3430 gop_xlg_mac_port_enable(port, enable);
3434 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
3435 port->phy_interface);
3440 /* RFU1 functions */
3441 static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3443 return readl(priv->rfu1_base + offset);
3446 static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3448 writel(data, priv->rfu1_base + offset);
3451 static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3456 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3457 val |= MV_NETC_GE_MAC2_SGMII;
3461 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3462 val |= MV_NETC_GE_MAC3_SGMII;
3463 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3464 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3465 val |= MV_NETC_GE_MAC3_RGMII;
3471 static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3475 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3476 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3478 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3479 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3483 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3486 static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3490 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3491 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3493 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3494 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3498 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3501 static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3505 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3506 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3508 val <<= NETC_GOP_SOFT_RESET_OFFS;
3509 val &= NETC_GOP_SOFT_RESET_MASK;
3513 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3516 static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3520 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3521 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3523 val <<= NETC_CLK_DIV_PHASE_OFFS;
3524 val &= NETC_CLK_DIV_PHASE_MASK;
3528 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3531 static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3535 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3536 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3538 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3539 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3543 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3546 static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3549 u32 reg, mask, offset;
3552 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3553 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3555 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3556 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3558 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3566 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3569 static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3573 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3574 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3576 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3577 val &= NETC_BUS_WIDTH_SELECT_MASK;
3581 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3584 static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3588 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3589 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3591 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3592 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3596 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3599 static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3600 enum mv_netc_phase phase)
3603 case MV_NETC_FIRST_PHASE:
3604 /* Set Bus Width to HB mode = 1 */
3605 gop_netc_bus_width_select(priv, 1);
3606 /* Select RGMII mode */
3607 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3610 case MV_NETC_SECOND_PHASE:
3611 /* De-assert the relevant port HB reset */
3612 gop_netc_port_rf_reset(priv, gop_id, 1);
3617 static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3618 enum mv_netc_phase phase)
3621 case MV_NETC_FIRST_PHASE:
3622 /* Set Bus Width to HB mode = 1 */
3623 gop_netc_bus_width_select(priv, 1);
3624 /* Select SGMII mode */
3626 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3630 /* Configure the sample stages */
3631 gop_netc_sample_stages_timing(priv, 0);
3632 /* Configure the ComPhy Selector */
3633 /* gop_netc_com_phy_selector_config(netComplex); */
3636 case MV_NETC_SECOND_PHASE:
3637 /* De-assert the relevant port HB reset */
3638 gop_netc_port_rf_reset(priv, gop_id, 1);
3643 static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3645 u32 c = priv->netc_config;
3647 if (c & MV_NETC_GE_MAC2_SGMII)
3648 gop_netc_mac_to_sgmii(priv, 2, phase);
3650 gop_netc_mac_to_xgmii(priv, 2, phase);
3652 if (c & MV_NETC_GE_MAC3_SGMII) {
3653 gop_netc_mac_to_sgmii(priv, 3, phase);
3655 gop_netc_mac_to_xgmii(priv, 3, phase);
3656 if (c & MV_NETC_GE_MAC3_RGMII)
3657 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3659 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3662 /* Activate gop ports 0, 2, 3 */
3663 gop_netc_active_port(priv, 0, 1);
3664 gop_netc_active_port(priv, 2, 1);
3665 gop_netc_active_port(priv, 3, 1);
3667 if (phase == MV_NETC_SECOND_PHASE) {
3668 /* Enable the GOP internal clock logic */
3669 gop_netc_gop_clock_logic_set(priv, 1);
3670 /* De-assert GOP unit reset */
3671 gop_netc_gop_reset(priv, 1);
3677 /* Set defaults to the MVPP2 port */
3678 static void mvpp2_defaults_set(struct mvpp2_port *port)
3680 int tx_port_num, val, queue, ptxq, lrxq;
3682 if (port->priv->hw_version == MVPP21) {
3683 /* Configure port to loopback if needed */
3684 if (port->flags & MVPP2_F_LOOPBACK)
3685 mvpp2_port_loopback_set(port);
3687 /* Update TX FIFO MIN Threshold */
3688 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3689 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3690 /* Min. TX threshold must be less than minimal packet length */
3691 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3692 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3695 /* Disable Legacy WRR, Disable EJP, Release from reset */
3696 tx_port_num = mvpp2_egress_port(port);
3697 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3699 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3701 /* Close bandwidth for all queues */
3702 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3703 ptxq = mvpp2_txq_phys(port->id, queue);
3704 mvpp2_write(port->priv,
3705 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3708 /* Set refill period to 1 usec, refill tokens
3709 * and bucket size to maximum
3711 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3712 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3713 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3714 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3715 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3716 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3717 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3718 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3720 /* Set MaximumLowLatencyPacketSize value to 256 */
3721 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3722 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3723 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3725 /* Enable Rx cache snoop */
3726 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3727 queue = port->rxqs[lrxq]->id;
3728 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3729 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3730 MVPP2_SNOOP_BUF_HDR_MASK;
3731 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3735 /* Enable/disable receiving packets */
3736 static void mvpp2_ingress_enable(struct mvpp2_port *port)
3741 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3742 queue = port->rxqs[lrxq]->id;
3743 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3744 val &= ~MVPP2_RXQ_DISABLE_MASK;
3745 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3749 static void mvpp2_ingress_disable(struct mvpp2_port *port)
3754 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3755 queue = port->rxqs[lrxq]->id;
3756 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3757 val |= MVPP2_RXQ_DISABLE_MASK;
3758 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3762 /* Enable transmit via physical egress queue
3763 * - HW starts take descriptors from DRAM
3765 static void mvpp2_egress_enable(struct mvpp2_port *port)
3769 int tx_port_num = mvpp2_egress_port(port);
3771 /* Enable all initialized TXs. */
3773 for (queue = 0; queue < txq_number; queue++) {
3774 struct mvpp2_tx_queue *txq = port->txqs[queue];
3776 if (txq->descs != NULL)
3777 qmap |= (1 << queue);
3780 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3781 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3784 /* Disable transmit via physical egress queue
3785 * - HW doesn't take descriptors from DRAM
3787 static void mvpp2_egress_disable(struct mvpp2_port *port)
3791 int tx_port_num = mvpp2_egress_port(port);
3793 /* Issue stop command for active channels only */
3794 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3795 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3796 MVPP2_TXP_SCHED_ENQ_MASK;
3798 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3799 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3801 /* Wait for all Tx activity to terminate. */
3804 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
3805 netdev_warn(port->dev,
3806 "Tx stop timed out, status=0x%08x\n",
3813 /* Check port TX Command register that all
3814 * Tx queues are stopped
3816 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3817 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3820 /* Rx descriptors helper methods */
3822 /* Get number of Rx descriptors occupied by received packets */
3824 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3826 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3828 return val & MVPP2_RXQ_OCCUPIED_MASK;
3831 /* Update Rx queue status with the number of occupied and available
3832 * Rx descriptor slots.
3835 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3836 int used_count, int free_count)
3838 /* Decrement the number of used descriptors and increment count
3839 * increment the number of free descriptors.
3841 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3843 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3846 /* Get pointer to next RX descriptor to be processed by SW */
3847 static inline struct mvpp2_rx_desc *
3848 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3850 int rx_desc = rxq->next_desc_to_proc;
3852 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3853 prefetch(rxq->descs + rxq->next_desc_to_proc);
3854 return rxq->descs + rx_desc;
3857 /* Set rx queue offset */
3858 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3859 int prxq, int offset)
3863 /* Convert offset from bytes to units of 32 bytes */
3864 offset = offset >> 5;
3866 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3867 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3870 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3871 MVPP2_RXQ_PACKET_OFFSET_MASK);
3873 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3876 /* Obtain BM cookie information from descriptor */
3877 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3878 struct mvpp2_rx_desc *rx_desc)
3880 int cpu = smp_processor_id();
3883 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3884 MVPP2_RXD_BM_POOL_ID_MASK) >>
3885 MVPP2_RXD_BM_POOL_ID_OFFS;
3887 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3888 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3891 /* Tx descriptors helper methods */
3893 /* Get number of Tx descriptors waiting to be transmitted by HW */
3894 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3895 struct mvpp2_tx_queue *txq)
3899 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3900 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3902 return val & MVPP2_TXQ_PENDING_MASK;
3905 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3906 static struct mvpp2_tx_desc *
3907 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3909 int tx_desc = txq->next_desc_to_proc;
3911 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3912 return txq->descs + tx_desc;
3915 /* Update HW with number of aggregated Tx descriptors to be sent */
3916 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3918 /* aggregated access - relevant TXQ number is written in TX desc */
3919 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3922 /* Get number of sent descriptors and decrement counter.
3923 * The number of sent descriptors is returned.
3926 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3927 struct mvpp2_tx_queue *txq)
3931 /* Reading status reg resets transmitted descriptor counter */
3932 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3934 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3935 MVPP2_TRANSMITTED_COUNT_OFFSET;
3938 static void mvpp2_txq_sent_counter_clear(void *arg)
3940 struct mvpp2_port *port = arg;
3943 for (queue = 0; queue < txq_number; queue++) {
3944 int id = port->txqs[queue]->id;
3946 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3950 /* Set max sizes for Tx queues */
3951 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3954 int txq, tx_port_num;
3956 mtu = port->pkt_size * 8;
3957 if (mtu > MVPP2_TXP_MTU_MAX)
3958 mtu = MVPP2_TXP_MTU_MAX;
3960 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3963 /* Indirect access to registers */
3964 tx_port_num = mvpp2_egress_port(port);
3965 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3968 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3969 val &= ~MVPP2_TXP_MTU_MAX;
3971 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3973 /* TXP token size and all TXQs token size must be larger that MTU */
3974 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3975 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3978 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3980 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3983 for (txq = 0; txq < txq_number; txq++) {
3984 val = mvpp2_read(port->priv,
3985 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3986 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3990 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3992 mvpp2_write(port->priv,
3993 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
3999 /* Free Tx queue skbuffs */
4000 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4001 struct mvpp2_tx_queue *txq,
4002 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4006 for (i = 0; i < num; i++)
4007 mvpp2_txq_inc_get(txq_pcpu);
4010 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4013 int queue = fls(cause) - 1;
4015 return port->rxqs[queue];
4018 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4021 int queue = fls(cause) - 1;
4023 return port->txqs[queue];
4026 /* Rx/Tx queue initialization/cleanup methods */
4028 /* Allocate and initialize descriptors for aggr TXQ */
4029 static int mvpp2_aggr_txq_init(struct udevice *dev,
4030 struct mvpp2_tx_queue *aggr_txq,
4031 int desc_num, int cpu,
4036 /* Allocate memory for TX descriptors */
4037 aggr_txq->descs = buffer_loc.aggr_tx_descs;
4038 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
4039 if (!aggr_txq->descs)
4042 /* Make sure descriptor address is cache line size aligned */
4043 BUG_ON(aggr_txq->descs !=
4044 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4046 aggr_txq->last_desc = aggr_txq->size - 1;
4048 /* Aggr TXQ no reset WA */
4049 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4050 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4052 /* Set Tx descriptors queue starting address indirect
4055 if (priv->hw_version == MVPP21)
4056 txq_dma = aggr_txq->descs_dma;
4058 txq_dma = aggr_txq->descs_dma >>
4059 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4061 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
4062 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4067 /* Create a specified Rx queue */
4068 static int mvpp2_rxq_init(struct mvpp2_port *port,
4069 struct mvpp2_rx_queue *rxq)
4074 rxq->size = port->rx_ring_size;
4076 /* Allocate memory for RX descriptors */
4077 rxq->descs = buffer_loc.rx_descs;
4078 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
4082 BUG_ON(rxq->descs !=
4083 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4085 rxq->last_desc = rxq->size - 1;
4087 /* Zero occupied and non-occupied counters - direct access */
4088 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4090 /* Set Rx descriptors queue starting address - indirect access */
4091 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4092 if (port->priv->hw_version == MVPP21)
4093 rxq_dma = rxq->descs_dma;
4095 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4096 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
4097 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4098 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4101 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4103 /* Add number of descriptors ready for receiving packets */
4104 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4109 /* Push packets received by the RXQ to BM pool */
4110 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4111 struct mvpp2_rx_queue *rxq)
4115 rx_received = mvpp2_rxq_received(port, rxq->id);
4119 for (i = 0; i < rx_received; i++) {
4120 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4121 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
4123 mvpp2_pool_refill(port, bm,
4124 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4125 mvpp2_rxdesc_cookie_get(port, rx_desc));
4127 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4130 /* Cleanup Rx queue */
4131 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4132 struct mvpp2_rx_queue *rxq)
4134 mvpp2_rxq_drop_pkts(port, rxq);
4138 rxq->next_desc_to_proc = 0;
4141 /* Clear Rx descriptors queue starting address and size;
4142 * free descriptor number
4144 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4145 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4146 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4147 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4150 /* Create and initialize a Tx queue */
4151 static int mvpp2_txq_init(struct mvpp2_port *port,
4152 struct mvpp2_tx_queue *txq)
4155 int cpu, desc, desc_per_txq, tx_port_num;
4156 struct mvpp2_txq_pcpu *txq_pcpu;
4158 txq->size = port->tx_ring_size;
4160 /* Allocate memory for Tx descriptors */
4161 txq->descs = buffer_loc.tx_descs;
4162 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
4166 /* Make sure descriptor address is cache line size aligned */
4167 BUG_ON(txq->descs !=
4168 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4170 txq->last_desc = txq->size - 1;
4172 /* Set Tx descriptors queue starting address - indirect access */
4173 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4174 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
4175 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4176 MVPP2_TXQ_DESC_SIZE_MASK);
4177 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4178 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4179 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4180 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4181 val &= ~MVPP2_TXQ_PENDING_MASK;
4182 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4184 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4185 * for each existing TXQ.
4186 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4187 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4190 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4191 (txq->log_id * desc_per_txq);
4193 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4194 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4195 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
4197 /* WRR / EJP configuration - indirect access */
4198 tx_port_num = mvpp2_egress_port(port);
4199 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4201 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4202 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4203 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4204 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4205 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4207 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4208 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4211 for_each_present_cpu(cpu) {
4212 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4213 txq_pcpu->size = txq->size;
4219 /* Free allocated TXQ resources */
4220 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4221 struct mvpp2_tx_queue *txq)
4225 txq->next_desc_to_proc = 0;
4228 /* Set minimum bandwidth for disabled TXQs */
4229 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4231 /* Set Tx descriptors queue starting address and size */
4232 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4233 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4234 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4237 /* Cleanup Tx ports */
4238 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4240 struct mvpp2_txq_pcpu *txq_pcpu;
4241 int delay, pending, cpu;
4244 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4245 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4246 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4247 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4249 /* The napi queue has been stopped so wait for all packets
4250 * to be transmitted.
4254 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4255 netdev_warn(port->dev,
4256 "port %d: cleaning queue %d timed out\n",
4257 port->id, txq->log_id);
4263 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4266 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4267 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4269 for_each_present_cpu(cpu) {
4270 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4272 /* Release all packets */
4273 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4276 txq_pcpu->count = 0;
4277 txq_pcpu->txq_put_index = 0;
4278 txq_pcpu->txq_get_index = 0;
4282 /* Cleanup all Tx queues */
4283 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4285 struct mvpp2_tx_queue *txq;
4289 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4291 /* Reset Tx ports and delete Tx queues */
4292 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4293 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4295 for (queue = 0; queue < txq_number; queue++) {
4296 txq = port->txqs[queue];
4297 mvpp2_txq_clean(port, txq);
4298 mvpp2_txq_deinit(port, txq);
4301 mvpp2_txq_sent_counter_clear(port);
4303 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4304 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4307 /* Cleanup all Rx queues */
4308 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4312 for (queue = 0; queue < rxq_number; queue++)
4313 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4316 /* Init all Rx queues for port */
4317 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4321 for (queue = 0; queue < rxq_number; queue++) {
4322 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4329 mvpp2_cleanup_rxqs(port);
4333 /* Init all tx queues for port */
4334 static int mvpp2_setup_txqs(struct mvpp2_port *port)
4336 struct mvpp2_tx_queue *txq;
4339 for (queue = 0; queue < txq_number; queue++) {
4340 txq = port->txqs[queue];
4341 err = mvpp2_txq_init(port, txq);
4346 mvpp2_txq_sent_counter_clear(port);
4350 mvpp2_cleanup_txqs(port);
4355 static void mvpp2_link_event(struct mvpp2_port *port)
4357 struct phy_device *phydev = port->phy_dev;
4358 int status_change = 0;
4362 if ((port->speed != phydev->speed) ||
4363 (port->duplex != phydev->duplex)) {
4366 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4367 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4368 MVPP2_GMAC_CONFIG_GMII_SPEED |
4369 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4370 MVPP2_GMAC_AN_SPEED_EN |
4371 MVPP2_GMAC_AN_DUPLEX_EN);
4374 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4376 if (phydev->speed == SPEED_1000)
4377 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4378 else if (phydev->speed == SPEED_100)
4379 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4381 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4383 port->duplex = phydev->duplex;
4384 port->speed = phydev->speed;
4388 if (phydev->link != port->link) {
4389 if (!phydev->link) {
4394 port->link = phydev->link;
4398 if (status_change) {
4400 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4401 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4402 MVPP2_GMAC_FORCE_LINK_DOWN);
4403 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4404 mvpp2_egress_enable(port);
4405 mvpp2_ingress_enable(port);
4407 mvpp2_ingress_disable(port);
4408 mvpp2_egress_disable(port);
4413 /* Main RX/TX processing routines */
4415 /* Display more error info */
4416 static void mvpp2_rx_error(struct mvpp2_port *port,
4417 struct mvpp2_rx_desc *rx_desc)
4419 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4420 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
4422 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4423 case MVPP2_RXD_ERR_CRC:
4424 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
4427 case MVPP2_RXD_ERR_OVERRUN:
4428 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
4431 case MVPP2_RXD_ERR_RESOURCE:
4432 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
4438 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4439 static int mvpp2_rx_refill(struct mvpp2_port *port,
4440 struct mvpp2_bm_pool *bm_pool,
4441 u32 bm, dma_addr_t dma_addr)
4443 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
4447 /* Set hw internals when starting port */
4448 static void mvpp2_start_dev(struct mvpp2_port *port)
4450 switch (port->phy_interface) {
4451 case PHY_INTERFACE_MODE_RGMII:
4452 case PHY_INTERFACE_MODE_RGMII_ID:
4453 case PHY_INTERFACE_MODE_SGMII:
4454 mvpp2_gmac_max_rx_size_set(port);
4459 mvpp2_txp_max_tx_size_set(port);
4461 if (port->priv->hw_version == MVPP21)
4462 mvpp2_port_enable(port);
4464 gop_port_enable(port, 1);
4467 /* Set hw internals when stopping port */
4468 static void mvpp2_stop_dev(struct mvpp2_port *port)
4470 /* Stop new packets from arriving to RXQs */
4471 mvpp2_ingress_disable(port);
4473 mvpp2_egress_disable(port);
4475 if (port->priv->hw_version == MVPP21)
4476 mvpp2_port_disable(port);
4478 gop_port_enable(port, 0);
4481 static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
4483 struct phy_device *phy_dev;
4485 if (!port->init || port->link == 0) {
4486 phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
4487 dev, port->phy_interface);
4490 * If the phy doesn't match with any existing u-boot drivers the
4491 * phy framework will connect it to generic one which
4492 * uid == 0xffffffff. In this case act as if the phy wouldn't be
4493 * declared in dts. Otherwise in case of 3310 (for which the
4494 * driver doesn't exist) the link will not be correctly
4495 * detected. Removing phy entry from dts in case of 3310 is not
4496 * an option because it is required for the phy_fw_down
4500 phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
4501 netdev_warn(port->dev,
4502 "Marking phy as invalid, link will not be checked\n");
4503 /* set phy_addr to invalid value */
4504 port->phyaddr = PHY_MAX_ADDR;
4505 mvpp2_egress_enable(port);
4506 mvpp2_ingress_enable(port);
4511 port->phy_dev = phy_dev;
4513 netdev_err(port->dev, "cannot connect to phy\n");
4516 phy_dev->supported &= PHY_GBIT_FEATURES;
4517 phy_dev->advertising = phy_dev->supported;
4519 port->phy_dev = phy_dev;
4524 phy_config(phy_dev);
4525 phy_startup(phy_dev);
4527 printf("%s: No link\n", phy_dev->dev->name);
4531 mvpp2_egress_enable(port);
4532 mvpp2_ingress_enable(port);
4536 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4538 unsigned char mac_bcast[ETH_ALEN] = {
4539 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4542 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4544 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4547 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4548 port->dev_addr, true);
4550 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
4553 err = mvpp2_prs_def_flow(port);
4555 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4559 /* Allocate the Rx/Tx queues */
4560 err = mvpp2_setup_rxqs(port);
4562 netdev_err(port->dev, "cannot allocate Rx queues\n");
4566 err = mvpp2_setup_txqs(port);
4568 netdev_err(port->dev, "cannot allocate Tx queues\n");
4572 if (port->phyaddr < PHY_MAX_ADDR) {
4573 mvpp2_phy_connect(dev, port);
4574 mvpp2_link_event(port);
4576 mvpp2_egress_enable(port);
4577 mvpp2_ingress_enable(port);
4580 mvpp2_start_dev(port);
4585 /* No Device ops here in U-Boot */
4587 /* Driver initialization */
4589 static void mvpp2_port_power_up(struct mvpp2_port *port)
4591 struct mvpp2 *priv = port->priv;
4593 /* On PPv2.2 the GoP / interface configuration has already been done */
4594 if (priv->hw_version == MVPP21)
4595 mvpp2_port_mii_set(port);
4596 mvpp2_port_periodic_xon_disable(port);
4597 if (priv->hw_version == MVPP21)
4598 mvpp2_port_fc_adv_enable(port);
4599 mvpp2_port_reset(port);
4602 /* Initialize port HW */
4603 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4605 struct mvpp2 *priv = port->priv;
4606 struct mvpp2_txq_pcpu *txq_pcpu;
4607 int queue, cpu, err;
4609 if (port->first_rxq + rxq_number >
4610 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4614 mvpp2_egress_disable(port);
4615 if (priv->hw_version == MVPP21)
4616 mvpp2_port_disable(port);
4618 gop_port_enable(port, 0);
4620 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4625 /* Associate physical Tx queues to this port and initialize.
4626 * The mapping is predefined.
4628 for (queue = 0; queue < txq_number; queue++) {
4629 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4630 struct mvpp2_tx_queue *txq;
4632 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4636 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4641 txq->id = queue_phy_id;
4642 txq->log_id = queue;
4643 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4644 for_each_present_cpu(cpu) {
4645 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4646 txq_pcpu->cpu = cpu;
4649 port->txqs[queue] = txq;
4652 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4657 /* Allocate and initialize Rx queue for this port */
4658 for (queue = 0; queue < rxq_number; queue++) {
4659 struct mvpp2_rx_queue *rxq;
4661 /* Map physical Rx queue to port's logical Rx queue */
4662 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4665 /* Map this Rx queue to a physical queue */
4666 rxq->id = port->first_rxq + queue;
4667 rxq->port = port->id;
4668 rxq->logic_rxq = queue;
4670 port->rxqs[queue] = rxq;
4674 /* Create Rx descriptor rings */
4675 for (queue = 0; queue < rxq_number; queue++) {
4676 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4678 rxq->size = port->rx_ring_size;
4679 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4680 rxq->time_coal = MVPP2_RX_COAL_USEC;
4683 mvpp2_ingress_disable(port);
4685 /* Port default configuration */
4686 mvpp2_defaults_set(port);
4688 /* Port's classifier configuration */
4689 mvpp2_cls_oversize_rxq_set(port);
4690 mvpp2_cls_port_config(port);
4692 /* Provide an initial Rx packet size */
4693 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4695 /* Initialize pools for swf */
4696 err = mvpp2_swf_bm_pool_init(port);
4703 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
4705 int port_node = dev_of_offset(dev);
4706 const char *phy_mode_str;
4713 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
4717 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
4719 dev_err(&pdev->dev, "could not find phy address\n");
4722 parent = fdt_parent_offset(gd->fdt_blob, phy_node);
4723 ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
4728 /* phy_addr is set to invalid value */
4729 phyaddr = PHY_MAX_ADDR;
4732 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
4734 phy_mode = phy_get_interface_by_name(phy_mode_str);
4735 if (phy_mode == -1) {
4736 dev_err(&pdev->dev, "incorrect phy mode\n");
4740 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4742 dev_err(&pdev->dev, "missing port-id value\n");
4746 #if CONFIG_IS_ENABLED(DM_GPIO)
4747 gpio_request_by_name(dev, "phy-reset-gpios", 0,
4748 &port->phy_reset_gpio, GPIOD_IS_OUT);
4749 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
4750 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
4755 * Not sure if this DT property "phy-speed" will get accepted, so
4756 * this might change later
4758 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
4759 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
4763 if (port->priv->hw_version == MVPP21)
4764 port->first_rxq = port->id * rxq_number;
4766 port->first_rxq = port->id * port->priv->max_port_rxqs;
4767 port->phy_interface = phy_mode;
4768 port->phyaddr = phyaddr;
4773 #if CONFIG_IS_ENABLED(DM_GPIO)
4774 /* Port GPIO initialization */
4775 static void mvpp2_gpio_init(struct mvpp2_port *port)
4777 if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
4778 dm_gpio_set_value(&port->phy_reset_gpio, 1);
4780 dm_gpio_set_value(&port->phy_reset_gpio, 0);
4783 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
4784 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
4788 /* Ports initialization */
4789 static int mvpp2_port_probe(struct udevice *dev,
4790 struct mvpp2_port *port,
4796 port->tx_ring_size = MVPP2_MAX_TXD;
4797 port->rx_ring_size = MVPP2_MAX_RXD;
4799 err = mvpp2_port_init(dev, port);
4801 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
4804 mvpp2_port_power_up(port);
4806 #if CONFIG_IS_ENABLED(DM_GPIO)
4807 mvpp2_gpio_init(port);
4810 priv->port_list[port->id] = port;
4815 /* Initialize decoding windows */
4816 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4822 for (i = 0; i < 6; i++) {
4823 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4824 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4827 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4832 for (i = 0; i < dram->num_cs; i++) {
4833 const struct mbus_dram_window *cs = dram->cs + i;
4835 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4836 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4837 dram->mbus_dram_target_id);
4839 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4840 (cs->size - 1) & 0xffff0000);
4842 win_enable |= (1 << i);
4845 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4848 /* Initialize Rx FIFO's */
4849 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4853 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4854 if (priv->hw_version == MVPP22) {
4857 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4858 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4860 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4861 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4862 } else if (port == 1) {
4864 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4865 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4867 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4868 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4871 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4872 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4874 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4875 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4878 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4879 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4880 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4881 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4885 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4886 MVPP2_RX_FIFO_PORT_MIN_PKT);
4887 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4890 /* Initialize Tx FIFO's */
4891 static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4895 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4896 /* Port 0 supports 10KB TX FIFO */
4898 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4899 MVPP22_TX_FIFO_SIZE_MASK;
4901 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4902 MVPP22_TX_FIFO_SIZE_MASK;
4904 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4908 static void mvpp2_axi_init(struct mvpp2 *priv)
4910 u32 val, rdval, wrval;
4912 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4914 /* AXI Bridge Configuration */
4916 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4917 << MVPP22_AXI_ATTR_CACHE_OFFS;
4918 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4919 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4921 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4922 << MVPP22_AXI_ATTR_CACHE_OFFS;
4923 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4924 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4927 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4928 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4931 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4932 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4933 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4934 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4937 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4938 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4940 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4941 << MVPP22_AXI_CODE_CACHE_OFFS;
4942 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4943 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4944 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4945 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4947 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4948 << MVPP22_AXI_CODE_CACHE_OFFS;
4949 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4950 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4952 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4954 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4955 << MVPP22_AXI_CODE_CACHE_OFFS;
4956 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4957 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4959 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
4962 /* Initialize network controller common part HW */
4963 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
4965 const struct mbus_dram_target_info *dram_target_info;
4969 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4970 if ((rxq_number > priv->max_port_rxqs) ||
4971 (txq_number > MVPP2_MAX_TXQ)) {
4972 dev_err(&pdev->dev, "invalid queue size parameter\n");
4976 if (priv->hw_version == MVPP22)
4977 mvpp2_axi_init(priv);
4979 /* MBUS windows configuration */
4980 dram_target_info = mvebu_mbus_dram_info();
4981 if (dram_target_info)
4982 mvpp2_conf_mbus_windows(dram_target_info, priv);
4985 if (priv->hw_version == MVPP21) {
4986 /* Disable HW PHY polling */
4987 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4988 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4989 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4991 /* Enable HW PHY polling */
4992 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4993 val |= MVPP22_SMI_POLLING_EN;
4994 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4997 /* Allocate and initialize aggregated TXQs */
4998 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
4999 sizeof(struct mvpp2_tx_queue),
5001 if (!priv->aggr_txqs)
5004 for_each_present_cpu(i) {
5005 priv->aggr_txqs[i].id = i;
5006 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5007 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5008 MVPP2_AGGR_TXQ_SIZE, i, priv);
5014 mvpp2_rx_fifo_init(priv);
5017 if (priv->hw_version == MVPP22)
5018 mvpp2_tx_fifo_init(priv);
5020 if (priv->hw_version == MVPP21)
5021 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5022 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5024 /* Allow cache snoop when transmiting packets */
5025 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5027 /* Buffer Manager initialization */
5028 err = mvpp2_bm_init(dev, priv);
5032 /* Parser default initialization */
5033 err = mvpp2_prs_default_init(dev, priv);
5037 /* Classifier default initialization */
5038 mvpp2_cls_init(priv);
5043 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5045 struct mvpp2_port *port = dev_get_priv(dev);
5046 struct mvpp2_rx_desc *rx_desc;
5047 struct mvpp2_bm_pool *bm_pool;
5048 dma_addr_t dma_addr;
5050 int pool, rx_bytes, err;
5052 struct mvpp2_rx_queue *rxq;
5055 if (port->phyaddr < PHY_MAX_ADDR)
5056 if (!port->phy_dev->link)
5059 /* Process RX packets */
5060 rxq = port->rxqs[0];
5062 /* Get number of received packets and clamp the to-do */
5063 rx_received = mvpp2_rxq_received(port, rxq->id);
5065 /* Return if no packets are received */
5069 rx_desc = mvpp2_rxq_next_desc_get(rxq);
5070 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5071 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5072 rx_bytes -= MVPP2_MH_SIZE;
5073 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
5075 bm = mvpp2_bm_cookie_build(port, rx_desc);
5076 pool = mvpp2_bm_cookie_pool_get(bm);
5077 bm_pool = &port->priv->bm_pools[pool];
5079 /* In case of an error, release the requested buffer pointer
5080 * to the Buffer Manager. This request process is controlled
5081 * by the hardware, and the information about the buffer is
5082 * comprised by the RX descriptor.
5084 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5085 mvpp2_rx_error(port, rx_desc);
5086 /* Return the buffer to the pool */
5087 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
5091 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
5093 netdev_err(port->dev, "failed to refill BM pools\n");
5097 /* Update Rx queue management counters */
5099 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5101 /* give packet to stack - skip on first n bytes */
5102 data = (u8 *)dma_addr + 2 + 32;
5108 * No cache invalidation needed here, since the rx_buffer's are
5109 * located in a uncached memory region
5116 static int mvpp2_send(struct udevice *dev, void *packet, int length)
5118 struct mvpp2_port *port = dev_get_priv(dev);
5119 struct mvpp2_tx_queue *txq, *aggr_txq;
5120 struct mvpp2_tx_desc *tx_desc;
5124 if (port->phyaddr < PHY_MAX_ADDR)
5125 if (!port->phy_dev->link)
5128 txq = port->txqs[0];
5129 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5131 /* Get a descriptor for the first part of the packet */
5132 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5133 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5134 mvpp2_txdesc_size_set(port, tx_desc, length);
5135 mvpp2_txdesc_offset_set(port, tx_desc,
5136 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5137 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5138 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
5139 /* First and Last descriptor */
5140 mvpp2_txdesc_cmd_set(port, tx_desc,
5141 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5142 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
5145 flush_dcache_range((unsigned long)packet,
5146 (unsigned long)packet + ALIGN(length, PKTALIGN));
5148 /* Enable transmit */
5150 mvpp2_aggr_txq_pend_desc_add(port, 1);
5152 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5156 if (timeout++ > 10000) {
5157 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5160 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5165 if (timeout++ > 10000) {
5166 printf("timeout: packet not sent\n");
5169 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5175 static int mvpp2_start(struct udevice *dev)
5177 struct eth_pdata *pdata = dev_get_platdata(dev);
5178 struct mvpp2_port *port = dev_get_priv(dev);
5180 /* Load current MAC address */
5181 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5183 /* Reconfigure parser accept the original MAC address */
5184 mvpp2_prs_update_mac_da(port, port->dev_addr);
5186 switch (port->phy_interface) {
5187 case PHY_INTERFACE_MODE_RGMII:
5188 case PHY_INTERFACE_MODE_RGMII_ID:
5189 case PHY_INTERFACE_MODE_SGMII:
5190 mvpp2_port_power_up(port);
5195 mvpp2_open(dev, port);
5200 static void mvpp2_stop(struct udevice *dev)
5202 struct mvpp2_port *port = dev_get_priv(dev);
5204 mvpp2_stop_dev(port);
5205 mvpp2_cleanup_rxqs(port);
5206 mvpp2_cleanup_txqs(port);
5209 static int mvpp2_write_hwaddr(struct udevice *dev)
5211 struct mvpp2_port *port = dev_get_priv(dev);
5213 return mvpp2_prs_update_mac_da(port, port->dev_addr);
5216 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
5218 writel(port->phyaddr, port->priv->iface_base +
5219 MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
5224 static int mvpp2_base_probe(struct udevice *dev)
5226 struct mvpp2 *priv = dev_get_priv(dev);
5231 /* Save hw-version */
5232 priv->hw_version = dev_get_driver_data(dev);
5235 * U-Boot special buffer handling:
5237 * Allocate buffer area for descs and rx_buffers. This is only
5238 * done once for all interfaces. As only one interface can
5239 * be active. Make this area DMA-safe by disabling the D-cache
5242 /* Align buffer area for descs and rx_buffers to 1MiB */
5243 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
5244 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5245 BD_SPACE, DCACHE_OFF);
5247 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5248 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
5250 buffer_loc.tx_descs =
5251 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
5252 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
5254 buffer_loc.rx_descs =
5255 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
5256 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
5258 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5259 buffer_loc.bm_pool[i] =
5260 (unsigned long *)((unsigned long)bd_space + size);
5261 if (priv->hw_version == MVPP21)
5262 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5264 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
5267 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
5268 buffer_loc.rx_buffer[i] =
5269 (unsigned long *)((unsigned long)bd_space + size);
5270 size += RX_BUFFER_SIZE;
5273 /* Clear the complete area so that all descriptors are cleared */
5274 memset(bd_space, 0, size);
5276 /* Save base addresses for later use */
5277 priv->base = (void *)devfdt_get_addr_index(dev, 0);
5278 if (IS_ERR(priv->base))
5279 return PTR_ERR(priv->base);
5281 if (priv->hw_version == MVPP21) {
5282 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
5283 if (IS_ERR(priv->lms_base))
5284 return PTR_ERR(priv->lms_base);
5286 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
5287 if (IS_ERR(priv->iface_base))
5288 return PTR_ERR(priv->iface_base);
5290 /* Store common base addresses for all ports */
5291 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5292 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5293 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
5296 if (priv->hw_version == MVPP21)
5297 priv->max_port_rxqs = 8;
5299 priv->max_port_rxqs = 32;
5304 static int mvpp2_probe(struct udevice *dev)
5306 struct mvpp2_port *port = dev_get_priv(dev);
5307 struct mvpp2 *priv = dev_get_priv(dev->parent);
5310 /* Only call the probe function for the parent once */
5311 if (!priv->probe_done)
5312 err = mvpp2_base_probe(dev->parent);
5316 err = phy_info_parse(dev, port);
5321 * We need the port specific io base addresses at this stage, since
5322 * gop_port_init() accesses these registers
5324 if (priv->hw_version == MVPP21) {
5325 int priv_common_regs_num = 2;
5327 port->base = (void __iomem *)devfdt_get_addr_index(
5328 dev->parent, priv_common_regs_num + port->id);
5329 if (IS_ERR(port->base))
5330 return PTR_ERR(port->base);
5332 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5334 if (port->id == -1) {
5335 dev_err(&pdev->dev, "missing gop-port-id value\n");
5339 port->base = priv->iface_base + MVPP22_PORT_BASE +
5340 port->gop_id * MVPP22_PORT_OFFSET;
5342 /* Set phy address of the port */
5343 if (port->phyaddr < PHY_MAX_ADDR)
5344 mvpp22_smi_phy_addr_cfg(port);
5347 gop_port_init(port);
5350 if (!priv->probe_done) {
5351 /* Initialize network controller */
5352 err = mvpp2_init(dev, priv);
5354 dev_err(&pdev->dev, "failed to initialize controller\n");
5357 priv->num_ports = 0;
5358 priv->probe_done = 1;
5361 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5365 if (priv->hw_version == MVPP22) {
5366 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5367 port->phy_interface);
5369 /* Netcomplex configurations for all ports */
5370 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5371 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5378 * Empty BM pool and stop its activity before the OS is started
5380 static int mvpp2_remove(struct udevice *dev)
5382 struct mvpp2_port *port = dev_get_priv(dev);
5383 struct mvpp2 *priv = port->priv;
5388 if (priv->num_ports)
5391 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5392 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5397 static const struct eth_ops mvpp2_ops = {
5398 .start = mvpp2_start,
5402 .write_hwaddr = mvpp2_write_hwaddr
5405 static struct driver mvpp2_driver = {
5408 .probe = mvpp2_probe,
5409 .remove = mvpp2_remove,
5411 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
5412 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5413 .flags = DM_FLAG_ACTIVE_DMA,
5417 * Use a MISC device to bind the n instances (child nodes) of the
5418 * network base controller in UCLASS_ETH.
5420 static int mvpp2_base_bind(struct udevice *parent)
5422 const void *blob = gd->fdt_blob;
5423 int node = dev_of_offset(parent);
5424 struct uclass_driver *drv;
5425 struct udevice *dev;
5426 struct eth_pdata *plat;
5432 /* Lookup eth driver */
5433 drv = lists_uclass_lookup(UCLASS_ETH);
5435 puts("Cannot find eth driver\n");
5439 base_id_add = base_id;
5441 fdt_for_each_subnode(subnode, blob, node) {
5442 /* Increment base_id for all subnodes, also the disabled ones */
5445 /* Skip disabled ports */
5446 if (!fdtdec_get_is_enabled(blob, subnode))
5449 plat = calloc(1, sizeof(*plat));
5453 id = fdtdec_get_int(blob, subnode, "port-id", -1);
5456 name = calloc(1, 16);
5461 sprintf(name, "mvpp2-%d", id);
5463 /* Create child device UCLASS_ETH and bind it */
5464 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
5465 dev_set_of_offset(dev, subnode);
5471 static const struct udevice_id mvpp2_ids[] = {
5473 .compatible = "marvell,armada-375-pp2",
5477 .compatible = "marvell,armada-7k-pp22",
5483 U_BOOT_DRIVER(mvpp2_base) = {
5484 .name = "mvpp2_base",
5486 .of_match = mvpp2_ids,
5487 .bind = mvpp2_base_bind,
5488 .priv_auto_alloc_size = sizeof(struct mvpp2),