2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
19 #include <dm/device-internal.h>
20 #include <dm/device_compat.h>
21 #include <dm/devres.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/soc.h>
35 #include <linux/compat.h>
36 #include <linux/mbus.h>
37 #include <asm-generic/gpio.h>
38 #include <fdt_support.h>
39 #include <linux/mdio.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #define __verify_pcpu_ptr(ptr) \
45 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
49 #define VERIFY_PERCPU_PTR(__p) \
51 __verify_pcpu_ptr(__p); \
52 (typeof(*(__p)) __kernel __force *)(__p); \
55 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
56 #define smp_processor_id() 0
57 #define num_present_cpus() 1
58 #define for_each_present_cpu(cpu) \
59 for ((cpu) = 0; (cpu) < 1; (cpu)++)
61 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
63 #define CONFIG_NR_CPUS 1
65 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
66 #define WRAP (2 + ETH_HLEN + 4 + 32)
68 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
70 /* RX Fifo Registers */
71 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
72 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
73 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
74 #define MVPP2_RX_FIFO_INIT_REG 0x64
76 /* RX DMA Top Registers */
77 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
78 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
79 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
80 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
81 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
82 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
83 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
84 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
85 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
86 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
87 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
88 #define MVPP2_RXQ_POOL_LONG_OFFS 24
89 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
90 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
91 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
92 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
93 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
95 /* Parser Registers */
96 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
97 #define MVPP2_PRS_PORT_LU_MAX 0xf
98 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
99 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
100 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
101 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
102 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
103 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
104 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
105 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
106 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
107 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
108 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
109 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
110 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
111 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
112 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
114 /* Classifier Registers */
115 #define MVPP2_CLS_MODE_REG 0x1800
116 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
117 #define MVPP2_CLS_PORT_WAY_REG 0x1810
118 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
119 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
120 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
121 #define MVPP2_CLS_LKP_TBL_REG 0x1818
122 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
123 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
124 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
125 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
126 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
127 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
128 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
129 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
130 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
131 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
132 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
133 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
135 /* Descriptor Manager Top Registers */
136 #define MVPP2_RXQ_NUM_REG 0x2040
137 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
138 #define MVPP22_DESC_ADDR_OFFS 8
139 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
140 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
141 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
142 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
143 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
144 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
145 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
146 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
147 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
148 #define MVPP2_RXQ_THRESH_REG 0x204c
149 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
150 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
151 #define MVPP2_RXQ_INDEX_REG 0x2050
152 #define MVPP2_TXQ_NUM_REG 0x2080
153 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
154 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
155 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
156 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
157 #define MVPP2_TXQ_THRESH_REG 0x2094
158 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
159 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
160 #define MVPP2_TXQ_INDEX_REG 0x2098
161 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
162 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
163 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
164 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
165 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
166 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
167 #define MVPP2_TXQ_PENDING_REG 0x20a0
168 #define MVPP2_TXQ_PENDING_MASK 0x3fff
169 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
170 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
171 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
172 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
173 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
174 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
175 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
176 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
177 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
178 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
179 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
180 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
181 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
182 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
183 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
184 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
185 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
187 /* MBUS bridge registers */
188 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
189 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
190 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
191 #define MVPP2_BASE_ADDR_ENABLE 0x4060
193 /* AXI Bridge Registers */
194 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
195 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
196 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
197 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
198 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
199 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
200 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
201 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
202 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
203 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
204 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
205 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
207 /* Values for AXI Bridge registers */
208 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
209 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
211 #define MVPP22_AXI_CODE_CACHE_OFFS 0
212 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
214 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
215 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
216 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
218 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
219 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
221 /* Interrupt Cause and Mask registers */
222 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
223 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
225 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
226 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
227 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
228 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
230 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
231 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
233 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
234 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
235 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
236 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
238 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
239 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
240 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
241 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
242 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
243 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
244 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
245 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
246 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
247 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
248 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
249 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
250 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
251 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
252 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
253 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
254 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
255 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
257 /* Buffer Manager registers */
258 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
259 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
260 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
261 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
262 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
263 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
264 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
265 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
266 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
267 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
268 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
269 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
270 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
271 #define MVPP2_BM_START_MASK BIT(0)
272 #define MVPP2_BM_STOP_MASK BIT(1)
273 #define MVPP2_BM_STATE_MASK BIT(4)
274 #define MVPP2_BM_LOW_THRESH_OFFS 8
275 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
276 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
277 MVPP2_BM_LOW_THRESH_OFFS)
278 #define MVPP2_BM_HIGH_THRESH_OFFS 16
279 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
280 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
281 MVPP2_BM_HIGH_THRESH_OFFS)
282 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
283 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
284 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
285 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
286 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
287 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
288 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
289 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
290 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
291 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
292 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
293 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
294 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
295 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
296 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
297 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
298 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
299 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
300 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
301 #define MVPP21_BM_MC_RLS_REG 0x64c4
302 #define MVPP2_BM_MC_ID_MASK 0xfff
303 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
304 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
305 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
306 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
307 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
308 #define MVPP22_BM_MC_RLS_REG 0x64d4
309 #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
310 #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
312 /* TX Scheduler registers */
313 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
314 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
315 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
316 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
317 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
318 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
319 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
320 #define MVPP2_TXP_MTU_MAX 0x7FFFF
321 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
322 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
323 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
324 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
325 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
326 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
327 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
328 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
329 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
330 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
331 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
332 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
333 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
334 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
336 /* TX general registers */
337 #define MVPP2_TX_SNOOP_REG 0x8800
338 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
339 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
342 #define MVPP2_SRC_ADDR_MIDDLE 0x24
343 #define MVPP2_SRC_ADDR_HIGH 0x28
344 #define MVPP2_PHY_AN_CFG0_REG 0x34
345 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
346 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
347 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
349 /* Per-port registers */
350 #define MVPP2_GMAC_CTRL_0_REG 0x0
351 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
352 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
353 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
354 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
355 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
356 #define MVPP2_GMAC_CTRL_1_REG 0x4
357 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
358 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
359 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
360 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
361 #define MVPP2_GMAC_SA_LOW_OFFS 7
362 #define MVPP2_GMAC_CTRL_2_REG 0x8
363 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
364 #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
365 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
366 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
367 #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
368 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
369 #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
370 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
371 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
372 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
373 #define MVPP2_GMAC_EN_PCS_AN BIT(2)
374 #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
375 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
376 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
377 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
378 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
379 #define MVPP2_GMAC_EN_FC_AN BIT(11)
380 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
381 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
382 #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
383 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
384 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
385 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
386 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
387 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
388 #define MVPP2_GMAC_CTRL_4_REG 0x90
389 #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
390 #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
391 #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
392 #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
395 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
396 * relative to port->base.
399 /* Port Mac Control0 */
400 #define MVPP22_XLG_CTRL0_REG 0x100
401 #define MVPP22_XLG_PORT_EN BIT(0)
402 #define MVPP22_XLG_MAC_RESETN BIT(1)
403 #define MVPP22_XLG_RX_FC_EN BIT(7)
404 #define MVPP22_XLG_MIBCNT_DIS BIT(13)
405 /* Port Mac Control1 */
406 #define MVPP22_XLG_CTRL1_REG 0x104
407 #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
408 #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
409 /* Port Interrupt Mask */
410 #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
411 #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
412 /* Port Mac Control3 */
413 #define MVPP22_XLG_CTRL3_REG 0x11c
414 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
415 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
416 #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
417 /* Port Mac Control4 */
418 #define MVPP22_XLG_CTRL4_REG 0x184
419 #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
420 #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
421 #define MVPP22_XLG_MODE_DMA_1G BIT(12)
422 #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
426 /* Global Configuration 0 */
427 #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
428 #define MVPP22_XPCS_PCSRESET BIT(0)
429 #define MVPP22_XPCS_PCSMODE_OFFS 3
430 #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
431 MVPP22_XPCS_PCSMODE_OFFS)
432 #define MVPP22_XPCS_LANEACTIVE_OFFS 5
433 #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
434 MVPP22_XPCS_LANEACTIVE_OFFS)
438 #define PCS40G_COMMON_CONTROL 0x14
439 #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
441 #define PCS_CLOCK_RESET 0x14c
442 #define TX_SD_CLK_RESET_MASK BIT(0)
443 #define RX_SD_CLK_RESET_MASK BIT(1)
444 #define MAC_CLK_RESET_MASK BIT(2)
445 #define CLK_DIVISION_RATIO_OFFS 4
446 #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
447 #define CLK_DIV_PHASE_SET_MASK BIT(11)
449 /* System Soft Reset 1 */
450 #define GOP_SOFT_RESET_1_REG 0x108
451 #define NETC_GOP_SOFT_RESET_OFFS 6
452 #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
453 NETC_GOP_SOFT_RESET_OFFS)
455 /* Ports Control 0 */
456 #define NETCOMP_PORTS_CONTROL_0_REG 0x110
457 #define NETC_BUS_WIDTH_SELECT_OFFS 1
458 #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
459 NETC_BUS_WIDTH_SELECT_OFFS)
460 #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
461 #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
462 NETC_GIG_RX_DATA_SAMPLE_OFFS)
463 #define NETC_CLK_DIV_PHASE_OFFS 31
464 #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
465 /* Ports Control 1 */
466 #define NETCOMP_PORTS_CONTROL_1_REG 0x114
467 #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
468 #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
469 NETC_PORTS_ACTIVE_OFFSET(p))
470 #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
471 #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
472 NETC_PORT_GIG_RF_RESET_OFFS(p))
473 #define NETCOMP_CONTROL_0_REG 0x120
474 #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
475 #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
476 NETC_GBE_PORT0_SGMII_MODE_OFFS)
477 #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
478 #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
479 NETC_GBE_PORT1_SGMII_MODE_OFFS)
480 #define NETC_GBE_PORT1_MII_MODE_OFFS 2
481 #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
482 NETC_GBE_PORT1_MII_MODE_OFFS)
484 #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
485 #define MVPP22_SMI_POLLING_EN BIT(10)
487 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
490 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
492 /* Descriptor ring Macros */
493 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
494 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
496 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
497 #define MVPP22_SMI 0x1200
499 /* Additional PPv2.2 offsets */
500 #define MVPP22_MPCS 0x007000
501 #define MVPP22_XPCS 0x007400
502 #define MVPP22_PORT_BASE 0x007e00
503 #define MVPP22_PORT_OFFSET 0x001000
504 #define MVPP22_RFU1 0x318000
506 /* Maximum number of ports */
507 #define MVPP22_GOP_MAC_NUM 4
509 /* Sets the field located at the specified in data */
510 #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
511 #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
512 #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
515 enum mv_netc_topology {
516 MV_NETC_GE_MAC2_SGMII = BIT(0),
517 MV_NETC_GE_MAC3_SGMII = BIT(1),
518 MV_NETC_GE_MAC3_RGMII = BIT(2),
523 MV_NETC_SECOND_PHASE,
526 enum mv_netc_sgmii_xmi_mode {
531 enum mv_netc_mii_mode {
541 /* Various constants */
544 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
545 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
546 #define MVPP2_RX_COAL_PKTS 32
547 #define MVPP2_RX_COAL_USEC 100
549 /* The two bytes Marvell header. Either contains a special value used
550 * by Marvell switches when a specific hardware mode is enabled (not
551 * supported by this driver) or is filled automatically by zeroes on
552 * the RX side. Those two bytes being at the front of the Ethernet
553 * header, they allow to have the IP header aligned on a 4 bytes
554 * boundary automatically: the hardware skips those two bytes on its
557 #define MVPP2_MH_SIZE 2
558 #define MVPP2_ETH_TYPE_LEN 2
559 #define MVPP2_PPPOE_HDR_SIZE 8
560 #define MVPP2_VLAN_TAG_LEN 4
562 /* Lbtd 802.3 type */
563 #define MVPP2_IP_LBDT_TYPE 0xfffa
565 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
566 #define MVPP2_TX_CSUM_MAX_SIZE 9800
568 /* Timeout constants */
569 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
570 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
572 #define MVPP2_TX_MTU_MAX 0x7ffff
574 /* Maximum number of T-CONTs of PON port */
575 #define MVPP2_MAX_TCONT 16
577 /* Maximum number of supported ports */
578 #define MVPP2_MAX_PORTS 4
580 /* Maximum number of TXQs used by single port */
581 #define MVPP2_MAX_TXQ 8
583 /* Default number of TXQs in use */
584 #define MVPP2_DEFAULT_TXQ 1
586 /* Default number of RXQs in use */
587 #define MVPP2_DEFAULT_RXQ 1
588 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
590 /* Max number of Rx descriptors */
591 #define MVPP2_MAX_RXD 16
593 /* Max number of Tx descriptors */
594 #define MVPP2_MAX_TXD 16
596 /* Amount of Tx descriptors that can be reserved at once by CPU */
597 #define MVPP2_CPU_DESC_CHUNK 16
599 /* Max number of Tx descriptors in each aggregated queue */
600 #define MVPP2_AGGR_TXQ_SIZE 16
602 /* Descriptor aligned size */
603 #define MVPP2_DESC_ALIGNED_SIZE 32
605 /* Descriptor alignment mask */
606 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
608 /* RX FIFO constants */
609 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
610 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
611 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
612 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
613 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
614 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
615 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
616 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
617 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
619 /* TX general registers */
620 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
621 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
623 /* TX FIFO constants */
624 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
625 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
627 /* RX buffer constants */
628 #define MVPP2_SKB_SHINFO_SIZE \
631 #define MVPP2_RX_PKT_SIZE(mtu) \
632 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
633 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
635 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
636 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
637 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
638 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
640 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
642 /* IPv6 max L3 address size */
643 #define MVPP2_MAX_L3_ADDR_SIZE 16
646 #define MVPP2_F_LOOPBACK BIT(0)
648 /* Marvell tag types */
649 enum mvpp2_tag_type {
650 MVPP2_TAG_TYPE_NONE = 0,
651 MVPP2_TAG_TYPE_MH = 1,
652 MVPP2_TAG_TYPE_DSA = 2,
653 MVPP2_TAG_TYPE_EDSA = 3,
654 MVPP2_TAG_TYPE_VLAN = 4,
655 MVPP2_TAG_TYPE_LAST = 5
658 /* Parser constants */
659 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
660 #define MVPP2_PRS_TCAM_WORDS 6
661 #define MVPP2_PRS_SRAM_WORDS 4
662 #define MVPP2_PRS_FLOW_ID_SIZE 64
663 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
664 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
665 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
666 #define MVPP2_PRS_IPV4_HEAD 0x40
667 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
668 #define MVPP2_PRS_IPV4_MC 0xe0
669 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
670 #define MVPP2_PRS_IPV4_BC_MASK 0xff
671 #define MVPP2_PRS_IPV4_IHL 0x5
672 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
673 #define MVPP2_PRS_IPV6_MC 0xff
674 #define MVPP2_PRS_IPV6_MC_MASK 0xff
675 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
676 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
677 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
678 #define MVPP2_PRS_DBL_VLANS_MAX 100
681 * - lookup ID - 4 bits
683 * - additional information - 1 byte
684 * - header data - 8 bytes
685 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
687 #define MVPP2_PRS_AI_BITS 8
688 #define MVPP2_PRS_PORT_MASK 0xff
689 #define MVPP2_PRS_LU_MASK 0xf
690 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
691 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
692 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
693 (((offs) * 2) - ((offs) % 2) + 2)
694 #define MVPP2_PRS_TCAM_AI_BYTE 16
695 #define MVPP2_PRS_TCAM_PORT_BYTE 17
696 #define MVPP2_PRS_TCAM_LU_BYTE 20
697 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
698 #define MVPP2_PRS_TCAM_INV_WORD 5
699 /* Tcam entries ID */
700 #define MVPP2_PE_DROP_ALL 0
701 #define MVPP2_PE_FIRST_FREE_TID 1
702 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
703 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
704 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
705 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
706 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
707 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
708 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
709 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
710 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
711 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
712 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
713 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
714 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
715 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
716 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
717 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
718 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
719 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
720 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
721 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
722 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
723 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
724 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
725 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
726 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
729 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
731 #define MVPP2_PRS_SRAM_RI_OFFS 0
732 #define MVPP2_PRS_SRAM_RI_WORD 0
733 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
734 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
735 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
736 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
737 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
738 #define MVPP2_PRS_SRAM_UDF_OFFS 73
739 #define MVPP2_PRS_SRAM_UDF_BITS 8
740 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
741 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
742 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
743 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
744 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
745 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
746 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
747 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
748 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
749 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
750 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
751 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
752 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
753 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
754 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
755 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
756 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
757 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
758 #define MVPP2_PRS_SRAM_AI_OFFS 90
759 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
760 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
761 #define MVPP2_PRS_SRAM_AI_MASK 0xff
762 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
763 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
764 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
765 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
767 /* Sram result info bits assignment */
768 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
769 #define MVPP2_PRS_RI_DSA_MASK 0x2
770 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
771 #define MVPP2_PRS_RI_VLAN_NONE 0x0
772 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
773 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
774 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
775 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
776 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
777 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
778 #define MVPP2_PRS_RI_L2_UCAST 0x0
779 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
780 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
781 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
782 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
783 #define MVPP2_PRS_RI_L3_UN 0x0
784 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
785 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
786 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
787 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
788 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
789 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
790 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
791 #define MVPP2_PRS_RI_L3_UCAST 0x0
792 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
793 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
794 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
795 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
796 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
797 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
798 #define MVPP2_PRS_RI_L4_TCP BIT(22)
799 #define MVPP2_PRS_RI_L4_UDP BIT(23)
800 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
801 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
802 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
803 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
805 /* Sram additional info bits assignment */
806 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
807 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
808 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
809 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
810 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
811 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
812 #define MVPP2_PRS_SINGLE_VLAN_AI 0
813 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
816 #define MVPP2_PRS_TAGGED true
817 #define MVPP2_PRS_UNTAGGED false
818 #define MVPP2_PRS_EDSA true
819 #define MVPP2_PRS_DSA false
821 /* MAC entries, shadow udf */
823 MVPP2_PRS_UDF_MAC_DEF,
824 MVPP2_PRS_UDF_MAC_RANGE,
825 MVPP2_PRS_UDF_L2_DEF,
826 MVPP2_PRS_UDF_L2_DEF_COPY,
827 MVPP2_PRS_UDF_L2_USER,
831 enum mvpp2_prs_lookup {
845 enum mvpp2_prs_l3_cast {
846 MVPP2_PRS_L3_UNI_CAST,
847 MVPP2_PRS_L3_MULTI_CAST,
848 MVPP2_PRS_L3_BROAD_CAST
851 /* Classifier constants */
852 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
853 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
854 #define MVPP2_CLS_LKP_TBL_SIZE 64
857 #define MVPP2_BM_POOLS_NUM 1
858 #define MVPP2_BM_LONG_BUF_NUM 16
859 #define MVPP2_BM_SHORT_BUF_NUM 16
860 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
861 #define MVPP2_BM_POOL_PTR_ALIGN 128
862 #define MVPP2_BM_SWF_LONG_POOL(port) 0
864 /* BM cookie (32 bits) definition */
865 #define MVPP2_BM_COOKIE_POOL_OFFS 8
866 #define MVPP2_BM_COOKIE_CPU_OFFS 24
868 /* BM short pool packet size
869 * These value assure that for SWF the total number
870 * of bytes allocated for each buffer will be 512
872 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
882 /* Shared Packet Processor resources */
884 /* Shared registers' base addresses */
886 void __iomem *lms_base;
887 void __iomem *iface_base;
889 void __iomem *mpcs_base;
890 void __iomem *xpcs_base;
891 void __iomem *rfu1_base;
895 /* List of pointers to port structures */
896 struct mvpp2_port **port_list;
898 /* Aggregated TXQs */
899 struct mvpp2_tx_queue *aggr_txqs;
902 struct mvpp2_bm_pool *bm_pools;
904 /* PRS shadow table */
905 struct mvpp2_prs_shadow *prs_shadow;
906 /* PRS auxiliary table for double vlan entries control */
907 bool *prs_double_vlans;
913 enum { MVPP21, MVPP22 } hw_version;
915 /* Maximum number of RXQs per port */
916 unsigned int max_port_rxqs;
922 struct mvpp2_pcpu_stats {
932 /* Index of the port from the "group of ports" complex point
941 /* Per-port registers' base address */
944 struct mvpp2_rx_queue **rxqs;
945 struct mvpp2_tx_queue **txqs;
949 u32 pending_cause_rx;
951 /* Per-CPU port control */
952 struct mvpp2_port_pcpu __percpu *pcpu;
959 struct mvpp2_pcpu_stats __percpu *stats;
961 struct phy_device *phy_dev;
962 phy_interface_t phy_interface;
964 struct udevice *mdio_dev;
966 #if CONFIG_IS_ENABLED(DM_GPIO)
967 struct gpio_desc phy_reset_gpio;
968 struct gpio_desc phy_tx_disable_gpio;
975 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
977 struct mvpp2_bm_pool *pool_long;
978 struct mvpp2_bm_pool *pool_short;
980 /* Index of first port's physical RXQ */
983 u8 dev_addr[ETH_ALEN];
986 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
987 * layout of the transmit and reception DMA descriptors, and their
988 * layout is therefore defined by the hardware design
991 #define MVPP2_TXD_L3_OFF_SHIFT 0
992 #define MVPP2_TXD_IP_HLEN_SHIFT 8
993 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
994 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
995 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
996 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
997 #define MVPP2_TXD_L4_UDP BIT(24)
998 #define MVPP2_TXD_L3_IP6 BIT(26)
999 #define MVPP2_TXD_L_DESC BIT(28)
1000 #define MVPP2_TXD_F_DESC BIT(29)
1002 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
1003 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1004 #define MVPP2_RXD_ERR_CRC 0x0
1005 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
1006 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1007 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
1008 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1009 #define MVPP2_RXD_HWF_SYNC BIT(21)
1010 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
1011 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1012 #define MVPP2_RXD_L4_TCP BIT(25)
1013 #define MVPP2_RXD_L4_UDP BIT(26)
1014 #define MVPP2_RXD_L3_IP4 BIT(28)
1015 #define MVPP2_RXD_L3_IP6 BIT(30)
1016 #define MVPP2_RXD_BUF_HDR BIT(31)
1018 /* HW TX descriptor for PPv2.1 */
1019 struct mvpp21_tx_desc {
1020 u32 command; /* Options used by HW for packet transmitting.*/
1021 u8 packet_offset; /* the offset from the buffer beginning */
1022 u8 phys_txq; /* destination queue ID */
1023 u16 data_size; /* data size of transmitted packet in bytes */
1024 u32 buf_dma_addr; /* physical addr of transmitted buffer */
1025 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1026 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1027 u32 reserved2; /* reserved (for future use) */
1030 /* HW RX descriptor for PPv2.1 */
1031 struct mvpp21_rx_desc {
1032 u32 status; /* info about received packet */
1033 u16 reserved1; /* parser_info (for future use, PnC) */
1034 u16 data_size; /* size of received packet in bytes */
1035 u32 buf_dma_addr; /* physical address of the buffer */
1036 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1037 u16 reserved2; /* gem_port_id (for future use, PON) */
1038 u16 reserved3; /* csum_l4 (for future use, PnC) */
1039 u8 reserved4; /* bm_qset (for future use, BM) */
1041 u16 reserved6; /* classify_info (for future use, PnC) */
1042 u32 reserved7; /* flow_id (for future use, PnC) */
1046 /* HW TX descriptor for PPv2.2 */
1047 struct mvpp22_tx_desc {
1053 u64 buf_dma_addr_ptp;
1054 u64 buf_cookie_misc;
1057 /* HW RX descriptor for PPv2.2 */
1058 struct mvpp22_rx_desc {
1064 u64 buf_dma_addr_key_hash;
1065 u64 buf_cookie_misc;
1068 /* Opaque type used by the driver to manipulate the HW TX and RX
1071 struct mvpp2_tx_desc {
1073 struct mvpp21_tx_desc pp21;
1074 struct mvpp22_tx_desc pp22;
1078 struct mvpp2_rx_desc {
1080 struct mvpp21_rx_desc pp21;
1081 struct mvpp22_rx_desc pp22;
1085 /* Per-CPU Tx queue control */
1086 struct mvpp2_txq_pcpu {
1089 /* Number of Tx DMA descriptors in the descriptor ring */
1092 /* Number of currently used Tx DMA descriptor in the
1097 /* Number of Tx DMA descriptors reserved for each CPU */
1100 /* Index of last TX DMA descriptor that was inserted */
1103 /* Index of the TX DMA descriptor to be cleaned up */
1107 struct mvpp2_tx_queue {
1108 /* Physical number of this Tx queue */
1111 /* Logical number of this Tx queue */
1114 /* Number of Tx DMA descriptors in the descriptor ring */
1117 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1120 /* Per-CPU control of physical Tx queues */
1121 struct mvpp2_txq_pcpu __percpu *pcpu;
1125 /* Virtual address of thex Tx DMA descriptors array */
1126 struct mvpp2_tx_desc *descs;
1128 /* DMA address of the Tx DMA descriptors array */
1129 dma_addr_t descs_dma;
1131 /* Index of the last Tx DMA descriptor */
1134 /* Index of the next Tx DMA descriptor to process */
1135 int next_desc_to_proc;
1138 struct mvpp2_rx_queue {
1139 /* RX queue number, in the range 0-31 for physical RXQs */
1142 /* Num of rx descriptors in the rx descriptor ring */
1148 /* Virtual address of the RX DMA descriptors array */
1149 struct mvpp2_rx_desc *descs;
1151 /* DMA address of the RX DMA descriptors array */
1152 dma_addr_t descs_dma;
1154 /* Index of the last RX DMA descriptor */
1157 /* Index of the next RX DMA descriptor to process */
1158 int next_desc_to_proc;
1160 /* ID of port to which physical RXQ is mapped */
1163 /* Port's logic RXQ number to which physical RXQ is mapped */
1167 union mvpp2_prs_tcam_entry {
1168 u32 word[MVPP2_PRS_TCAM_WORDS];
1169 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1172 union mvpp2_prs_sram_entry {
1173 u32 word[MVPP2_PRS_SRAM_WORDS];
1174 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1177 struct mvpp2_prs_entry {
1179 union mvpp2_prs_tcam_entry tcam;
1180 union mvpp2_prs_sram_entry sram;
1183 struct mvpp2_prs_shadow {
1190 /* User defined offset */
1198 struct mvpp2_cls_flow_entry {
1200 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1203 struct mvpp2_cls_lookup_entry {
1209 struct mvpp2_bm_pool {
1210 /* Pool number in the range 0-7 */
1212 enum mvpp2_bm_type type;
1214 /* Buffer Pointers Pool External (BPPE) size */
1216 /* Number of buffers for this pool */
1218 /* Pool buffer size */
1223 /* BPPE virtual base address */
1224 unsigned long *virt_addr;
1225 /* BPPE DMA base address */
1226 dma_addr_t dma_addr;
1228 /* Ports using BM pool */
1232 /* Static declaractions */
1234 /* Number of RXQs used by single port */
1235 static int rxq_number = MVPP2_DEFAULT_RXQ;
1236 /* Number of TXQs used by single port */
1237 static int txq_number = MVPP2_DEFAULT_TXQ;
1241 #define MVPP2_DRIVER_NAME "mvpp2"
1242 #define MVPP2_DRIVER_VERSION "1.0"
1245 * U-Boot internal data, mostly uncached buffers for descriptors and data
1247 struct buffer_location {
1248 struct mvpp2_tx_desc *aggr_tx_descs;
1249 struct mvpp2_tx_desc *tx_descs;
1250 struct mvpp2_rx_desc *rx_descs;
1251 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1252 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1257 * All 4 interfaces use the same global buffer, since only one interface
1258 * can be enabled at once
1260 static struct buffer_location buffer_loc;
1263 * Page table entries are set to 1MB, or multiples of 1MB
1264 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1266 #define BD_SPACE (1 << 20)
1268 /* Utility/helper methods */
1270 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1272 writel(data, priv->base + offset);
1275 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1277 return readl(priv->base + offset);
1280 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1281 struct mvpp2_tx_desc *tx_desc,
1282 dma_addr_t dma_addr)
1284 if (port->priv->hw_version == MVPP21) {
1285 tx_desc->pp21.buf_dma_addr = dma_addr;
1287 u64 val = (u64)dma_addr;
1289 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1290 tx_desc->pp22.buf_dma_addr_ptp |= val;
1294 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1295 struct mvpp2_tx_desc *tx_desc,
1298 if (port->priv->hw_version == MVPP21)
1299 tx_desc->pp21.data_size = size;
1301 tx_desc->pp22.data_size = size;
1304 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1305 struct mvpp2_tx_desc *tx_desc,
1308 if (port->priv->hw_version == MVPP21)
1309 tx_desc->pp21.phys_txq = txq;
1311 tx_desc->pp22.phys_txq = txq;
1314 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1315 struct mvpp2_tx_desc *tx_desc,
1316 unsigned int command)
1318 if (port->priv->hw_version == MVPP21)
1319 tx_desc->pp21.command = command;
1321 tx_desc->pp22.command = command;
1324 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1325 struct mvpp2_tx_desc *tx_desc,
1326 unsigned int offset)
1328 if (port->priv->hw_version == MVPP21)
1329 tx_desc->pp21.packet_offset = offset;
1331 tx_desc->pp22.packet_offset = offset;
1334 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1335 struct mvpp2_rx_desc *rx_desc)
1337 if (port->priv->hw_version == MVPP21)
1338 return rx_desc->pp21.buf_dma_addr;
1340 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1343 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1344 struct mvpp2_rx_desc *rx_desc)
1346 if (port->priv->hw_version == MVPP21)
1347 return rx_desc->pp21.buf_cookie;
1349 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1352 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1353 struct mvpp2_rx_desc *rx_desc)
1355 if (port->priv->hw_version == MVPP21)
1356 return rx_desc->pp21.data_size;
1358 return rx_desc->pp22.data_size;
1361 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1362 struct mvpp2_rx_desc *rx_desc)
1364 if (port->priv->hw_version == MVPP21)
1365 return rx_desc->pp21.status;
1367 return rx_desc->pp22.status;
1370 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1372 txq_pcpu->txq_get_index++;
1373 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1374 txq_pcpu->txq_get_index = 0;
1377 /* Get number of physical egress port */
1378 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1380 return MVPP2_MAX_TCONT + port->id;
1383 /* Get number of physical TXQ */
1384 static inline int mvpp2_txq_phys(int port, int txq)
1386 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1389 /* Parser configuration routines */
1391 /* Update parser tcam and sram hw entries */
1392 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1396 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1399 /* Clear entry invalidation bit */
1400 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1402 /* Write tcam index - indirect access */
1403 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1404 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1405 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1407 /* Write sram index - indirect access */
1408 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1409 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1410 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1415 /* Read tcam entry from hw */
1416 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1420 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1423 /* Write tcam index - indirect access */
1424 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1426 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1427 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1428 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1429 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1431 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1432 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1434 /* Write sram index - indirect access */
1435 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1436 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1437 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1442 /* Invalidate tcam hw entry */
1443 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1445 /* Write index - indirect access */
1446 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1447 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1448 MVPP2_PRS_TCAM_INV_MASK);
1451 /* Enable shadow table entry and set its lookup ID */
1452 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1454 priv->prs_shadow[index].valid = true;
1455 priv->prs_shadow[index].lu = lu;
1458 /* Update ri fields in shadow table entry */
1459 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1460 unsigned int ri, unsigned int ri_mask)
1462 priv->prs_shadow[index].ri_mask = ri_mask;
1463 priv->prs_shadow[index].ri = ri;
1466 /* Update lookup field in tcam sw entry */
1467 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1469 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1471 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1472 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1475 /* Update mask for single port in tcam sw entry */
1476 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1477 unsigned int port, bool add)
1479 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1482 pe->tcam.byte[enable_off] &= ~(1 << port);
1484 pe->tcam.byte[enable_off] |= 1 << port;
1487 /* Update port map in tcam sw entry */
1488 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1491 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1492 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1494 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1495 pe->tcam.byte[enable_off] &= ~port_mask;
1496 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1499 /* Obtain port map from tcam sw entry */
1500 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1502 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1504 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1507 /* Set byte of data and its enable bits in tcam sw entry */
1508 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1509 unsigned int offs, unsigned char byte,
1510 unsigned char enable)
1512 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1513 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1516 /* Get byte of data and its enable bits from tcam sw entry */
1517 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1518 unsigned int offs, unsigned char *byte,
1519 unsigned char *enable)
1521 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1522 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1525 /* Set ethertype in tcam sw entry */
1526 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1527 unsigned short ethertype)
1529 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1530 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1533 /* Set bits in sram sw entry */
1534 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1537 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1540 /* Clear bits in sram sw entry */
1541 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1544 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1547 /* Update ri bits in sram sw entry */
1548 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1549 unsigned int bits, unsigned int mask)
1553 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1554 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1556 if (!(mask & BIT(i)))
1560 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1562 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1564 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1568 /* Update ai bits in sram sw entry */
1569 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1570 unsigned int bits, unsigned int mask)
1573 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1575 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1577 if (!(mask & BIT(i)))
1581 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1583 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1585 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1589 /* Read ai bits from sram sw entry */
1590 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1593 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1594 int ai_en_off = ai_off + 1;
1595 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1597 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1598 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1603 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1606 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1609 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1611 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1612 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1613 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1616 /* In the sram sw entry set sign and value of the next lookup offset
1617 * and the offset value generated to the classifier
1619 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1624 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1627 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1631 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1632 (unsigned char)shift;
1634 /* Reset and set operation */
1635 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1636 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1637 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1639 /* Set base offset as current */
1640 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1643 /* In the sram sw entry set sign and value of the user defined offset
1644 * generated to the classifier
1646 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1647 unsigned int type, int offset,
1652 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1653 offset = 0 - offset;
1655 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1659 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1660 MVPP2_PRS_SRAM_UDF_MASK);
1661 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1662 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1663 MVPP2_PRS_SRAM_UDF_BITS)] &=
1664 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1665 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1666 MVPP2_PRS_SRAM_UDF_BITS)] |=
1667 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1669 /* Set offset type */
1670 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1671 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1672 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1674 /* Set offset operation */
1675 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1676 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1677 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1679 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1680 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1681 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1682 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1684 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1685 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1686 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1688 /* Set base offset as current */
1689 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1692 /* Find parser flow entry */
1693 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1695 struct mvpp2_prs_entry *pe;
1698 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1701 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1703 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1704 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1707 if (!priv->prs_shadow[tid].valid ||
1708 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1712 mvpp2_prs_hw_read(priv, pe);
1713 bits = mvpp2_prs_sram_ai_get(pe);
1715 /* Sram store classification lookup ID in AI bits [5:0] */
1716 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1724 /* Return first free tcam index, seeking from start to end */
1725 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1733 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1734 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1736 for (tid = start; tid <= end; tid++) {
1737 if (!priv->prs_shadow[tid].valid)
1744 /* Enable/disable dropping all mac da's */
1745 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1747 struct mvpp2_prs_entry pe;
1749 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1750 /* Entry exist - update port only */
1751 pe.index = MVPP2_PE_DROP_ALL;
1752 mvpp2_prs_hw_read(priv, &pe);
1754 /* Entry doesn't exist - create new */
1755 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1756 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1757 pe.index = MVPP2_PE_DROP_ALL;
1759 /* Non-promiscuous mode for all ports - DROP unknown packets */
1760 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1761 MVPP2_PRS_RI_DROP_MASK);
1763 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1764 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1766 /* Update shadow table */
1767 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1769 /* Mask all ports */
1770 mvpp2_prs_tcam_port_map_set(&pe, 0);
1773 /* Update port mask */
1774 mvpp2_prs_tcam_port_set(&pe, port, add);
1776 mvpp2_prs_hw_write(priv, &pe);
1779 /* Set port to promiscuous mode */
1780 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1782 struct mvpp2_prs_entry pe;
1784 /* Promiscuous mode - Accept unknown packets */
1786 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1787 /* Entry exist - update port only */
1788 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1789 mvpp2_prs_hw_read(priv, &pe);
1791 /* Entry doesn't exist - create new */
1792 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1793 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1794 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1796 /* Continue - set next lookup */
1797 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1799 /* Set result info bits */
1800 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1801 MVPP2_PRS_RI_L2_CAST_MASK);
1803 /* Shift to ethertype */
1804 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1805 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1807 /* Mask all ports */
1808 mvpp2_prs_tcam_port_map_set(&pe, 0);
1810 /* Update shadow table */
1811 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1814 /* Update port mask */
1815 mvpp2_prs_tcam_port_set(&pe, port, add);
1817 mvpp2_prs_hw_write(priv, &pe);
1820 /* Accept multicast */
1821 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1824 struct mvpp2_prs_entry pe;
1825 unsigned char da_mc;
1827 /* Ethernet multicast address first byte is
1828 * 0x01 for IPv4 and 0x33 for IPv6
1830 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1832 if (priv->prs_shadow[index].valid) {
1833 /* Entry exist - update port only */
1835 mvpp2_prs_hw_read(priv, &pe);
1837 /* Entry doesn't exist - create new */
1838 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1839 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1842 /* Continue - set next lookup */
1843 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1845 /* Set result info bits */
1846 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1847 MVPP2_PRS_RI_L2_CAST_MASK);
1849 /* Update tcam entry data first byte */
1850 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1852 /* Shift to ethertype */
1853 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1854 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1856 /* Mask all ports */
1857 mvpp2_prs_tcam_port_map_set(&pe, 0);
1859 /* Update shadow table */
1860 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1863 /* Update port mask */
1864 mvpp2_prs_tcam_port_set(&pe, port, add);
1866 mvpp2_prs_hw_write(priv, &pe);
1869 /* Parser per-port initialization */
1870 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1871 int lu_max, int offset)
1876 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1877 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1878 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1879 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1881 /* Set maximum number of loops for packet received from port */
1882 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1883 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1884 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1885 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1887 /* Set initial offset for packet header extraction for the first
1890 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1891 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1892 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1893 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1896 /* Default flow entries initialization for all ports */
1897 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1899 struct mvpp2_prs_entry pe;
1902 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1903 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1904 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1905 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1907 /* Mask all ports */
1908 mvpp2_prs_tcam_port_map_set(&pe, 0);
1911 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1912 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1914 /* Update shadow table and hw entry */
1915 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1916 mvpp2_prs_hw_write(priv, &pe);
1920 /* Set default entry for Marvell Header field */
1921 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1923 struct mvpp2_prs_entry pe;
1925 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1927 pe.index = MVPP2_PE_MH_DEFAULT;
1928 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1929 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1930 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1931 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1933 /* Unmask all ports */
1934 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1936 /* Update shadow table and hw entry */
1937 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1938 mvpp2_prs_hw_write(priv, &pe);
1941 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1942 * multicast MAC addresses
1944 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1946 struct mvpp2_prs_entry pe;
1948 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1950 /* Non-promiscuous mode for all ports - DROP unknown packets */
1951 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1952 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1954 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1955 MVPP2_PRS_RI_DROP_MASK);
1956 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1957 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1959 /* Unmask all ports */
1960 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1962 /* Update shadow table and hw entry */
1963 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1964 mvpp2_prs_hw_write(priv, &pe);
1966 /* place holders only - no ports */
1967 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1968 mvpp2_prs_mac_promisc_set(priv, 0, false);
1969 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1970 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1973 /* Match basic ethertypes */
1974 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1976 struct mvpp2_prs_entry pe;
1979 /* Ethertype: PPPoE */
1980 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1981 MVPP2_PE_LAST_FREE_TID);
1985 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1986 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1989 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1991 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1992 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1993 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1994 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1995 MVPP2_PRS_RI_PPPOE_MASK);
1997 /* Update shadow table and hw entry */
1998 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1999 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2000 priv->prs_shadow[pe.index].finish = false;
2001 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2002 MVPP2_PRS_RI_PPPOE_MASK);
2003 mvpp2_prs_hw_write(priv, &pe);
2005 /* Ethertype: ARP */
2006 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2007 MVPP2_PE_LAST_FREE_TID);
2011 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2012 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2015 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2017 /* Generate flow in the next iteration*/
2018 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2019 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2020 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2021 MVPP2_PRS_RI_L3_PROTO_MASK);
2023 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2025 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2027 /* Update shadow table and hw entry */
2028 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2029 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2030 priv->prs_shadow[pe.index].finish = true;
2031 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2032 MVPP2_PRS_RI_L3_PROTO_MASK);
2033 mvpp2_prs_hw_write(priv, &pe);
2035 /* Ethertype: LBTD */
2036 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2037 MVPP2_PE_LAST_FREE_TID);
2041 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2042 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2045 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2047 /* Generate flow in the next iteration*/
2048 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2049 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2050 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2051 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2052 MVPP2_PRS_RI_CPU_CODE_MASK |
2053 MVPP2_PRS_RI_UDF3_MASK);
2055 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2057 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2059 /* Update shadow table and hw entry */
2060 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2061 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2062 priv->prs_shadow[pe.index].finish = true;
2063 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2064 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2065 MVPP2_PRS_RI_CPU_CODE_MASK |
2066 MVPP2_PRS_RI_UDF3_MASK);
2067 mvpp2_prs_hw_write(priv, &pe);
2069 /* Ethertype: IPv4 without options */
2070 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2071 MVPP2_PE_LAST_FREE_TID);
2075 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2076 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2079 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2080 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2081 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2082 MVPP2_PRS_IPV4_HEAD_MASK |
2083 MVPP2_PRS_IPV4_IHL_MASK);
2085 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2086 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2087 MVPP2_PRS_RI_L3_PROTO_MASK);
2088 /* Skip eth_type + 4 bytes of IP header */
2089 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2090 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2092 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2094 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2096 /* Update shadow table and hw entry */
2097 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2098 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2099 priv->prs_shadow[pe.index].finish = false;
2100 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2101 MVPP2_PRS_RI_L3_PROTO_MASK);
2102 mvpp2_prs_hw_write(priv, &pe);
2104 /* Ethertype: IPv4 with options */
2105 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2106 MVPP2_PE_LAST_FREE_TID);
2112 /* Clear tcam data before updating */
2113 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2114 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2116 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2117 MVPP2_PRS_IPV4_HEAD,
2118 MVPP2_PRS_IPV4_HEAD_MASK);
2120 /* Clear ri before updating */
2121 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2122 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2123 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2124 MVPP2_PRS_RI_L3_PROTO_MASK);
2126 /* Update shadow table and hw entry */
2127 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2128 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2129 priv->prs_shadow[pe.index].finish = false;
2130 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2131 MVPP2_PRS_RI_L3_PROTO_MASK);
2132 mvpp2_prs_hw_write(priv, &pe);
2134 /* Ethertype: IPv6 without options */
2135 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2136 MVPP2_PE_LAST_FREE_TID);
2140 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2141 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2144 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2146 /* Skip DIP of IPV6 header */
2147 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2148 MVPP2_MAX_L3_ADDR_SIZE,
2149 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2150 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2151 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2152 MVPP2_PRS_RI_L3_PROTO_MASK);
2154 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2156 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2158 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2159 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2160 priv->prs_shadow[pe.index].finish = false;
2161 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2162 MVPP2_PRS_RI_L3_PROTO_MASK);
2163 mvpp2_prs_hw_write(priv, &pe);
2165 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2166 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2167 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2168 pe.index = MVPP2_PE_ETH_TYPE_UN;
2170 /* Unmask all ports */
2171 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2173 /* Generate flow in the next iteration*/
2174 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2175 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2176 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2177 MVPP2_PRS_RI_L3_PROTO_MASK);
2178 /* Set L3 offset even it's unknown L3 */
2179 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2181 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2183 /* Update shadow table and hw entry */
2184 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2185 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2186 priv->prs_shadow[pe.index].finish = true;
2187 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2188 MVPP2_PRS_RI_L3_PROTO_MASK);
2189 mvpp2_prs_hw_write(priv, &pe);
2194 /* Parser default initialization */
2195 static int mvpp2_prs_default_init(struct udevice *dev,
2200 /* Enable tcam table */
2201 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2203 /* Clear all tcam and sram entries */
2204 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2205 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2206 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2207 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2209 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2210 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2211 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2214 /* Invalidate all tcam entries */
2215 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2216 mvpp2_prs_hw_inv(priv, index);
2218 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2219 sizeof(struct mvpp2_prs_shadow),
2221 if (!priv->prs_shadow)
2224 /* Always start from lookup = 0 */
2225 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2226 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2227 MVPP2_PRS_PORT_LU_MAX, 0);
2229 mvpp2_prs_def_flow_init(priv);
2231 mvpp2_prs_mh_init(priv);
2233 mvpp2_prs_mac_init(priv);
2235 err = mvpp2_prs_etype_init(priv);
2242 /* Compare MAC DA with tcam entry data */
2243 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2244 const u8 *da, unsigned char *mask)
2246 unsigned char tcam_byte, tcam_mask;
2249 for (index = 0; index < ETH_ALEN; index++) {
2250 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2251 if (tcam_mask != mask[index])
2254 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2261 /* Find tcam entry with matched pair <MAC DA, port> */
2262 static struct mvpp2_prs_entry *
2263 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2264 unsigned char *mask, int udf_type)
2266 struct mvpp2_prs_entry *pe;
2269 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2272 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2274 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2275 for (tid = MVPP2_PE_FIRST_FREE_TID;
2276 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2277 unsigned int entry_pmap;
2279 if (!priv->prs_shadow[tid].valid ||
2280 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2281 (priv->prs_shadow[tid].udf != udf_type))
2285 mvpp2_prs_hw_read(priv, pe);
2286 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2288 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2297 /* Update parser's mac da entry */
2298 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2299 const u8 *da, bool add)
2301 struct mvpp2_prs_entry *pe;
2302 unsigned int pmap, len, ri;
2303 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2306 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2307 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2308 MVPP2_PRS_UDF_MAC_DEF);
2315 /* Create new TCAM entry */
2316 /* Find first range mac entry*/
2317 for (tid = MVPP2_PE_FIRST_FREE_TID;
2318 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2319 if (priv->prs_shadow[tid].valid &&
2320 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2321 (priv->prs_shadow[tid].udf ==
2322 MVPP2_PRS_UDF_MAC_RANGE))
2325 /* Go through the all entries from first to last */
2326 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2331 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2334 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2337 /* Mask all ports */
2338 mvpp2_prs_tcam_port_map_set(pe, 0);
2341 /* Update port mask */
2342 mvpp2_prs_tcam_port_set(pe, port, add);
2344 /* Invalidate the entry if no ports are left enabled */
2345 pmap = mvpp2_prs_tcam_port_map_get(pe);
2351 mvpp2_prs_hw_inv(priv, pe->index);
2352 priv->prs_shadow[pe->index].valid = false;
2357 /* Continue - set next lookup */
2358 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2360 /* Set match on DA */
2363 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2365 /* Set result info bits */
2366 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2368 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2369 MVPP2_PRS_RI_MAC_ME_MASK);
2370 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2371 MVPP2_PRS_RI_MAC_ME_MASK);
2373 /* Shift to ethertype */
2374 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2375 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2377 /* Update shadow table and hw entry */
2378 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2379 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2380 mvpp2_prs_hw_write(priv, pe);
2387 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2391 /* Remove old parser entry */
2392 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2397 /* Add new parser entry */
2398 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2402 /* Set addr in the device */
2403 memcpy(port->dev_addr, da, ETH_ALEN);
2408 /* Set prs flow for the port */
2409 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2411 struct mvpp2_prs_entry *pe;
2414 pe = mvpp2_prs_flow_find(port->priv, port->id);
2416 /* Such entry not exist */
2418 /* Go through the all entires from last to first */
2419 tid = mvpp2_prs_tcam_first_free(port->priv,
2420 MVPP2_PE_LAST_FREE_TID,
2421 MVPP2_PE_FIRST_FREE_TID);
2425 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2429 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2433 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2434 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2436 /* Update shadow table */
2437 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2440 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2441 mvpp2_prs_hw_write(port->priv, pe);
2447 /* Classifier configuration routines */
2449 /* Update classification flow table registers */
2450 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2451 struct mvpp2_cls_flow_entry *fe)
2453 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2454 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2455 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2456 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2459 /* Update classification lookup table register */
2460 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2461 struct mvpp2_cls_lookup_entry *le)
2465 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2466 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2467 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2470 /* Classifier default initialization */
2471 static void mvpp2_cls_init(struct mvpp2 *priv)
2473 struct mvpp2_cls_lookup_entry le;
2474 struct mvpp2_cls_flow_entry fe;
2477 /* Enable classifier */
2478 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2480 /* Clear classifier flow table */
2481 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2482 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2484 mvpp2_cls_flow_write(priv, &fe);
2487 /* Clear classifier lookup table */
2489 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2492 mvpp2_cls_lookup_write(priv, &le);
2495 mvpp2_cls_lookup_write(priv, &le);
2499 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2501 struct mvpp2_cls_lookup_entry le;
2504 /* Set way for the port */
2505 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2506 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2507 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2509 /* Pick the entry to be accessed in lookup ID decoding table
2510 * according to the way and lkpid.
2512 le.lkpid = port->id;
2516 /* Set initial CPU queue for receiving packets */
2517 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2518 le.data |= port->first_rxq;
2520 /* Disable classification engines */
2521 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2523 /* Update lookup ID table entry */
2524 mvpp2_cls_lookup_write(port->priv, &le);
2527 /* Set CPU queue number for oversize packets */
2528 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2532 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2533 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2535 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2536 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2538 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2539 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2540 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2543 /* Buffer Manager configuration routines */
2546 static int mvpp2_bm_pool_create(struct udevice *dev,
2548 struct mvpp2_bm_pool *bm_pool, int size)
2552 /* Number of buffer pointers must be a multiple of 16, as per
2553 * hardware constraints
2555 if (!IS_ALIGNED(size, 16))
2558 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2559 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2560 if (!bm_pool->virt_addr)
2563 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2564 MVPP2_BM_POOL_PTR_ALIGN)) {
2565 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2566 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2570 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2571 lower_32_bits(bm_pool->dma_addr));
2572 if (priv->hw_version == MVPP22)
2573 mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
2574 (upper_32_bits(bm_pool->dma_addr) &
2575 MVPP22_BM_POOL_BASE_HIGH_MASK));
2576 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2578 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2579 val |= MVPP2_BM_START_MASK;
2580 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2582 bm_pool->type = MVPP2_BM_FREE;
2583 bm_pool->size = size;
2584 bm_pool->pkt_size = 0;
2585 bm_pool->buf_num = 0;
2590 /* Set pool buffer size */
2591 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2592 struct mvpp2_bm_pool *bm_pool,
2597 bm_pool->buf_size = buf_size;
2599 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2600 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2603 /* Free all buffers from the pool */
2604 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2605 struct mvpp2_bm_pool *bm_pool)
2609 for (i = 0; i < bm_pool->buf_num; i++) {
2610 /* Allocate buffer back from the buffer manager */
2611 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2614 bm_pool->buf_num = 0;
2618 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2620 struct mvpp2_bm_pool *bm_pool)
2624 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2625 if (bm_pool->buf_num) {
2626 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2630 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2631 val |= MVPP2_BM_STOP_MASK;
2632 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2637 static int mvpp2_bm_pools_init(struct udevice *dev,
2641 struct mvpp2_bm_pool *bm_pool;
2643 /* Create all pools with maximum size */
2644 size = MVPP2_BM_POOL_SIZE_MAX;
2645 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2646 bm_pool = &priv->bm_pools[i];
2648 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2650 goto err_unroll_pools;
2651 mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
2656 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2657 for (i = i - 1; i >= 0; i--)
2658 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2662 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2666 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2667 /* Mask BM all interrupts */
2668 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2669 /* Clear BM cause register */
2670 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2673 /* Allocate and initialize BM pools */
2674 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2675 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2676 if (!priv->bm_pools)
2679 err = mvpp2_bm_pools_init(dev, priv);
2685 /* Attach long pool to rxq */
2686 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2687 int lrxq, int long_pool)
2692 /* Get queue physical ID */
2693 prxq = port->rxqs[lrxq]->id;
2695 if (port->priv->hw_version == MVPP21)
2696 mask = MVPP21_RXQ_POOL_LONG_MASK;
2698 mask = MVPP22_RXQ_POOL_LONG_MASK;
2700 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2702 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2703 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2706 /* Set pool number in a BM cookie */
2707 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2711 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2712 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2717 /* Get pool number from a BM cookie */
2718 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2720 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2723 /* Release buffer to BM */
2724 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2725 dma_addr_t buf_dma_addr,
2726 unsigned long buf_phys_addr)
2728 if (port->priv->hw_version == MVPP22) {
2731 if (sizeof(dma_addr_t) == 8)
2732 val |= upper_32_bits(buf_dma_addr) &
2733 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2735 if (sizeof(phys_addr_t) == 8)
2736 val |= (upper_32_bits(buf_phys_addr)
2737 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2738 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2740 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2743 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2744 * returned in the "cookie" field of the RX
2745 * descriptor. Instead of storing the virtual address, we
2746 * store the physical address
2748 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2749 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2752 /* Refill BM pool */
2753 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2754 dma_addr_t dma_addr,
2755 phys_addr_t phys_addr)
2757 int pool = mvpp2_bm_cookie_pool_get(bm);
2759 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2762 /* Allocate buffers for the pool */
2763 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2764 struct mvpp2_bm_pool *bm_pool, int buf_num)
2769 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2770 netdev_err(port->dev,
2771 "cannot allocate %d buffers for pool %d\n",
2772 buf_num, bm_pool->id);
2776 for (i = 0; i < buf_num; i++) {
2777 mvpp2_bm_pool_put(port, bm_pool->id,
2778 (dma_addr_t)buffer_loc.rx_buffer[i],
2779 (unsigned long)buffer_loc.rx_buffer[i]);
2783 /* Update BM driver with number of buffers added to pool */
2784 bm_pool->buf_num += i;
2789 /* Notify the driver that BM pool is being used as specific type and return the
2790 * pool pointer on success
2792 static struct mvpp2_bm_pool *
2793 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2796 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2799 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2800 netdev_err(port->dev, "mixing pool types is forbidden\n");
2804 if (new_pool->type == MVPP2_BM_FREE)
2805 new_pool->type = type;
2807 /* Allocate buffers in case BM pool is used as long pool, but packet
2808 * size doesn't match MTU or BM pool hasn't being used yet
2810 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2811 (new_pool->pkt_size == 0)) {
2814 /* Set default buffer number or free all the buffers in case
2815 * the pool is not empty
2817 pkts_num = new_pool->buf_num;
2819 pkts_num = type == MVPP2_BM_SWF_LONG ?
2820 MVPP2_BM_LONG_BUF_NUM :
2821 MVPP2_BM_SHORT_BUF_NUM;
2823 mvpp2_bm_bufs_free(NULL,
2824 port->priv, new_pool);
2826 new_pool->pkt_size = pkt_size;
2828 /* Allocate buffers for this pool */
2829 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2830 if (num != pkts_num) {
2831 dev_err(dev, "pool %d: %d of %d allocated\n",
2832 new_pool->id, num, pkts_num);
2840 /* Initialize pools for swf */
2841 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2845 if (!port->pool_long) {
2847 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2850 if (!port->pool_long)
2853 port->pool_long->port_map |= (1 << port->id);
2855 for (rxq = 0; rxq < rxq_number; rxq++)
2856 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2862 /* Port configuration routines */
2864 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2868 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2870 switch (port->phy_interface) {
2871 case PHY_INTERFACE_MODE_SGMII:
2872 val |= MVPP2_GMAC_INBAND_AN_MASK;
2874 case PHY_INTERFACE_MODE_RGMII:
2875 case PHY_INTERFACE_MODE_RGMII_ID:
2876 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2878 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2881 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2884 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2888 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2889 val |= MVPP2_GMAC_FC_ADV_EN;
2890 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2893 static void mvpp2_port_enable(struct mvpp2_port *port)
2897 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2898 val |= MVPP2_GMAC_PORT_EN_MASK;
2899 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2900 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2903 static void mvpp2_port_disable(struct mvpp2_port *port)
2907 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2908 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2909 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2912 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2913 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2917 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2918 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2919 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2922 /* Configure loopback port */
2923 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2927 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2929 if (port->speed == 1000)
2930 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2932 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2934 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2935 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2937 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2939 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2942 static void mvpp2_port_reset(struct mvpp2_port *port)
2946 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2947 ~MVPP2_GMAC_PORT_RESET_MASK;
2948 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2950 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2951 MVPP2_GMAC_PORT_RESET_MASK)
2955 /* Change maximum receive size of the port */
2956 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2960 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2961 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2962 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2963 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2964 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2967 /* PPv2.2 GoP/GMAC config */
2969 /* Set the MAC to reset or exit from reset */
2970 static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2974 /* read - modify - write */
2975 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2977 val |= MVPP2_GMAC_PORT_RESET_MASK;
2979 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
2980 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2988 * Configure port to working with Gig PCS or don't.
2990 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
2994 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2996 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
2998 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2999 /* enable / disable PCS on this port */
3000 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3005 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3009 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3011 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3013 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3014 /* enable / disable PCS on this port */
3015 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3020 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3025 * Configure minimal level of the Tx FIFO before the lower part
3026 * starts to read a packet
3028 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3029 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3030 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3031 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3032 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3034 /* Disable bypass of sync module */
3035 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3036 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3037 /* configure DP clock select according to mode */
3038 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3039 /* configure QSGMII bypass according to mode */
3040 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3041 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3043 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3045 * Configure GIG MAC to 1000Base-X mode connected to a fiber
3048 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3049 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3051 /* configure AN 0x9268 */
3052 val = MVPP2_GMAC_EN_PCS_AN |
3053 MVPP2_GMAC_AN_BYPASS_EN |
3054 MVPP2_GMAC_CONFIG_MII_SPEED |
3055 MVPP2_GMAC_CONFIG_GMII_SPEED |
3056 MVPP2_GMAC_FC_ADV_EN |
3057 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3058 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3059 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3062 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3067 * Configure minimal level of the Tx FIFO before the lower part
3068 * starts to read a packet
3070 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3071 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3072 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3073 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3074 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3076 /* Disable bypass of sync module */
3077 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3078 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3079 /* configure DP clock select according to mode */
3080 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3081 /* configure QSGMII bypass according to mode */
3082 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3083 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3085 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3086 /* configure GIG MAC to SGMII mode */
3087 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3088 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3091 val = MVPP2_GMAC_EN_PCS_AN |
3092 MVPP2_GMAC_AN_BYPASS_EN |
3093 MVPP2_GMAC_AN_SPEED_EN |
3094 MVPP2_GMAC_EN_FC_AN |
3095 MVPP2_GMAC_AN_DUPLEX_EN |
3096 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3097 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3100 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3105 * Configure minimal level of the Tx FIFO before the lower part
3106 * starts to read a packet
3108 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3109 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3110 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3111 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3112 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3114 /* Disable bypass of sync module */
3115 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3116 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3117 /* configure DP clock select according to mode */
3118 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3119 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3120 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3121 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3123 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3124 /* configure GIG MAC to SGMII mode */
3125 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3126 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3128 /* configure AN 0xb8e8 */
3129 val = MVPP2_GMAC_AN_BYPASS_EN |
3130 MVPP2_GMAC_AN_SPEED_EN |
3131 MVPP2_GMAC_EN_FC_AN |
3132 MVPP2_GMAC_AN_DUPLEX_EN |
3133 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3134 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3137 /* Set the internal mux's to the required MAC in the GOP */
3138 static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3142 /* Set TX FIFO thresholds */
3143 switch (port->phy_interface) {
3144 case PHY_INTERFACE_MODE_SGMII:
3145 if (port->phy_speed == 2500)
3146 gop_gmac_sgmii2_5_cfg(port);
3148 gop_gmac_sgmii_cfg(port);
3151 case PHY_INTERFACE_MODE_RGMII:
3152 case PHY_INTERFACE_MODE_RGMII_ID:
3153 gop_gmac_rgmii_cfg(port);
3160 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3161 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3162 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3163 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3164 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3166 /* PeriodicXonEn disable */
3167 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3168 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3169 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3174 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3178 /* relevant only for MAC0 (XLG0 and GMAC0) */
3179 if (port->gop_id > 0)
3182 /* configure 1Gig MAC mode */
3183 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3184 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3185 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3186 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3189 static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3193 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3195 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3197 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3198 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3203 /* Set the internal mux's to the required PCS in the PI */
3204 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
3209 switch (num_of_lanes) {
3223 /* configure XG MAC mode */
3224 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3225 val &= ~MVPP22_XPCS_PCSMODE_MASK;
3226 val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
3227 val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
3228 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3233 static int gop_mpcs_mode(struct mvpp2_port *port)
3237 /* configure PCS40G COMMON CONTROL */
3238 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3239 val &= ~FORWARD_ERROR_CORRECTION_MASK;
3240 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3242 /* configure PCS CLOCK RESET */
3243 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
3244 val &= ~CLK_DIVISION_RATIO_MASK;
3245 val |= 1 << CLK_DIVISION_RATIO_OFFS;
3246 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3248 val &= ~CLK_DIV_PHASE_SET_MASK;
3249 val |= MAC_CLK_RESET_MASK;
3250 val |= RX_SD_CLK_RESET_MASK;
3251 val |= TX_SD_CLK_RESET_MASK;
3252 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3257 /* Set the internal mux's to the required MAC in the GOP */
3258 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3262 /* configure 10G MAC mode */
3263 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3264 val |= MVPP22_XLG_RX_FC_EN;
3265 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3267 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3268 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3269 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3270 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3272 /* read - modify - write */
3273 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3274 val &= ~MVPP22_XLG_MODE_DMA_1G;
3275 val |= MVPP22_XLG_FORWARD_PFC_EN;
3276 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3277 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3278 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3280 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3281 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3282 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3283 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3284 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3286 /* unmask link change interrupt */
3287 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3288 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3289 val |= 1; /* unmask summary bit */
3290 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3295 /* Set PCS to reset or exit from reset */
3296 static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
3300 /* read - modify - write */
3301 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3303 val &= ~MVPP22_XPCS_PCSRESET;
3305 val |= MVPP22_XPCS_PCSRESET;
3306 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3311 /* Set the MAC to reset or exit from reset */
3312 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3316 /* read - modify - write */
3317 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3319 val &= ~MVPP22_XLG_MAC_RESETN;
3321 val |= MVPP22_XLG_MAC_RESETN;
3322 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3330 * Init physical port. Configures the port mode and all it's elements
3332 * Does not verify that the selected mode/port number is valid at the
3335 static int gop_port_init(struct mvpp2_port *port)
3337 int mac_num = port->gop_id;
3338 int num_of_act_lanes;
3340 if (mac_num >= MVPP22_GOP_MAC_NUM) {
3341 netdev_err(NULL, "%s: illegal port number %d", __func__,
3346 switch (port->phy_interface) {
3347 case PHY_INTERFACE_MODE_RGMII:
3348 case PHY_INTERFACE_MODE_RGMII_ID:
3349 gop_gmac_reset(port, 1);
3352 gop_gpcs_mode_cfg(port, 0);
3353 gop_bypass_clk_cfg(port, 1);
3356 gop_gmac_mode_cfg(port);
3358 gop_gpcs_reset(port, 0);
3361 gop_gmac_reset(port, 0);
3364 case PHY_INTERFACE_MODE_SGMII:
3366 gop_gpcs_mode_cfg(port, 1);
3369 gop_gmac_mode_cfg(port);
3370 /* select proper Mac mode */
3371 gop_xlg_2_gig_mac_cfg(port);
3374 gop_gpcs_reset(port, 0);
3376 gop_gmac_reset(port, 0);
3379 case PHY_INTERFACE_MODE_SFI:
3380 num_of_act_lanes = 2;
3383 gop_xpcs_mode(port, num_of_act_lanes);
3384 gop_mpcs_mode(port);
3386 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3389 gop_xpcs_reset(port, 0);
3392 gop_xlg_mac_reset(port, 0);
3396 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
3397 __func__, port->phy_interface);
3404 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3408 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3410 /* Enable port and MIB counters update */
3411 val |= MVPP22_XLG_PORT_EN;
3412 val &= ~MVPP22_XLG_MIBCNT_DIS;
3415 val &= ~MVPP22_XLG_PORT_EN;
3417 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3420 static void gop_port_enable(struct mvpp2_port *port, int enable)
3422 switch (port->phy_interface) {
3423 case PHY_INTERFACE_MODE_RGMII:
3424 case PHY_INTERFACE_MODE_RGMII_ID:
3425 case PHY_INTERFACE_MODE_SGMII:
3427 mvpp2_port_enable(port);
3429 mvpp2_port_disable(port);
3432 case PHY_INTERFACE_MODE_SFI:
3433 gop_xlg_mac_port_enable(port, enable);
3437 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
3438 port->phy_interface);
3443 /* RFU1 functions */
3444 static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3446 return readl(priv->rfu1_base + offset);
3449 static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3451 writel(data, priv->rfu1_base + offset);
3454 static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3459 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3460 val |= MV_NETC_GE_MAC2_SGMII;
3464 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3465 val |= MV_NETC_GE_MAC3_SGMII;
3466 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3467 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3468 val |= MV_NETC_GE_MAC3_RGMII;
3474 static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3478 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3479 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3481 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3482 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3486 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3489 static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3493 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3494 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3496 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3497 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3501 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3504 static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3508 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3509 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3511 val <<= NETC_GOP_SOFT_RESET_OFFS;
3512 val &= NETC_GOP_SOFT_RESET_MASK;
3516 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3519 static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3523 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3524 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3526 val <<= NETC_CLK_DIV_PHASE_OFFS;
3527 val &= NETC_CLK_DIV_PHASE_MASK;
3531 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3534 static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3538 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3539 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3541 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3542 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3546 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3549 static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3552 u32 reg, mask, offset;
3555 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3556 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3558 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3559 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3561 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3569 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3572 static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3576 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3577 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3579 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3580 val &= NETC_BUS_WIDTH_SELECT_MASK;
3584 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3587 static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3591 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3592 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3594 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3595 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3599 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3602 static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3603 enum mv_netc_phase phase)
3606 case MV_NETC_FIRST_PHASE:
3607 /* Set Bus Width to HB mode = 1 */
3608 gop_netc_bus_width_select(priv, 1);
3609 /* Select RGMII mode */
3610 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3613 case MV_NETC_SECOND_PHASE:
3614 /* De-assert the relevant port HB reset */
3615 gop_netc_port_rf_reset(priv, gop_id, 1);
3620 static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3621 enum mv_netc_phase phase)
3624 case MV_NETC_FIRST_PHASE:
3625 /* Set Bus Width to HB mode = 1 */
3626 gop_netc_bus_width_select(priv, 1);
3627 /* Select SGMII mode */
3629 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3633 /* Configure the sample stages */
3634 gop_netc_sample_stages_timing(priv, 0);
3635 /* Configure the ComPhy Selector */
3636 /* gop_netc_com_phy_selector_config(netComplex); */
3639 case MV_NETC_SECOND_PHASE:
3640 /* De-assert the relevant port HB reset */
3641 gop_netc_port_rf_reset(priv, gop_id, 1);
3646 static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3648 u32 c = priv->netc_config;
3650 if (c & MV_NETC_GE_MAC2_SGMII)
3651 gop_netc_mac_to_sgmii(priv, 2, phase);
3653 gop_netc_mac_to_xgmii(priv, 2, phase);
3655 if (c & MV_NETC_GE_MAC3_SGMII) {
3656 gop_netc_mac_to_sgmii(priv, 3, phase);
3658 gop_netc_mac_to_xgmii(priv, 3, phase);
3659 if (c & MV_NETC_GE_MAC3_RGMII)
3660 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3662 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3665 /* Activate gop ports 0, 2, 3 */
3666 gop_netc_active_port(priv, 0, 1);
3667 gop_netc_active_port(priv, 2, 1);
3668 gop_netc_active_port(priv, 3, 1);
3670 if (phase == MV_NETC_SECOND_PHASE) {
3671 /* Enable the GOP internal clock logic */
3672 gop_netc_gop_clock_logic_set(priv, 1);
3673 /* De-assert GOP unit reset */
3674 gop_netc_gop_reset(priv, 1);
3680 /* Set defaults to the MVPP2 port */
3681 static void mvpp2_defaults_set(struct mvpp2_port *port)
3683 int tx_port_num, val, queue, ptxq, lrxq;
3685 if (port->priv->hw_version == MVPP21) {
3686 /* Configure port to loopback if needed */
3687 if (port->flags & MVPP2_F_LOOPBACK)
3688 mvpp2_port_loopback_set(port);
3690 /* Update TX FIFO MIN Threshold */
3691 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3692 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3693 /* Min. TX threshold must be less than minimal packet length */
3694 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3695 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3698 /* Disable Legacy WRR, Disable EJP, Release from reset */
3699 tx_port_num = mvpp2_egress_port(port);
3700 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3702 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3704 /* Close bandwidth for all queues */
3705 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3706 ptxq = mvpp2_txq_phys(port->id, queue);
3707 mvpp2_write(port->priv,
3708 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3711 /* Set refill period to 1 usec, refill tokens
3712 * and bucket size to maximum
3714 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3715 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3716 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3717 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3718 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3719 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3720 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3721 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3723 /* Set MaximumLowLatencyPacketSize value to 256 */
3724 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3725 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3726 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3728 /* Enable Rx cache snoop */
3729 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3730 queue = port->rxqs[lrxq]->id;
3731 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3732 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3733 MVPP2_SNOOP_BUF_HDR_MASK;
3734 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3738 /* Enable/disable receiving packets */
3739 static void mvpp2_ingress_enable(struct mvpp2_port *port)
3744 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3745 queue = port->rxqs[lrxq]->id;
3746 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3747 val &= ~MVPP2_RXQ_DISABLE_MASK;
3748 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3752 static void mvpp2_ingress_disable(struct mvpp2_port *port)
3757 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3758 queue = port->rxqs[lrxq]->id;
3759 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3760 val |= MVPP2_RXQ_DISABLE_MASK;
3761 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3765 /* Enable transmit via physical egress queue
3766 * - HW starts take descriptors from DRAM
3768 static void mvpp2_egress_enable(struct mvpp2_port *port)
3772 int tx_port_num = mvpp2_egress_port(port);
3774 /* Enable all initialized TXs. */
3776 for (queue = 0; queue < txq_number; queue++) {
3777 struct mvpp2_tx_queue *txq = port->txqs[queue];
3779 if (txq->descs != NULL)
3780 qmap |= (1 << queue);
3783 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3784 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3787 /* Disable transmit via physical egress queue
3788 * - HW doesn't take descriptors from DRAM
3790 static void mvpp2_egress_disable(struct mvpp2_port *port)
3794 int tx_port_num = mvpp2_egress_port(port);
3796 /* Issue stop command for active channels only */
3797 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3798 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3799 MVPP2_TXP_SCHED_ENQ_MASK;
3801 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3802 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3804 /* Wait for all Tx activity to terminate. */
3807 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
3808 netdev_warn(port->dev,
3809 "Tx stop timed out, status=0x%08x\n",
3816 /* Check port TX Command register that all
3817 * Tx queues are stopped
3819 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3820 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3823 /* Rx descriptors helper methods */
3825 /* Get number of Rx descriptors occupied by received packets */
3827 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3829 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3831 return val & MVPP2_RXQ_OCCUPIED_MASK;
3834 /* Update Rx queue status with the number of occupied and available
3835 * Rx descriptor slots.
3838 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3839 int used_count, int free_count)
3841 /* Decrement the number of used descriptors and increment count
3842 * increment the number of free descriptors.
3844 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3846 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3849 /* Get pointer to next RX descriptor to be processed by SW */
3850 static inline struct mvpp2_rx_desc *
3851 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3853 int rx_desc = rxq->next_desc_to_proc;
3855 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3856 prefetch(rxq->descs + rxq->next_desc_to_proc);
3857 return rxq->descs + rx_desc;
3860 /* Set rx queue offset */
3861 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3862 int prxq, int offset)
3866 /* Convert offset from bytes to units of 32 bytes */
3867 offset = offset >> 5;
3869 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3870 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3873 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3874 MVPP2_RXQ_PACKET_OFFSET_MASK);
3876 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3879 /* Obtain BM cookie information from descriptor */
3880 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3881 struct mvpp2_rx_desc *rx_desc)
3883 int cpu = smp_processor_id();
3886 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3887 MVPP2_RXD_BM_POOL_ID_MASK) >>
3888 MVPP2_RXD_BM_POOL_ID_OFFS;
3890 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3891 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3894 /* Tx descriptors helper methods */
3896 /* Get number of Tx descriptors waiting to be transmitted by HW */
3897 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3898 struct mvpp2_tx_queue *txq)
3902 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3903 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3905 return val & MVPP2_TXQ_PENDING_MASK;
3908 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3909 static struct mvpp2_tx_desc *
3910 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3912 int tx_desc = txq->next_desc_to_proc;
3914 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3915 return txq->descs + tx_desc;
3918 /* Update HW with number of aggregated Tx descriptors to be sent */
3919 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3921 /* aggregated access - relevant TXQ number is written in TX desc */
3922 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3925 /* Get number of sent descriptors and decrement counter.
3926 * The number of sent descriptors is returned.
3929 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3930 struct mvpp2_tx_queue *txq)
3934 /* Reading status reg resets transmitted descriptor counter */
3935 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3937 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3938 MVPP2_TRANSMITTED_COUNT_OFFSET;
3941 static void mvpp2_txq_sent_counter_clear(void *arg)
3943 struct mvpp2_port *port = arg;
3946 for (queue = 0; queue < txq_number; queue++) {
3947 int id = port->txqs[queue]->id;
3949 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3953 /* Set max sizes for Tx queues */
3954 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3957 int txq, tx_port_num;
3959 mtu = port->pkt_size * 8;
3960 if (mtu > MVPP2_TXP_MTU_MAX)
3961 mtu = MVPP2_TXP_MTU_MAX;
3963 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3966 /* Indirect access to registers */
3967 tx_port_num = mvpp2_egress_port(port);
3968 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3971 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3972 val &= ~MVPP2_TXP_MTU_MAX;
3974 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3976 /* TXP token size and all TXQs token size must be larger that MTU */
3977 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3978 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3981 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3983 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3986 for (txq = 0; txq < txq_number; txq++) {
3987 val = mvpp2_read(port->priv,
3988 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3989 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3993 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3995 mvpp2_write(port->priv,
3996 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4002 /* Free Tx queue skbuffs */
4003 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4004 struct mvpp2_tx_queue *txq,
4005 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4009 for (i = 0; i < num; i++)
4010 mvpp2_txq_inc_get(txq_pcpu);
4013 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4016 int queue = fls(cause) - 1;
4018 return port->rxqs[queue];
4021 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4024 int queue = fls(cause) - 1;
4026 return port->txqs[queue];
4029 /* Rx/Tx queue initialization/cleanup methods */
4031 /* Allocate and initialize descriptors for aggr TXQ */
4032 static int mvpp2_aggr_txq_init(struct udevice *dev,
4033 struct mvpp2_tx_queue *aggr_txq,
4034 int desc_num, int cpu,
4039 /* Allocate memory for TX descriptors */
4040 aggr_txq->descs = buffer_loc.aggr_tx_descs;
4041 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
4042 if (!aggr_txq->descs)
4045 /* Make sure descriptor address is cache line size aligned */
4046 BUG_ON(aggr_txq->descs !=
4047 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4049 aggr_txq->last_desc = aggr_txq->size - 1;
4051 /* Aggr TXQ no reset WA */
4052 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4053 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4055 /* Set Tx descriptors queue starting address indirect
4058 if (priv->hw_version == MVPP21)
4059 txq_dma = aggr_txq->descs_dma;
4061 txq_dma = aggr_txq->descs_dma >>
4062 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4064 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
4065 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4070 /* Create a specified Rx queue */
4071 static int mvpp2_rxq_init(struct mvpp2_port *port,
4072 struct mvpp2_rx_queue *rxq)
4077 rxq->size = port->rx_ring_size;
4079 /* Allocate memory for RX descriptors */
4080 rxq->descs = buffer_loc.rx_descs;
4081 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
4085 BUG_ON(rxq->descs !=
4086 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4088 rxq->last_desc = rxq->size - 1;
4090 /* Zero occupied and non-occupied counters - direct access */
4091 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4093 /* Set Rx descriptors queue starting address - indirect access */
4094 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4095 if (port->priv->hw_version == MVPP21)
4096 rxq_dma = rxq->descs_dma;
4098 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4099 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
4100 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4101 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4104 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4106 /* Add number of descriptors ready for receiving packets */
4107 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4112 /* Push packets received by the RXQ to BM pool */
4113 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4114 struct mvpp2_rx_queue *rxq)
4118 rx_received = mvpp2_rxq_received(port, rxq->id);
4122 for (i = 0; i < rx_received; i++) {
4123 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4124 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
4126 mvpp2_pool_refill(port, bm,
4127 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4128 mvpp2_rxdesc_cookie_get(port, rx_desc));
4130 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4133 /* Cleanup Rx queue */
4134 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4135 struct mvpp2_rx_queue *rxq)
4137 mvpp2_rxq_drop_pkts(port, rxq);
4141 rxq->next_desc_to_proc = 0;
4144 /* Clear Rx descriptors queue starting address and size;
4145 * free descriptor number
4147 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4148 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4149 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4150 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4153 /* Create and initialize a Tx queue */
4154 static int mvpp2_txq_init(struct mvpp2_port *port,
4155 struct mvpp2_tx_queue *txq)
4158 int cpu, desc, desc_per_txq, tx_port_num;
4159 struct mvpp2_txq_pcpu *txq_pcpu;
4161 txq->size = port->tx_ring_size;
4163 /* Allocate memory for Tx descriptors */
4164 txq->descs = buffer_loc.tx_descs;
4165 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
4169 /* Make sure descriptor address is cache line size aligned */
4170 BUG_ON(txq->descs !=
4171 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4173 txq->last_desc = txq->size - 1;
4175 /* Set Tx descriptors queue starting address - indirect access */
4176 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4177 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
4178 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4179 MVPP2_TXQ_DESC_SIZE_MASK);
4180 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4181 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4182 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4183 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4184 val &= ~MVPP2_TXQ_PENDING_MASK;
4185 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4187 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4188 * for each existing TXQ.
4189 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4190 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4193 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4194 (txq->log_id * desc_per_txq);
4196 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4197 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4198 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
4200 /* WRR / EJP configuration - indirect access */
4201 tx_port_num = mvpp2_egress_port(port);
4202 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4204 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4205 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4206 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4207 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4208 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4210 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4211 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4214 for_each_present_cpu(cpu) {
4215 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4216 txq_pcpu->size = txq->size;
4222 /* Free allocated TXQ resources */
4223 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4224 struct mvpp2_tx_queue *txq)
4228 txq->next_desc_to_proc = 0;
4231 /* Set minimum bandwidth for disabled TXQs */
4232 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4234 /* Set Tx descriptors queue starting address and size */
4235 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4236 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4237 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4240 /* Cleanup Tx ports */
4241 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4243 struct mvpp2_txq_pcpu *txq_pcpu;
4244 int delay, pending, cpu;
4247 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4248 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4249 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4250 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4252 /* The napi queue has been stopped so wait for all packets
4253 * to be transmitted.
4257 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4258 netdev_warn(port->dev,
4259 "port %d: cleaning queue %d timed out\n",
4260 port->id, txq->log_id);
4266 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4269 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4270 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4272 for_each_present_cpu(cpu) {
4273 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4275 /* Release all packets */
4276 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4279 txq_pcpu->count = 0;
4280 txq_pcpu->txq_put_index = 0;
4281 txq_pcpu->txq_get_index = 0;
4285 /* Cleanup all Tx queues */
4286 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4288 struct mvpp2_tx_queue *txq;
4292 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4294 /* Reset Tx ports and delete Tx queues */
4295 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4296 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4298 for (queue = 0; queue < txq_number; queue++) {
4299 txq = port->txqs[queue];
4300 mvpp2_txq_clean(port, txq);
4301 mvpp2_txq_deinit(port, txq);
4304 mvpp2_txq_sent_counter_clear(port);
4306 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4307 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4310 /* Cleanup all Rx queues */
4311 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4315 for (queue = 0; queue < rxq_number; queue++)
4316 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4319 /* Init all Rx queues for port */
4320 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4324 for (queue = 0; queue < rxq_number; queue++) {
4325 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4332 mvpp2_cleanup_rxqs(port);
4336 /* Init all tx queues for port */
4337 static int mvpp2_setup_txqs(struct mvpp2_port *port)
4339 struct mvpp2_tx_queue *txq;
4342 for (queue = 0; queue < txq_number; queue++) {
4343 txq = port->txqs[queue];
4344 err = mvpp2_txq_init(port, txq);
4349 mvpp2_txq_sent_counter_clear(port);
4353 mvpp2_cleanup_txqs(port);
4358 static void mvpp2_link_event(struct mvpp2_port *port)
4360 struct phy_device *phydev = port->phy_dev;
4361 int status_change = 0;
4365 if ((port->speed != phydev->speed) ||
4366 (port->duplex != phydev->duplex)) {
4369 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4370 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4371 MVPP2_GMAC_CONFIG_GMII_SPEED |
4372 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4373 MVPP2_GMAC_AN_SPEED_EN |
4374 MVPP2_GMAC_AN_DUPLEX_EN);
4377 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4379 if (phydev->speed == SPEED_1000)
4380 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4381 else if (phydev->speed == SPEED_100)
4382 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4384 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4386 port->duplex = phydev->duplex;
4387 port->speed = phydev->speed;
4391 if (phydev->link != port->link) {
4392 if (!phydev->link) {
4397 port->link = phydev->link;
4401 if (status_change) {
4403 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4404 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4405 MVPP2_GMAC_FORCE_LINK_DOWN);
4406 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4407 mvpp2_egress_enable(port);
4408 mvpp2_ingress_enable(port);
4410 mvpp2_ingress_disable(port);
4411 mvpp2_egress_disable(port);
4416 /* Main RX/TX processing routines */
4418 /* Display more error info */
4419 static void mvpp2_rx_error(struct mvpp2_port *port,
4420 struct mvpp2_rx_desc *rx_desc)
4422 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4423 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
4425 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4426 case MVPP2_RXD_ERR_CRC:
4427 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
4430 case MVPP2_RXD_ERR_OVERRUN:
4431 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
4434 case MVPP2_RXD_ERR_RESOURCE:
4435 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
4441 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4442 static int mvpp2_rx_refill(struct mvpp2_port *port,
4443 struct mvpp2_bm_pool *bm_pool,
4444 u32 bm, dma_addr_t dma_addr)
4446 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
4450 /* Set hw internals when starting port */
4451 static void mvpp2_start_dev(struct mvpp2_port *port)
4453 switch (port->phy_interface) {
4454 case PHY_INTERFACE_MODE_RGMII:
4455 case PHY_INTERFACE_MODE_RGMII_ID:
4456 case PHY_INTERFACE_MODE_SGMII:
4457 mvpp2_gmac_max_rx_size_set(port);
4462 mvpp2_txp_max_tx_size_set(port);
4464 if (port->priv->hw_version == MVPP21)
4465 mvpp2_port_enable(port);
4467 gop_port_enable(port, 1);
4470 /* Set hw internals when stopping port */
4471 static void mvpp2_stop_dev(struct mvpp2_port *port)
4473 /* Stop new packets from arriving to RXQs */
4474 mvpp2_ingress_disable(port);
4476 mvpp2_egress_disable(port);
4478 if (port->priv->hw_version == MVPP21)
4479 mvpp2_port_disable(port);
4481 gop_port_enable(port, 0);
4484 static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
4486 struct phy_device *phy_dev;
4488 if (!port->init || port->link == 0) {
4489 phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
4490 dev, port->phy_interface);
4493 * If the phy doesn't match with any existing u-boot drivers the
4494 * phy framework will connect it to generic one which
4495 * uid == 0xffffffff. In this case act as if the phy wouldn't be
4496 * declared in dts. Otherwise in case of 3310 (for which the
4497 * driver doesn't exist) the link will not be correctly
4498 * detected. Removing phy entry from dts in case of 3310 is not
4499 * an option because it is required for the phy_fw_down
4503 phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
4504 netdev_warn(port->dev,
4505 "Marking phy as invalid, link will not be checked\n");
4506 /* set phy_addr to invalid value */
4507 port->phyaddr = PHY_MAX_ADDR;
4508 mvpp2_egress_enable(port);
4509 mvpp2_ingress_enable(port);
4514 port->phy_dev = phy_dev;
4516 netdev_err(port->dev, "cannot connect to phy\n");
4519 phy_dev->supported &= PHY_GBIT_FEATURES;
4520 phy_dev->advertising = phy_dev->supported;
4522 port->phy_dev = phy_dev;
4527 phy_config(phy_dev);
4528 phy_startup(phy_dev);
4530 printf("%s: No link\n", phy_dev->dev->name);
4534 mvpp2_egress_enable(port);
4535 mvpp2_ingress_enable(port);
4539 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4541 unsigned char mac_bcast[ETH_ALEN] = {
4542 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4545 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4547 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4550 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4551 port->dev_addr, true);
4553 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
4556 err = mvpp2_prs_def_flow(port);
4558 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4562 /* Allocate the Rx/Tx queues */
4563 err = mvpp2_setup_rxqs(port);
4565 netdev_err(port->dev, "cannot allocate Rx queues\n");
4569 err = mvpp2_setup_txqs(port);
4571 netdev_err(port->dev, "cannot allocate Tx queues\n");
4575 if (port->phyaddr < PHY_MAX_ADDR) {
4576 mvpp2_phy_connect(dev, port);
4577 mvpp2_link_event(port);
4579 mvpp2_egress_enable(port);
4580 mvpp2_ingress_enable(port);
4583 mvpp2_start_dev(port);
4588 /* No Device ops here in U-Boot */
4590 /* Driver initialization */
4592 static void mvpp2_port_power_up(struct mvpp2_port *port)
4594 struct mvpp2 *priv = port->priv;
4596 /* On PPv2.2 the GoP / interface configuration has already been done */
4597 if (priv->hw_version == MVPP21)
4598 mvpp2_port_mii_set(port);
4599 mvpp2_port_periodic_xon_disable(port);
4600 if (priv->hw_version == MVPP21)
4601 mvpp2_port_fc_adv_enable(port);
4602 mvpp2_port_reset(port);
4605 /* Initialize port HW */
4606 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4608 struct mvpp2 *priv = port->priv;
4609 struct mvpp2_txq_pcpu *txq_pcpu;
4610 int queue, cpu, err;
4612 if (port->first_rxq + rxq_number >
4613 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4617 mvpp2_egress_disable(port);
4618 if (priv->hw_version == MVPP21)
4619 mvpp2_port_disable(port);
4621 gop_port_enable(port, 0);
4623 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4628 /* Associate physical Tx queues to this port and initialize.
4629 * The mapping is predefined.
4631 for (queue = 0; queue < txq_number; queue++) {
4632 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4633 struct mvpp2_tx_queue *txq;
4635 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4639 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4644 txq->id = queue_phy_id;
4645 txq->log_id = queue;
4646 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4647 for_each_present_cpu(cpu) {
4648 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4649 txq_pcpu->cpu = cpu;
4652 port->txqs[queue] = txq;
4655 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4660 /* Allocate and initialize Rx queue for this port */
4661 for (queue = 0; queue < rxq_number; queue++) {
4662 struct mvpp2_rx_queue *rxq;
4664 /* Map physical Rx queue to port's logical Rx queue */
4665 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4668 /* Map this Rx queue to a physical queue */
4669 rxq->id = port->first_rxq + queue;
4670 rxq->port = port->id;
4671 rxq->logic_rxq = queue;
4673 port->rxqs[queue] = rxq;
4677 /* Create Rx descriptor rings */
4678 for (queue = 0; queue < rxq_number; queue++) {
4679 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4681 rxq->size = port->rx_ring_size;
4682 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4683 rxq->time_coal = MVPP2_RX_COAL_USEC;
4686 mvpp2_ingress_disable(port);
4688 /* Port default configuration */
4689 mvpp2_defaults_set(port);
4691 /* Port's classifier configuration */
4692 mvpp2_cls_oversize_rxq_set(port);
4693 mvpp2_cls_port_config(port);
4695 /* Provide an initial Rx packet size */
4696 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4698 /* Initialize pools for swf */
4699 err = mvpp2_swf_bm_pool_init(port);
4706 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
4708 int port_node = dev_of_offset(dev);
4709 const char *phy_mode_str;
4716 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
4720 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
4722 dev_err(&pdev->dev, "could not find phy address\n");
4725 parent = fdt_parent_offset(gd->fdt_blob, phy_node);
4726 ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
4731 /* phy_addr is set to invalid value */
4732 phyaddr = PHY_MAX_ADDR;
4735 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
4737 phy_mode = phy_get_interface_by_name(phy_mode_str);
4738 if (phy_mode == -1) {
4739 dev_err(&pdev->dev, "incorrect phy mode\n");
4743 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4745 dev_err(&pdev->dev, "missing port-id value\n");
4749 #if CONFIG_IS_ENABLED(DM_GPIO)
4750 gpio_request_by_name(dev, "phy-reset-gpios", 0,
4751 &port->phy_reset_gpio, GPIOD_IS_OUT);
4752 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
4753 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
4758 * Not sure if this DT property "phy-speed" will get accepted, so
4759 * this might change later
4761 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
4762 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
4766 if (port->priv->hw_version == MVPP21)
4767 port->first_rxq = port->id * rxq_number;
4769 port->first_rxq = port->id * port->priv->max_port_rxqs;
4770 port->phy_interface = phy_mode;
4771 port->phyaddr = phyaddr;
4776 #if CONFIG_IS_ENABLED(DM_GPIO)
4777 /* Port GPIO initialization */
4778 static void mvpp2_gpio_init(struct mvpp2_port *port)
4780 if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
4781 dm_gpio_set_value(&port->phy_reset_gpio, 1);
4783 dm_gpio_set_value(&port->phy_reset_gpio, 0);
4786 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
4787 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
4791 /* Ports initialization */
4792 static int mvpp2_port_probe(struct udevice *dev,
4793 struct mvpp2_port *port,
4799 port->tx_ring_size = MVPP2_MAX_TXD;
4800 port->rx_ring_size = MVPP2_MAX_RXD;
4802 err = mvpp2_port_init(dev, port);
4804 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
4807 mvpp2_port_power_up(port);
4809 #if CONFIG_IS_ENABLED(DM_GPIO)
4810 mvpp2_gpio_init(port);
4813 priv->port_list[port->id] = port;
4818 /* Initialize decoding windows */
4819 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4825 for (i = 0; i < 6; i++) {
4826 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4827 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4830 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4835 for (i = 0; i < dram->num_cs; i++) {
4836 const struct mbus_dram_window *cs = dram->cs + i;
4838 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4839 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4840 dram->mbus_dram_target_id);
4842 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4843 (cs->size - 1) & 0xffff0000);
4845 win_enable |= (1 << i);
4848 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4851 /* Initialize Rx FIFO's */
4852 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4856 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4857 if (priv->hw_version == MVPP22) {
4860 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4861 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4863 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4864 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4865 } else if (port == 1) {
4867 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4868 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4870 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4871 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4874 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4875 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4877 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4878 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4881 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4882 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4883 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4884 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4888 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4889 MVPP2_RX_FIFO_PORT_MIN_PKT);
4890 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4893 /* Initialize Tx FIFO's */
4894 static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4898 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4899 /* Port 0 supports 10KB TX FIFO */
4901 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4902 MVPP22_TX_FIFO_SIZE_MASK;
4904 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4905 MVPP22_TX_FIFO_SIZE_MASK;
4907 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4911 static void mvpp2_axi_init(struct mvpp2 *priv)
4913 u32 val, rdval, wrval;
4915 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4917 /* AXI Bridge Configuration */
4919 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4920 << MVPP22_AXI_ATTR_CACHE_OFFS;
4921 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4922 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4924 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4925 << MVPP22_AXI_ATTR_CACHE_OFFS;
4926 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4927 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4930 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4931 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4934 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4935 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4936 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4937 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4940 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4941 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4943 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4944 << MVPP22_AXI_CODE_CACHE_OFFS;
4945 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4946 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4947 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4948 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4950 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4951 << MVPP22_AXI_CODE_CACHE_OFFS;
4952 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4953 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4955 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4957 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4958 << MVPP22_AXI_CODE_CACHE_OFFS;
4959 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4960 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4962 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
4965 /* Initialize network controller common part HW */
4966 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
4968 const struct mbus_dram_target_info *dram_target_info;
4972 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4973 if ((rxq_number > priv->max_port_rxqs) ||
4974 (txq_number > MVPP2_MAX_TXQ)) {
4975 dev_err(&pdev->dev, "invalid queue size parameter\n");
4979 if (priv->hw_version == MVPP22)
4980 mvpp2_axi_init(priv);
4982 /* MBUS windows configuration */
4983 dram_target_info = mvebu_mbus_dram_info();
4984 if (dram_target_info)
4985 mvpp2_conf_mbus_windows(dram_target_info, priv);
4988 if (priv->hw_version == MVPP21) {
4989 /* Disable HW PHY polling */
4990 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4991 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4992 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4994 /* Enable HW PHY polling */
4995 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4996 val |= MVPP22_SMI_POLLING_EN;
4997 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5000 /* Allocate and initialize aggregated TXQs */
5001 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
5002 sizeof(struct mvpp2_tx_queue),
5004 if (!priv->aggr_txqs)
5007 for_each_present_cpu(i) {
5008 priv->aggr_txqs[i].id = i;
5009 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5010 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5011 MVPP2_AGGR_TXQ_SIZE, i, priv);
5017 mvpp2_rx_fifo_init(priv);
5020 if (priv->hw_version == MVPP22)
5021 mvpp2_tx_fifo_init(priv);
5023 if (priv->hw_version == MVPP21)
5024 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5025 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5027 /* Allow cache snoop when transmiting packets */
5028 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5030 /* Buffer Manager initialization */
5031 err = mvpp2_bm_init(dev, priv);
5035 /* Parser default initialization */
5036 err = mvpp2_prs_default_init(dev, priv);
5040 /* Classifier default initialization */
5041 mvpp2_cls_init(priv);
5046 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5048 struct mvpp2_port *port = dev_get_priv(dev);
5049 struct mvpp2_rx_desc *rx_desc;
5050 struct mvpp2_bm_pool *bm_pool;
5051 dma_addr_t dma_addr;
5053 int pool, rx_bytes, err;
5055 struct mvpp2_rx_queue *rxq;
5058 if (port->phyaddr < PHY_MAX_ADDR)
5059 if (!port->phy_dev->link)
5062 /* Process RX packets */
5063 rxq = port->rxqs[0];
5065 /* Get number of received packets and clamp the to-do */
5066 rx_received = mvpp2_rxq_received(port, rxq->id);
5068 /* Return if no packets are received */
5072 rx_desc = mvpp2_rxq_next_desc_get(rxq);
5073 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5074 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5075 rx_bytes -= MVPP2_MH_SIZE;
5076 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
5078 bm = mvpp2_bm_cookie_build(port, rx_desc);
5079 pool = mvpp2_bm_cookie_pool_get(bm);
5080 bm_pool = &port->priv->bm_pools[pool];
5082 /* In case of an error, release the requested buffer pointer
5083 * to the Buffer Manager. This request process is controlled
5084 * by the hardware, and the information about the buffer is
5085 * comprised by the RX descriptor.
5087 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5088 mvpp2_rx_error(port, rx_desc);
5089 /* Return the buffer to the pool */
5090 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
5094 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
5096 netdev_err(port->dev, "failed to refill BM pools\n");
5100 /* Update Rx queue management counters */
5102 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5104 /* give packet to stack - skip on first n bytes */
5105 data = (u8 *)dma_addr + 2 + 32;
5111 * No cache invalidation needed here, since the rx_buffer's are
5112 * located in a uncached memory region
5119 static int mvpp2_send(struct udevice *dev, void *packet, int length)
5121 struct mvpp2_port *port = dev_get_priv(dev);
5122 struct mvpp2_tx_queue *txq, *aggr_txq;
5123 struct mvpp2_tx_desc *tx_desc;
5127 if (port->phyaddr < PHY_MAX_ADDR)
5128 if (!port->phy_dev->link)
5131 txq = port->txqs[0];
5132 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5134 /* Get a descriptor for the first part of the packet */
5135 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5136 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5137 mvpp2_txdesc_size_set(port, tx_desc, length);
5138 mvpp2_txdesc_offset_set(port, tx_desc,
5139 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5140 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5141 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
5142 /* First and Last descriptor */
5143 mvpp2_txdesc_cmd_set(port, tx_desc,
5144 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5145 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
5148 flush_dcache_range((unsigned long)packet,
5149 (unsigned long)packet + ALIGN(length, PKTALIGN));
5151 /* Enable transmit */
5153 mvpp2_aggr_txq_pend_desc_add(port, 1);
5155 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5159 if (timeout++ > 10000) {
5160 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5163 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5168 if (timeout++ > 10000) {
5169 printf("timeout: packet not sent\n");
5172 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5178 static int mvpp2_start(struct udevice *dev)
5180 struct eth_pdata *pdata = dev_get_platdata(dev);
5181 struct mvpp2_port *port = dev_get_priv(dev);
5183 /* Load current MAC address */
5184 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5186 /* Reconfigure parser accept the original MAC address */
5187 mvpp2_prs_update_mac_da(port, port->dev_addr);
5189 switch (port->phy_interface) {
5190 case PHY_INTERFACE_MODE_RGMII:
5191 case PHY_INTERFACE_MODE_RGMII_ID:
5192 case PHY_INTERFACE_MODE_SGMII:
5193 mvpp2_port_power_up(port);
5198 mvpp2_open(dev, port);
5203 static void mvpp2_stop(struct udevice *dev)
5205 struct mvpp2_port *port = dev_get_priv(dev);
5207 mvpp2_stop_dev(port);
5208 mvpp2_cleanup_rxqs(port);
5209 mvpp2_cleanup_txqs(port);
5212 static int mvpp2_write_hwaddr(struct udevice *dev)
5214 struct mvpp2_port *port = dev_get_priv(dev);
5216 return mvpp2_prs_update_mac_da(port, port->dev_addr);
5219 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
5221 writel(port->phyaddr, port->priv->iface_base +
5222 MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
5227 static int mvpp2_base_probe(struct udevice *dev)
5229 struct mvpp2 *priv = dev_get_priv(dev);
5234 /* Save hw-version */
5235 priv->hw_version = dev_get_driver_data(dev);
5238 * U-Boot special buffer handling:
5240 * Allocate buffer area for descs and rx_buffers. This is only
5241 * done once for all interfaces. As only one interface can
5242 * be active. Make this area DMA-safe by disabling the D-cache
5245 /* Align buffer area for descs and rx_buffers to 1MiB */
5246 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
5247 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5248 BD_SPACE, DCACHE_OFF);
5250 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5251 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
5253 buffer_loc.tx_descs =
5254 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
5255 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
5257 buffer_loc.rx_descs =
5258 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
5259 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
5261 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5262 buffer_loc.bm_pool[i] =
5263 (unsigned long *)((unsigned long)bd_space + size);
5264 if (priv->hw_version == MVPP21)
5265 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5267 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
5270 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
5271 buffer_loc.rx_buffer[i] =
5272 (unsigned long *)((unsigned long)bd_space + size);
5273 size += RX_BUFFER_SIZE;
5276 /* Clear the complete area so that all descriptors are cleared */
5277 memset(bd_space, 0, size);
5279 /* Save base addresses for later use */
5280 priv->base = (void *)devfdt_get_addr_index(dev, 0);
5281 if (IS_ERR(priv->base))
5282 return PTR_ERR(priv->base);
5284 if (priv->hw_version == MVPP21) {
5285 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
5286 if (IS_ERR(priv->lms_base))
5287 return PTR_ERR(priv->lms_base);
5289 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
5290 if (IS_ERR(priv->iface_base))
5291 return PTR_ERR(priv->iface_base);
5293 /* Store common base addresses for all ports */
5294 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5295 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5296 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
5299 if (priv->hw_version == MVPP21)
5300 priv->max_port_rxqs = 8;
5302 priv->max_port_rxqs = 32;
5307 static int mvpp2_probe(struct udevice *dev)
5309 struct mvpp2_port *port = dev_get_priv(dev);
5310 struct mvpp2 *priv = dev_get_priv(dev->parent);
5313 /* Only call the probe function for the parent once */
5314 if (!priv->probe_done)
5315 err = mvpp2_base_probe(dev->parent);
5319 err = phy_info_parse(dev, port);
5324 * We need the port specific io base addresses at this stage, since
5325 * gop_port_init() accesses these registers
5327 if (priv->hw_version == MVPP21) {
5328 int priv_common_regs_num = 2;
5330 port->base = (void __iomem *)devfdt_get_addr_index(
5331 dev->parent, priv_common_regs_num + port->id);
5332 if (IS_ERR(port->base))
5333 return PTR_ERR(port->base);
5335 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5337 if (port->id == -1) {
5338 dev_err(&pdev->dev, "missing gop-port-id value\n");
5342 port->base = priv->iface_base + MVPP22_PORT_BASE +
5343 port->gop_id * MVPP22_PORT_OFFSET;
5345 /* Set phy address of the port */
5346 if (port->phyaddr < PHY_MAX_ADDR)
5347 mvpp22_smi_phy_addr_cfg(port);
5350 gop_port_init(port);
5353 if (!priv->probe_done) {
5354 /* Initialize network controller */
5355 err = mvpp2_init(dev, priv);
5357 dev_err(&pdev->dev, "failed to initialize controller\n");
5360 priv->num_ports = 0;
5361 priv->probe_done = 1;
5364 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5368 if (priv->hw_version == MVPP22) {
5369 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5370 port->phy_interface);
5372 /* Netcomplex configurations for all ports */
5373 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5374 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5381 * Empty BM pool and stop its activity before the OS is started
5383 static int mvpp2_remove(struct udevice *dev)
5385 struct mvpp2_port *port = dev_get_priv(dev);
5386 struct mvpp2 *priv = port->priv;
5391 if (priv->num_ports)
5394 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5395 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5400 static const struct eth_ops mvpp2_ops = {
5401 .start = mvpp2_start,
5405 .write_hwaddr = mvpp2_write_hwaddr
5408 static struct driver mvpp2_driver = {
5411 .probe = mvpp2_probe,
5412 .remove = mvpp2_remove,
5414 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
5415 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5416 .flags = DM_FLAG_ACTIVE_DMA,
5420 * Use a MISC device to bind the n instances (child nodes) of the
5421 * network base controller in UCLASS_ETH.
5423 static int mvpp2_base_bind(struct udevice *parent)
5425 const void *blob = gd->fdt_blob;
5426 int node = dev_of_offset(parent);
5427 struct uclass_driver *drv;
5428 struct udevice *dev;
5429 struct eth_pdata *plat;
5435 /* Lookup eth driver */
5436 drv = lists_uclass_lookup(UCLASS_ETH);
5438 puts("Cannot find eth driver\n");
5442 base_id_add = base_id;
5444 fdt_for_each_subnode(subnode, blob, node) {
5445 /* Increment base_id for all subnodes, also the disabled ones */
5448 /* Skip disabled ports */
5449 if (!fdtdec_get_is_enabled(blob, subnode))
5452 plat = calloc(1, sizeof(*plat));
5456 id = fdtdec_get_int(blob, subnode, "port-id", -1);
5459 name = calloc(1, 16);
5464 sprintf(name, "mvpp2-%d", id);
5466 /* Create child device UCLASS_ETH and bind it */
5467 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
5468 dev_set_of_offset(dev, subnode);
5474 static const struct udevice_id mvpp2_ids[] = {
5476 .compatible = "marvell,armada-375-pp2",
5480 .compatible = "marvell,armada-7k-pp22",
5486 U_BOOT_DRIVER(mvpp2_base) = {
5487 .name = "mvpp2_base",
5489 .of_match = mvpp2_ids,
5490 .bind = mvpp2_base_bind,
5491 .priv_auto_alloc_size = sizeof(struct mvpp2),