2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
19 #include <asm/cache.h>
20 #include <dm/device-internal.h>
21 #include <dm/device_compat.h>
22 #include <dm/devres.h>
29 #include <linux/err.h>
30 #include <linux/errno.h>
34 #include <asm/arch/cpu.h>
35 #include <asm/arch/soc.h>
36 #include <linux/compat.h>
37 #include <linux/mbus.h>
38 #include <asm-generic/gpio.h>
39 #include <fdt_support.h>
40 #include <linux/mdio.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 #define __verify_pcpu_ptr(ptr) \
46 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
50 #define VERIFY_PERCPU_PTR(__p) \
52 __verify_pcpu_ptr(__p); \
53 (typeof(*(__p)) __kernel __force *)(__p); \
56 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
57 #define smp_processor_id() 0
58 #define num_present_cpus() 1
59 #define for_each_present_cpu(cpu) \
60 for ((cpu) = 0; (cpu) < 1; (cpu)++)
62 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
64 #define CONFIG_NR_CPUS 1
66 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
67 #define WRAP (2 + ETH_HLEN + 4 + 32)
69 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
71 /* RX Fifo Registers */
72 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
73 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
74 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
75 #define MVPP2_RX_FIFO_INIT_REG 0x64
77 /* RX DMA Top Registers */
78 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
79 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
80 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
81 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
82 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
83 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
84 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
85 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
86 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
87 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
88 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
89 #define MVPP2_RXQ_POOL_LONG_OFFS 24
90 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
91 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
92 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
93 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
94 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
96 /* Parser Registers */
97 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
98 #define MVPP2_PRS_PORT_LU_MAX 0xf
99 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
100 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
101 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
102 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
103 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
104 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
105 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
106 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
107 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
108 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
109 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
110 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
111 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
112 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
113 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
115 /* Classifier Registers */
116 #define MVPP2_CLS_MODE_REG 0x1800
117 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
118 #define MVPP2_CLS_PORT_WAY_REG 0x1810
119 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
120 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
121 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
122 #define MVPP2_CLS_LKP_TBL_REG 0x1818
123 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
124 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
125 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
126 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
127 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
128 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
129 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
130 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
131 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
132 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
133 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
134 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
136 /* Descriptor Manager Top Registers */
137 #define MVPP2_RXQ_NUM_REG 0x2040
138 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
139 #define MVPP22_DESC_ADDR_OFFS 8
140 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
141 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
142 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
143 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
144 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
145 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
146 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
147 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
148 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
149 #define MVPP2_RXQ_THRESH_REG 0x204c
150 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
151 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
152 #define MVPP2_RXQ_INDEX_REG 0x2050
153 #define MVPP2_TXQ_NUM_REG 0x2080
154 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
155 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
156 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
157 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
158 #define MVPP2_TXQ_THRESH_REG 0x2094
159 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
160 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
161 #define MVPP2_TXQ_INDEX_REG 0x2098
162 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
163 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
164 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
165 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
166 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
167 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
168 #define MVPP2_TXQ_PENDING_REG 0x20a0
169 #define MVPP2_TXQ_PENDING_MASK 0x3fff
170 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
171 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
172 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
173 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
174 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
175 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
176 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
177 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
178 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
179 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
180 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
181 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
182 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
183 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
184 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
185 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
186 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
188 /* MBUS bridge registers */
189 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
190 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
191 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
192 #define MVPP2_BASE_ADDR_ENABLE 0x4060
194 /* AXI Bridge Registers */
195 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
196 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
197 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
198 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
199 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
200 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
201 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
202 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
203 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
204 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
205 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
206 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
208 /* Values for AXI Bridge registers */
209 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
210 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
212 #define MVPP22_AXI_CODE_CACHE_OFFS 0
213 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
215 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
216 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
217 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
219 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
220 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
222 /* Interrupt Cause and Mask registers */
223 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
224 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
226 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
227 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
228 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
229 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
231 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
232 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
234 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
235 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
236 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
237 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
239 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
240 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
241 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
242 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
243 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
244 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
245 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
246 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
247 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
248 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
249 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
250 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
251 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
252 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
253 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
254 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
255 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
256 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
258 /* Buffer Manager registers */
259 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
260 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
261 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
262 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
263 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
264 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
265 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
266 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
267 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
268 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
269 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
270 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
271 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
272 #define MVPP2_BM_START_MASK BIT(0)
273 #define MVPP2_BM_STOP_MASK BIT(1)
274 #define MVPP2_BM_STATE_MASK BIT(4)
275 #define MVPP2_BM_LOW_THRESH_OFFS 8
276 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
277 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
278 MVPP2_BM_LOW_THRESH_OFFS)
279 #define MVPP2_BM_HIGH_THRESH_OFFS 16
280 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
281 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
282 MVPP2_BM_HIGH_THRESH_OFFS)
283 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
284 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
285 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
286 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
287 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
288 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
289 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
290 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
291 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
292 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
293 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
294 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
295 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
296 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
297 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
298 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
299 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
300 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
301 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
302 #define MVPP21_BM_MC_RLS_REG 0x64c4
303 #define MVPP2_BM_MC_ID_MASK 0xfff
304 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
305 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
306 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
307 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
308 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
309 #define MVPP22_BM_MC_RLS_REG 0x64d4
310 #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
311 #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
313 /* TX Scheduler registers */
314 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
315 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
316 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
317 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
318 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
319 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
320 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
321 #define MVPP2_TXP_MTU_MAX 0x7FFFF
322 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
323 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
324 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
325 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
326 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
327 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
328 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
329 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
330 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
331 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
332 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
333 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
334 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
335 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
337 /* TX general registers */
338 #define MVPP2_TX_SNOOP_REG 0x8800
339 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
340 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
343 #define MVPP2_SRC_ADDR_MIDDLE 0x24
344 #define MVPP2_SRC_ADDR_HIGH 0x28
345 #define MVPP2_PHY_AN_CFG0_REG 0x34
346 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
347 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
348 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
350 /* Per-port registers */
351 #define MVPP2_GMAC_CTRL_0_REG 0x0
352 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
353 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
354 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
355 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
356 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
357 #define MVPP2_GMAC_CTRL_1_REG 0x4
358 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
359 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
360 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
361 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
362 #define MVPP2_GMAC_SA_LOW_OFFS 7
363 #define MVPP2_GMAC_CTRL_2_REG 0x8
364 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
365 #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
366 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
367 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
368 #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
369 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
370 #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
371 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
372 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
373 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
374 #define MVPP2_GMAC_EN_PCS_AN BIT(2)
375 #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
376 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
377 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
378 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
379 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
380 #define MVPP2_GMAC_EN_FC_AN BIT(11)
381 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
382 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
383 #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
384 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
385 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
386 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
387 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
388 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
389 #define MVPP2_GMAC_CTRL_4_REG 0x90
390 #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
391 #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
392 #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
393 #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
396 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
397 * relative to port->base.
400 /* Port Mac Control0 */
401 #define MVPP22_XLG_CTRL0_REG 0x100
402 #define MVPP22_XLG_PORT_EN BIT(0)
403 #define MVPP22_XLG_MAC_RESETN BIT(1)
404 #define MVPP22_XLG_RX_FC_EN BIT(7)
405 #define MVPP22_XLG_MIBCNT_DIS BIT(13)
406 /* Port Mac Control1 */
407 #define MVPP22_XLG_CTRL1_REG 0x104
408 #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
409 #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
410 /* Port Interrupt Mask */
411 #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
412 #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
413 /* Port Mac Control3 */
414 #define MVPP22_XLG_CTRL3_REG 0x11c
415 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
416 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
417 #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
418 /* Port Mac Control4 */
419 #define MVPP22_XLG_CTRL4_REG 0x184
420 #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
421 #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
422 #define MVPP22_XLG_MODE_DMA_1G BIT(12)
423 #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
427 /* Global Configuration 0 */
428 #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
429 #define MVPP22_XPCS_PCSRESET BIT(0)
430 #define MVPP22_XPCS_PCSMODE_OFFS 3
431 #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
432 MVPP22_XPCS_PCSMODE_OFFS)
433 #define MVPP22_XPCS_LANEACTIVE_OFFS 5
434 #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
435 MVPP22_XPCS_LANEACTIVE_OFFS)
439 #define PCS40G_COMMON_CONTROL 0x14
440 #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
442 #define PCS_CLOCK_RESET 0x14c
443 #define TX_SD_CLK_RESET_MASK BIT(0)
444 #define RX_SD_CLK_RESET_MASK BIT(1)
445 #define MAC_CLK_RESET_MASK BIT(2)
446 #define CLK_DIVISION_RATIO_OFFS 4
447 #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
448 #define CLK_DIV_PHASE_SET_MASK BIT(11)
450 /* System Soft Reset 1 */
451 #define GOP_SOFT_RESET_1_REG 0x108
452 #define NETC_GOP_SOFT_RESET_OFFS 6
453 #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
454 NETC_GOP_SOFT_RESET_OFFS)
456 /* Ports Control 0 */
457 #define NETCOMP_PORTS_CONTROL_0_REG 0x110
458 #define NETC_BUS_WIDTH_SELECT_OFFS 1
459 #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
460 NETC_BUS_WIDTH_SELECT_OFFS)
461 #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
462 #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
463 NETC_GIG_RX_DATA_SAMPLE_OFFS)
464 #define NETC_CLK_DIV_PHASE_OFFS 31
465 #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
466 /* Ports Control 1 */
467 #define NETCOMP_PORTS_CONTROL_1_REG 0x114
468 #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
469 #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
470 NETC_PORTS_ACTIVE_OFFSET(p))
471 #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
472 #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
473 NETC_PORT_GIG_RF_RESET_OFFS(p))
474 #define NETCOMP_CONTROL_0_REG 0x120
475 #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
476 #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
477 NETC_GBE_PORT0_SGMII_MODE_OFFS)
478 #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
479 #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
480 NETC_GBE_PORT1_SGMII_MODE_OFFS)
481 #define NETC_GBE_PORT1_MII_MODE_OFFS 2
482 #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
483 NETC_GBE_PORT1_MII_MODE_OFFS)
485 #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
486 #define MVPP22_SMI_POLLING_EN BIT(10)
488 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
491 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
493 /* Descriptor ring Macros */
494 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
495 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
497 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
498 #define MVPP22_SMI 0x1200
500 /* Additional PPv2.2 offsets */
501 #define MVPP22_MPCS 0x007000
502 #define MVPP22_XPCS 0x007400
503 #define MVPP22_PORT_BASE 0x007e00
504 #define MVPP22_PORT_OFFSET 0x001000
505 #define MVPP22_RFU1 0x318000
507 /* Maximum number of ports */
508 #define MVPP22_GOP_MAC_NUM 4
510 /* Sets the field located at the specified in data */
511 #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
512 #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
513 #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
516 enum mv_netc_topology {
517 MV_NETC_GE_MAC2_SGMII = BIT(0),
518 MV_NETC_GE_MAC3_SGMII = BIT(1),
519 MV_NETC_GE_MAC3_RGMII = BIT(2),
524 MV_NETC_SECOND_PHASE,
527 enum mv_netc_sgmii_xmi_mode {
532 enum mv_netc_mii_mode {
542 /* Various constants */
545 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
546 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
547 #define MVPP2_RX_COAL_PKTS 32
548 #define MVPP2_RX_COAL_USEC 100
550 /* The two bytes Marvell header. Either contains a special value used
551 * by Marvell switches when a specific hardware mode is enabled (not
552 * supported by this driver) or is filled automatically by zeroes on
553 * the RX side. Those two bytes being at the front of the Ethernet
554 * header, they allow to have the IP header aligned on a 4 bytes
555 * boundary automatically: the hardware skips those two bytes on its
558 #define MVPP2_MH_SIZE 2
559 #define MVPP2_ETH_TYPE_LEN 2
560 #define MVPP2_PPPOE_HDR_SIZE 8
561 #define MVPP2_VLAN_TAG_LEN 4
563 /* Lbtd 802.3 type */
564 #define MVPP2_IP_LBDT_TYPE 0xfffa
566 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
567 #define MVPP2_TX_CSUM_MAX_SIZE 9800
569 /* Timeout constants */
570 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
571 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
573 #define MVPP2_TX_MTU_MAX 0x7ffff
575 /* Maximum number of T-CONTs of PON port */
576 #define MVPP2_MAX_TCONT 16
578 /* Maximum number of supported ports */
579 #define MVPP2_MAX_PORTS 4
581 /* Maximum number of TXQs used by single port */
582 #define MVPP2_MAX_TXQ 8
584 /* Default number of TXQs in use */
585 #define MVPP2_DEFAULT_TXQ 1
587 /* Default number of RXQs in use */
588 #define MVPP2_DEFAULT_RXQ 1
589 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
591 /* Max number of Rx descriptors */
592 #define MVPP2_MAX_RXD 16
594 /* Max number of Tx descriptors */
595 #define MVPP2_MAX_TXD 16
597 /* Amount of Tx descriptors that can be reserved at once by CPU */
598 #define MVPP2_CPU_DESC_CHUNK 16
600 /* Max number of Tx descriptors in each aggregated queue */
601 #define MVPP2_AGGR_TXQ_SIZE 16
603 /* Descriptor aligned size */
604 #define MVPP2_DESC_ALIGNED_SIZE 32
606 /* Descriptor alignment mask */
607 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
609 /* RX FIFO constants */
610 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
611 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
612 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
613 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
614 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
615 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
616 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
617 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
618 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
620 /* TX general registers */
621 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
622 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
624 /* TX FIFO constants */
625 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
626 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
628 /* RX buffer constants */
629 #define MVPP2_SKB_SHINFO_SIZE \
632 #define MVPP2_RX_PKT_SIZE(mtu) \
633 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
634 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
636 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
637 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
638 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
639 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
641 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
643 /* IPv6 max L3 address size */
644 #define MVPP2_MAX_L3_ADDR_SIZE 16
647 #define MVPP2_F_LOOPBACK BIT(0)
649 /* Marvell tag types */
650 enum mvpp2_tag_type {
651 MVPP2_TAG_TYPE_NONE = 0,
652 MVPP2_TAG_TYPE_MH = 1,
653 MVPP2_TAG_TYPE_DSA = 2,
654 MVPP2_TAG_TYPE_EDSA = 3,
655 MVPP2_TAG_TYPE_VLAN = 4,
656 MVPP2_TAG_TYPE_LAST = 5
659 /* Parser constants */
660 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
661 #define MVPP2_PRS_TCAM_WORDS 6
662 #define MVPP2_PRS_SRAM_WORDS 4
663 #define MVPP2_PRS_FLOW_ID_SIZE 64
664 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
665 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
666 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
667 #define MVPP2_PRS_IPV4_HEAD 0x40
668 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
669 #define MVPP2_PRS_IPV4_MC 0xe0
670 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
671 #define MVPP2_PRS_IPV4_BC_MASK 0xff
672 #define MVPP2_PRS_IPV4_IHL 0x5
673 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
674 #define MVPP2_PRS_IPV6_MC 0xff
675 #define MVPP2_PRS_IPV6_MC_MASK 0xff
676 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
677 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
678 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
679 #define MVPP2_PRS_DBL_VLANS_MAX 100
682 * - lookup ID - 4 bits
684 * - additional information - 1 byte
685 * - header data - 8 bytes
686 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
688 #define MVPP2_PRS_AI_BITS 8
689 #define MVPP2_PRS_PORT_MASK 0xff
690 #define MVPP2_PRS_LU_MASK 0xf
691 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
692 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
693 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
694 (((offs) * 2) - ((offs) % 2) + 2)
695 #define MVPP2_PRS_TCAM_AI_BYTE 16
696 #define MVPP2_PRS_TCAM_PORT_BYTE 17
697 #define MVPP2_PRS_TCAM_LU_BYTE 20
698 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
699 #define MVPP2_PRS_TCAM_INV_WORD 5
700 /* Tcam entries ID */
701 #define MVPP2_PE_DROP_ALL 0
702 #define MVPP2_PE_FIRST_FREE_TID 1
703 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
704 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
705 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
706 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
707 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
708 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
709 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
710 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
711 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
712 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
713 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
714 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
715 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
716 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
717 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
718 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
719 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
720 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
721 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
722 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
723 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
724 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
725 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
726 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
727 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
730 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
732 #define MVPP2_PRS_SRAM_RI_OFFS 0
733 #define MVPP2_PRS_SRAM_RI_WORD 0
734 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
735 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
736 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
737 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
738 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
739 #define MVPP2_PRS_SRAM_UDF_OFFS 73
740 #define MVPP2_PRS_SRAM_UDF_BITS 8
741 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
742 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
743 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
744 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
745 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
746 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
747 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
748 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
749 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
750 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
751 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
752 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
753 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
754 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
755 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
756 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
757 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
758 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
759 #define MVPP2_PRS_SRAM_AI_OFFS 90
760 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
761 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
762 #define MVPP2_PRS_SRAM_AI_MASK 0xff
763 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
764 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
765 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
766 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
768 /* Sram result info bits assignment */
769 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
770 #define MVPP2_PRS_RI_DSA_MASK 0x2
771 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
772 #define MVPP2_PRS_RI_VLAN_NONE 0x0
773 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
774 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
775 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
776 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
777 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
778 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
779 #define MVPP2_PRS_RI_L2_UCAST 0x0
780 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
781 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
782 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
783 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
784 #define MVPP2_PRS_RI_L3_UN 0x0
785 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
786 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
787 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
788 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
789 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
790 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
791 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
792 #define MVPP2_PRS_RI_L3_UCAST 0x0
793 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
794 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
795 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
796 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
797 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
798 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
799 #define MVPP2_PRS_RI_L4_TCP BIT(22)
800 #define MVPP2_PRS_RI_L4_UDP BIT(23)
801 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
802 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
803 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
804 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
806 /* Sram additional info bits assignment */
807 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
808 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
809 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
810 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
811 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
812 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
813 #define MVPP2_PRS_SINGLE_VLAN_AI 0
814 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
817 #define MVPP2_PRS_TAGGED true
818 #define MVPP2_PRS_UNTAGGED false
819 #define MVPP2_PRS_EDSA true
820 #define MVPP2_PRS_DSA false
822 /* MAC entries, shadow udf */
824 MVPP2_PRS_UDF_MAC_DEF,
825 MVPP2_PRS_UDF_MAC_RANGE,
826 MVPP2_PRS_UDF_L2_DEF,
827 MVPP2_PRS_UDF_L2_DEF_COPY,
828 MVPP2_PRS_UDF_L2_USER,
832 enum mvpp2_prs_lookup {
846 enum mvpp2_prs_l3_cast {
847 MVPP2_PRS_L3_UNI_CAST,
848 MVPP2_PRS_L3_MULTI_CAST,
849 MVPP2_PRS_L3_BROAD_CAST
852 /* Classifier constants */
853 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
854 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
855 #define MVPP2_CLS_LKP_TBL_SIZE 64
858 #define MVPP2_BM_POOLS_NUM 1
859 #define MVPP2_BM_LONG_BUF_NUM 16
860 #define MVPP2_BM_SHORT_BUF_NUM 16
861 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
862 #define MVPP2_BM_POOL_PTR_ALIGN 128
863 #define MVPP2_BM_SWF_LONG_POOL(port) 0
865 /* BM cookie (32 bits) definition */
866 #define MVPP2_BM_COOKIE_POOL_OFFS 8
867 #define MVPP2_BM_COOKIE_CPU_OFFS 24
869 /* BM short pool packet size
870 * These value assure that for SWF the total number
871 * of bytes allocated for each buffer will be 512
873 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
883 /* Shared Packet Processor resources */
885 /* Shared registers' base addresses */
887 void __iomem *lms_base;
888 void __iomem *iface_base;
890 void __iomem *mpcs_base;
891 void __iomem *xpcs_base;
892 void __iomem *rfu1_base;
896 /* List of pointers to port structures */
897 struct mvpp2_port **port_list;
899 /* Aggregated TXQs */
900 struct mvpp2_tx_queue *aggr_txqs;
903 struct mvpp2_bm_pool *bm_pools;
905 /* PRS shadow table */
906 struct mvpp2_prs_shadow *prs_shadow;
907 /* PRS auxiliary table for double vlan entries control */
908 bool *prs_double_vlans;
914 enum { MVPP21, MVPP22 } hw_version;
916 /* Maximum number of RXQs per port */
917 unsigned int max_port_rxqs;
923 struct mvpp2_pcpu_stats {
933 /* Index of the port from the "group of ports" complex point
942 /* Per-port registers' base address */
945 struct mvpp2_rx_queue **rxqs;
946 struct mvpp2_tx_queue **txqs;
950 u32 pending_cause_rx;
952 /* Per-CPU port control */
953 struct mvpp2_port_pcpu __percpu *pcpu;
960 struct mvpp2_pcpu_stats __percpu *stats;
962 struct phy_device *phy_dev;
963 phy_interface_t phy_interface;
965 struct udevice *mdio_dev;
967 #if CONFIG_IS_ENABLED(DM_GPIO)
968 struct gpio_desc phy_reset_gpio;
969 struct gpio_desc phy_tx_disable_gpio;
976 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
978 struct mvpp2_bm_pool *pool_long;
979 struct mvpp2_bm_pool *pool_short;
981 /* Index of first port's physical RXQ */
984 u8 dev_addr[ETH_ALEN];
987 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
988 * layout of the transmit and reception DMA descriptors, and their
989 * layout is therefore defined by the hardware design
992 #define MVPP2_TXD_L3_OFF_SHIFT 0
993 #define MVPP2_TXD_IP_HLEN_SHIFT 8
994 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
995 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
996 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
997 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
998 #define MVPP2_TXD_L4_UDP BIT(24)
999 #define MVPP2_TXD_L3_IP6 BIT(26)
1000 #define MVPP2_TXD_L_DESC BIT(28)
1001 #define MVPP2_TXD_F_DESC BIT(29)
1003 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
1004 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1005 #define MVPP2_RXD_ERR_CRC 0x0
1006 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
1007 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1008 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
1009 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1010 #define MVPP2_RXD_HWF_SYNC BIT(21)
1011 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
1012 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1013 #define MVPP2_RXD_L4_TCP BIT(25)
1014 #define MVPP2_RXD_L4_UDP BIT(26)
1015 #define MVPP2_RXD_L3_IP4 BIT(28)
1016 #define MVPP2_RXD_L3_IP6 BIT(30)
1017 #define MVPP2_RXD_BUF_HDR BIT(31)
1019 /* HW TX descriptor for PPv2.1 */
1020 struct mvpp21_tx_desc {
1021 u32 command; /* Options used by HW for packet transmitting.*/
1022 u8 packet_offset; /* the offset from the buffer beginning */
1023 u8 phys_txq; /* destination queue ID */
1024 u16 data_size; /* data size of transmitted packet in bytes */
1025 u32 buf_dma_addr; /* physical addr of transmitted buffer */
1026 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1027 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1028 u32 reserved2; /* reserved (for future use) */
1031 /* HW RX descriptor for PPv2.1 */
1032 struct mvpp21_rx_desc {
1033 u32 status; /* info about received packet */
1034 u16 reserved1; /* parser_info (for future use, PnC) */
1035 u16 data_size; /* size of received packet in bytes */
1036 u32 buf_dma_addr; /* physical address of the buffer */
1037 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1038 u16 reserved2; /* gem_port_id (for future use, PON) */
1039 u16 reserved3; /* csum_l4 (for future use, PnC) */
1040 u8 reserved4; /* bm_qset (for future use, BM) */
1042 u16 reserved6; /* classify_info (for future use, PnC) */
1043 u32 reserved7; /* flow_id (for future use, PnC) */
1047 /* HW TX descriptor for PPv2.2 */
1048 struct mvpp22_tx_desc {
1054 u64 buf_dma_addr_ptp;
1055 u64 buf_cookie_misc;
1058 /* HW RX descriptor for PPv2.2 */
1059 struct mvpp22_rx_desc {
1065 u64 buf_dma_addr_key_hash;
1066 u64 buf_cookie_misc;
1069 /* Opaque type used by the driver to manipulate the HW TX and RX
1072 struct mvpp2_tx_desc {
1074 struct mvpp21_tx_desc pp21;
1075 struct mvpp22_tx_desc pp22;
1079 struct mvpp2_rx_desc {
1081 struct mvpp21_rx_desc pp21;
1082 struct mvpp22_rx_desc pp22;
1086 /* Per-CPU Tx queue control */
1087 struct mvpp2_txq_pcpu {
1090 /* Number of Tx DMA descriptors in the descriptor ring */
1093 /* Number of currently used Tx DMA descriptor in the
1098 /* Number of Tx DMA descriptors reserved for each CPU */
1101 /* Index of last TX DMA descriptor that was inserted */
1104 /* Index of the TX DMA descriptor to be cleaned up */
1108 struct mvpp2_tx_queue {
1109 /* Physical number of this Tx queue */
1112 /* Logical number of this Tx queue */
1115 /* Number of Tx DMA descriptors in the descriptor ring */
1118 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1121 /* Per-CPU control of physical Tx queues */
1122 struct mvpp2_txq_pcpu __percpu *pcpu;
1126 /* Virtual address of thex Tx DMA descriptors array */
1127 struct mvpp2_tx_desc *descs;
1129 /* DMA address of the Tx DMA descriptors array */
1130 dma_addr_t descs_dma;
1132 /* Index of the last Tx DMA descriptor */
1135 /* Index of the next Tx DMA descriptor to process */
1136 int next_desc_to_proc;
1139 struct mvpp2_rx_queue {
1140 /* RX queue number, in the range 0-31 for physical RXQs */
1143 /* Num of rx descriptors in the rx descriptor ring */
1149 /* Virtual address of the RX DMA descriptors array */
1150 struct mvpp2_rx_desc *descs;
1152 /* DMA address of the RX DMA descriptors array */
1153 dma_addr_t descs_dma;
1155 /* Index of the last RX DMA descriptor */
1158 /* Index of the next RX DMA descriptor to process */
1159 int next_desc_to_proc;
1161 /* ID of port to which physical RXQ is mapped */
1164 /* Port's logic RXQ number to which physical RXQ is mapped */
1168 union mvpp2_prs_tcam_entry {
1169 u32 word[MVPP2_PRS_TCAM_WORDS];
1170 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1173 union mvpp2_prs_sram_entry {
1174 u32 word[MVPP2_PRS_SRAM_WORDS];
1175 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1178 struct mvpp2_prs_entry {
1180 union mvpp2_prs_tcam_entry tcam;
1181 union mvpp2_prs_sram_entry sram;
1184 struct mvpp2_prs_shadow {
1191 /* User defined offset */
1199 struct mvpp2_cls_flow_entry {
1201 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1204 struct mvpp2_cls_lookup_entry {
1210 struct mvpp2_bm_pool {
1211 /* Pool number in the range 0-7 */
1213 enum mvpp2_bm_type type;
1215 /* Buffer Pointers Pool External (BPPE) size */
1217 /* Number of buffers for this pool */
1219 /* Pool buffer size */
1224 /* BPPE virtual base address */
1225 unsigned long *virt_addr;
1226 /* BPPE DMA base address */
1227 dma_addr_t dma_addr;
1229 /* Ports using BM pool */
1233 /* Static declaractions */
1235 /* Number of RXQs used by single port */
1236 static int rxq_number = MVPP2_DEFAULT_RXQ;
1237 /* Number of TXQs used by single port */
1238 static int txq_number = MVPP2_DEFAULT_TXQ;
1242 #define MVPP2_DRIVER_NAME "mvpp2"
1243 #define MVPP2_DRIVER_VERSION "1.0"
1246 * U-Boot internal data, mostly uncached buffers for descriptors and data
1248 struct buffer_location {
1249 struct mvpp2_tx_desc *aggr_tx_descs;
1250 struct mvpp2_tx_desc *tx_descs;
1251 struct mvpp2_rx_desc *rx_descs;
1252 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1253 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1258 * All 4 interfaces use the same global buffer, since only one interface
1259 * can be enabled at once
1261 static struct buffer_location buffer_loc;
1264 * Page table entries are set to 1MB, or multiples of 1MB
1265 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1267 #define BD_SPACE (1 << 20)
1269 /* Utility/helper methods */
1271 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1273 writel(data, priv->base + offset);
1276 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1278 return readl(priv->base + offset);
1281 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1282 struct mvpp2_tx_desc *tx_desc,
1283 dma_addr_t dma_addr)
1285 if (port->priv->hw_version == MVPP21) {
1286 tx_desc->pp21.buf_dma_addr = dma_addr;
1288 u64 val = (u64)dma_addr;
1290 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1291 tx_desc->pp22.buf_dma_addr_ptp |= val;
1295 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1296 struct mvpp2_tx_desc *tx_desc,
1299 if (port->priv->hw_version == MVPP21)
1300 tx_desc->pp21.data_size = size;
1302 tx_desc->pp22.data_size = size;
1305 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1306 struct mvpp2_tx_desc *tx_desc,
1309 if (port->priv->hw_version == MVPP21)
1310 tx_desc->pp21.phys_txq = txq;
1312 tx_desc->pp22.phys_txq = txq;
1315 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1316 struct mvpp2_tx_desc *tx_desc,
1317 unsigned int command)
1319 if (port->priv->hw_version == MVPP21)
1320 tx_desc->pp21.command = command;
1322 tx_desc->pp22.command = command;
1325 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1326 struct mvpp2_tx_desc *tx_desc,
1327 unsigned int offset)
1329 if (port->priv->hw_version == MVPP21)
1330 tx_desc->pp21.packet_offset = offset;
1332 tx_desc->pp22.packet_offset = offset;
1335 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1336 struct mvpp2_rx_desc *rx_desc)
1338 if (port->priv->hw_version == MVPP21)
1339 return rx_desc->pp21.buf_dma_addr;
1341 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1344 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1345 struct mvpp2_rx_desc *rx_desc)
1347 if (port->priv->hw_version == MVPP21)
1348 return rx_desc->pp21.buf_cookie;
1350 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1353 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1354 struct mvpp2_rx_desc *rx_desc)
1356 if (port->priv->hw_version == MVPP21)
1357 return rx_desc->pp21.data_size;
1359 return rx_desc->pp22.data_size;
1362 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1363 struct mvpp2_rx_desc *rx_desc)
1365 if (port->priv->hw_version == MVPP21)
1366 return rx_desc->pp21.status;
1368 return rx_desc->pp22.status;
1371 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1373 txq_pcpu->txq_get_index++;
1374 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1375 txq_pcpu->txq_get_index = 0;
1378 /* Get number of physical egress port */
1379 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1381 return MVPP2_MAX_TCONT + port->id;
1384 /* Get number of physical TXQ */
1385 static inline int mvpp2_txq_phys(int port, int txq)
1387 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1390 /* Parser configuration routines */
1392 /* Update parser tcam and sram hw entries */
1393 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1397 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1400 /* Clear entry invalidation bit */
1401 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1403 /* Write tcam index - indirect access */
1404 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1405 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1406 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1408 /* Write sram index - indirect access */
1409 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1410 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1411 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1416 /* Read tcam entry from hw */
1417 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1421 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1424 /* Write tcam index - indirect access */
1425 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1427 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1428 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1429 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1430 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1432 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1433 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1435 /* Write sram index - indirect access */
1436 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1437 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1438 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1443 /* Invalidate tcam hw entry */
1444 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1446 /* Write index - indirect access */
1447 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1448 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1449 MVPP2_PRS_TCAM_INV_MASK);
1452 /* Enable shadow table entry and set its lookup ID */
1453 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1455 priv->prs_shadow[index].valid = true;
1456 priv->prs_shadow[index].lu = lu;
1459 /* Update ri fields in shadow table entry */
1460 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1461 unsigned int ri, unsigned int ri_mask)
1463 priv->prs_shadow[index].ri_mask = ri_mask;
1464 priv->prs_shadow[index].ri = ri;
1467 /* Update lookup field in tcam sw entry */
1468 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1470 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1472 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1473 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1476 /* Update mask for single port in tcam sw entry */
1477 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1478 unsigned int port, bool add)
1480 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1483 pe->tcam.byte[enable_off] &= ~(1 << port);
1485 pe->tcam.byte[enable_off] |= 1 << port;
1488 /* Update port map in tcam sw entry */
1489 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1492 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1493 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1495 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1496 pe->tcam.byte[enable_off] &= ~port_mask;
1497 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1500 /* Obtain port map from tcam sw entry */
1501 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1503 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1505 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1508 /* Set byte of data and its enable bits in tcam sw entry */
1509 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1510 unsigned int offs, unsigned char byte,
1511 unsigned char enable)
1513 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1514 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1517 /* Get byte of data and its enable bits from tcam sw entry */
1518 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1519 unsigned int offs, unsigned char *byte,
1520 unsigned char *enable)
1522 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1523 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1526 /* Set ethertype in tcam sw entry */
1527 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1528 unsigned short ethertype)
1530 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1531 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1534 /* Set bits in sram sw entry */
1535 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1538 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1541 /* Clear bits in sram sw entry */
1542 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1545 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1548 /* Update ri bits in sram sw entry */
1549 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1550 unsigned int bits, unsigned int mask)
1554 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1555 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1557 if (!(mask & BIT(i)))
1561 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1563 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1565 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1569 /* Update ai bits in sram sw entry */
1570 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1571 unsigned int bits, unsigned int mask)
1574 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1576 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1578 if (!(mask & BIT(i)))
1582 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1584 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1586 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1590 /* Read ai bits from sram sw entry */
1591 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1594 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1595 int ai_en_off = ai_off + 1;
1596 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1598 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1599 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1604 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1607 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1610 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1612 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1613 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1614 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1617 /* In the sram sw entry set sign and value of the next lookup offset
1618 * and the offset value generated to the classifier
1620 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1625 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1628 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1632 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1633 (unsigned char)shift;
1635 /* Reset and set operation */
1636 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1637 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1638 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1640 /* Set base offset as current */
1641 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1644 /* In the sram sw entry set sign and value of the user defined offset
1645 * generated to the classifier
1647 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1648 unsigned int type, int offset,
1653 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1654 offset = 0 - offset;
1656 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1660 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1661 MVPP2_PRS_SRAM_UDF_MASK);
1662 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1663 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1664 MVPP2_PRS_SRAM_UDF_BITS)] &=
1665 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1666 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1667 MVPP2_PRS_SRAM_UDF_BITS)] |=
1668 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1670 /* Set offset type */
1671 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1672 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1673 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1675 /* Set offset operation */
1676 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1677 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1678 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1680 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1681 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1682 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1683 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1685 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1686 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1687 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1689 /* Set base offset as current */
1690 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1693 /* Find parser flow entry */
1694 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1696 struct mvpp2_prs_entry *pe;
1699 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1702 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1704 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1705 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1708 if (!priv->prs_shadow[tid].valid ||
1709 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1713 mvpp2_prs_hw_read(priv, pe);
1714 bits = mvpp2_prs_sram_ai_get(pe);
1716 /* Sram store classification lookup ID in AI bits [5:0] */
1717 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1725 /* Return first free tcam index, seeking from start to end */
1726 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1734 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1735 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1737 for (tid = start; tid <= end; tid++) {
1738 if (!priv->prs_shadow[tid].valid)
1745 /* Enable/disable dropping all mac da's */
1746 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1748 struct mvpp2_prs_entry pe;
1750 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1751 /* Entry exist - update port only */
1752 pe.index = MVPP2_PE_DROP_ALL;
1753 mvpp2_prs_hw_read(priv, &pe);
1755 /* Entry doesn't exist - create new */
1756 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1757 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1758 pe.index = MVPP2_PE_DROP_ALL;
1760 /* Non-promiscuous mode for all ports - DROP unknown packets */
1761 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1762 MVPP2_PRS_RI_DROP_MASK);
1764 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1765 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1767 /* Update shadow table */
1768 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1770 /* Mask all ports */
1771 mvpp2_prs_tcam_port_map_set(&pe, 0);
1774 /* Update port mask */
1775 mvpp2_prs_tcam_port_set(&pe, port, add);
1777 mvpp2_prs_hw_write(priv, &pe);
1780 /* Set port to promiscuous mode */
1781 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1783 struct mvpp2_prs_entry pe;
1785 /* Promiscuous mode - Accept unknown packets */
1787 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1788 /* Entry exist - update port only */
1789 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1790 mvpp2_prs_hw_read(priv, &pe);
1792 /* Entry doesn't exist - create new */
1793 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1794 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1795 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1797 /* Continue - set next lookup */
1798 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1800 /* Set result info bits */
1801 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1802 MVPP2_PRS_RI_L2_CAST_MASK);
1804 /* Shift to ethertype */
1805 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1806 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1808 /* Mask all ports */
1809 mvpp2_prs_tcam_port_map_set(&pe, 0);
1811 /* Update shadow table */
1812 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1815 /* Update port mask */
1816 mvpp2_prs_tcam_port_set(&pe, port, add);
1818 mvpp2_prs_hw_write(priv, &pe);
1821 /* Accept multicast */
1822 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1825 struct mvpp2_prs_entry pe;
1826 unsigned char da_mc;
1828 /* Ethernet multicast address first byte is
1829 * 0x01 for IPv4 and 0x33 for IPv6
1831 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1833 if (priv->prs_shadow[index].valid) {
1834 /* Entry exist - update port only */
1836 mvpp2_prs_hw_read(priv, &pe);
1838 /* Entry doesn't exist - create new */
1839 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1840 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1843 /* Continue - set next lookup */
1844 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1846 /* Set result info bits */
1847 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1848 MVPP2_PRS_RI_L2_CAST_MASK);
1850 /* Update tcam entry data first byte */
1851 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1853 /* Shift to ethertype */
1854 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1855 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1857 /* Mask all ports */
1858 mvpp2_prs_tcam_port_map_set(&pe, 0);
1860 /* Update shadow table */
1861 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1864 /* Update port mask */
1865 mvpp2_prs_tcam_port_set(&pe, port, add);
1867 mvpp2_prs_hw_write(priv, &pe);
1870 /* Parser per-port initialization */
1871 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1872 int lu_max, int offset)
1877 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1878 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1879 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1880 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1882 /* Set maximum number of loops for packet received from port */
1883 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1884 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1885 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1886 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1888 /* Set initial offset for packet header extraction for the first
1891 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1892 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1893 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1894 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1897 /* Default flow entries initialization for all ports */
1898 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1900 struct mvpp2_prs_entry pe;
1903 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1904 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1905 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1906 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1908 /* Mask all ports */
1909 mvpp2_prs_tcam_port_map_set(&pe, 0);
1912 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1913 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1915 /* Update shadow table and hw entry */
1916 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1917 mvpp2_prs_hw_write(priv, &pe);
1921 /* Set default entry for Marvell Header field */
1922 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1924 struct mvpp2_prs_entry pe;
1926 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1928 pe.index = MVPP2_PE_MH_DEFAULT;
1929 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1930 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1931 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1932 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1934 /* Unmask all ports */
1935 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1937 /* Update shadow table and hw entry */
1938 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1939 mvpp2_prs_hw_write(priv, &pe);
1942 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1943 * multicast MAC addresses
1945 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1947 struct mvpp2_prs_entry pe;
1949 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1951 /* Non-promiscuous mode for all ports - DROP unknown packets */
1952 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1953 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1955 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1956 MVPP2_PRS_RI_DROP_MASK);
1957 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1958 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1960 /* Unmask all ports */
1961 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1963 /* Update shadow table and hw entry */
1964 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1965 mvpp2_prs_hw_write(priv, &pe);
1967 /* place holders only - no ports */
1968 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1969 mvpp2_prs_mac_promisc_set(priv, 0, false);
1970 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1971 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1974 /* Match basic ethertypes */
1975 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1977 struct mvpp2_prs_entry pe;
1980 /* Ethertype: PPPoE */
1981 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1982 MVPP2_PE_LAST_FREE_TID);
1986 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1987 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1990 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1992 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1993 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1994 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1995 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1996 MVPP2_PRS_RI_PPPOE_MASK);
1998 /* Update shadow table and hw entry */
1999 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2000 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2001 priv->prs_shadow[pe.index].finish = false;
2002 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2003 MVPP2_PRS_RI_PPPOE_MASK);
2004 mvpp2_prs_hw_write(priv, &pe);
2006 /* Ethertype: ARP */
2007 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2008 MVPP2_PE_LAST_FREE_TID);
2012 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2013 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2016 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2018 /* Generate flow in the next iteration*/
2019 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2020 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2021 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2022 MVPP2_PRS_RI_L3_PROTO_MASK);
2024 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2026 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2028 /* Update shadow table and hw entry */
2029 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2030 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2031 priv->prs_shadow[pe.index].finish = true;
2032 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2033 MVPP2_PRS_RI_L3_PROTO_MASK);
2034 mvpp2_prs_hw_write(priv, &pe);
2036 /* Ethertype: LBTD */
2037 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2038 MVPP2_PE_LAST_FREE_TID);
2042 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2043 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2046 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2048 /* Generate flow in the next iteration*/
2049 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2050 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2051 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2052 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2053 MVPP2_PRS_RI_CPU_CODE_MASK |
2054 MVPP2_PRS_RI_UDF3_MASK);
2056 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2058 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2060 /* Update shadow table and hw entry */
2061 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2062 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2063 priv->prs_shadow[pe.index].finish = true;
2064 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2065 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2066 MVPP2_PRS_RI_CPU_CODE_MASK |
2067 MVPP2_PRS_RI_UDF3_MASK);
2068 mvpp2_prs_hw_write(priv, &pe);
2070 /* Ethertype: IPv4 without options */
2071 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2072 MVPP2_PE_LAST_FREE_TID);
2076 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2077 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2080 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2081 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2082 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2083 MVPP2_PRS_IPV4_HEAD_MASK |
2084 MVPP2_PRS_IPV4_IHL_MASK);
2086 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2087 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2088 MVPP2_PRS_RI_L3_PROTO_MASK);
2089 /* Skip eth_type + 4 bytes of IP header */
2090 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2091 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2093 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2095 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2097 /* Update shadow table and hw entry */
2098 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2099 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2100 priv->prs_shadow[pe.index].finish = false;
2101 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2102 MVPP2_PRS_RI_L3_PROTO_MASK);
2103 mvpp2_prs_hw_write(priv, &pe);
2105 /* Ethertype: IPv4 with options */
2106 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2107 MVPP2_PE_LAST_FREE_TID);
2113 /* Clear tcam data before updating */
2114 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2115 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2117 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2118 MVPP2_PRS_IPV4_HEAD,
2119 MVPP2_PRS_IPV4_HEAD_MASK);
2121 /* Clear ri before updating */
2122 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2123 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2124 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2125 MVPP2_PRS_RI_L3_PROTO_MASK);
2127 /* Update shadow table and hw entry */
2128 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2129 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2130 priv->prs_shadow[pe.index].finish = false;
2131 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2132 MVPP2_PRS_RI_L3_PROTO_MASK);
2133 mvpp2_prs_hw_write(priv, &pe);
2135 /* Ethertype: IPv6 without options */
2136 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2137 MVPP2_PE_LAST_FREE_TID);
2141 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2142 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2145 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2147 /* Skip DIP of IPV6 header */
2148 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2149 MVPP2_MAX_L3_ADDR_SIZE,
2150 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2151 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2152 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2153 MVPP2_PRS_RI_L3_PROTO_MASK);
2155 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2157 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2159 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2160 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2161 priv->prs_shadow[pe.index].finish = false;
2162 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2163 MVPP2_PRS_RI_L3_PROTO_MASK);
2164 mvpp2_prs_hw_write(priv, &pe);
2166 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2167 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2168 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2169 pe.index = MVPP2_PE_ETH_TYPE_UN;
2171 /* Unmask all ports */
2172 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2174 /* Generate flow in the next iteration*/
2175 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2176 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2177 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2178 MVPP2_PRS_RI_L3_PROTO_MASK);
2179 /* Set L3 offset even it's unknown L3 */
2180 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2182 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2184 /* Update shadow table and hw entry */
2185 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2186 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2187 priv->prs_shadow[pe.index].finish = true;
2188 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2189 MVPP2_PRS_RI_L3_PROTO_MASK);
2190 mvpp2_prs_hw_write(priv, &pe);
2195 /* Parser default initialization */
2196 static int mvpp2_prs_default_init(struct udevice *dev,
2201 /* Enable tcam table */
2202 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2204 /* Clear all tcam and sram entries */
2205 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2206 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2207 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2208 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2210 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2211 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2212 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2215 /* Invalidate all tcam entries */
2216 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2217 mvpp2_prs_hw_inv(priv, index);
2219 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2220 sizeof(struct mvpp2_prs_shadow),
2222 if (!priv->prs_shadow)
2225 /* Always start from lookup = 0 */
2226 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2227 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2228 MVPP2_PRS_PORT_LU_MAX, 0);
2230 mvpp2_prs_def_flow_init(priv);
2232 mvpp2_prs_mh_init(priv);
2234 mvpp2_prs_mac_init(priv);
2236 err = mvpp2_prs_etype_init(priv);
2243 /* Compare MAC DA with tcam entry data */
2244 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2245 const u8 *da, unsigned char *mask)
2247 unsigned char tcam_byte, tcam_mask;
2250 for (index = 0; index < ETH_ALEN; index++) {
2251 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2252 if (tcam_mask != mask[index])
2255 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2262 /* Find tcam entry with matched pair <MAC DA, port> */
2263 static struct mvpp2_prs_entry *
2264 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2265 unsigned char *mask, int udf_type)
2267 struct mvpp2_prs_entry *pe;
2270 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2273 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2275 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2276 for (tid = MVPP2_PE_FIRST_FREE_TID;
2277 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2278 unsigned int entry_pmap;
2280 if (!priv->prs_shadow[tid].valid ||
2281 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2282 (priv->prs_shadow[tid].udf != udf_type))
2286 mvpp2_prs_hw_read(priv, pe);
2287 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2289 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2298 /* Update parser's mac da entry */
2299 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2300 const u8 *da, bool add)
2302 struct mvpp2_prs_entry *pe;
2303 unsigned int pmap, len, ri;
2304 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2307 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2308 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2309 MVPP2_PRS_UDF_MAC_DEF);
2316 /* Create new TCAM entry */
2317 /* Find first range mac entry*/
2318 for (tid = MVPP2_PE_FIRST_FREE_TID;
2319 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2320 if (priv->prs_shadow[tid].valid &&
2321 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2322 (priv->prs_shadow[tid].udf ==
2323 MVPP2_PRS_UDF_MAC_RANGE))
2326 /* Go through the all entries from first to last */
2327 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2332 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2335 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2338 /* Mask all ports */
2339 mvpp2_prs_tcam_port_map_set(pe, 0);
2342 /* Update port mask */
2343 mvpp2_prs_tcam_port_set(pe, port, add);
2345 /* Invalidate the entry if no ports are left enabled */
2346 pmap = mvpp2_prs_tcam_port_map_get(pe);
2352 mvpp2_prs_hw_inv(priv, pe->index);
2353 priv->prs_shadow[pe->index].valid = false;
2358 /* Continue - set next lookup */
2359 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2361 /* Set match on DA */
2364 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2366 /* Set result info bits */
2367 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2369 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2370 MVPP2_PRS_RI_MAC_ME_MASK);
2371 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2372 MVPP2_PRS_RI_MAC_ME_MASK);
2374 /* Shift to ethertype */
2375 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2376 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2378 /* Update shadow table and hw entry */
2379 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2380 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2381 mvpp2_prs_hw_write(priv, pe);
2388 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2392 /* Remove old parser entry */
2393 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2398 /* Add new parser entry */
2399 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2403 /* Set addr in the device */
2404 memcpy(port->dev_addr, da, ETH_ALEN);
2409 /* Set prs flow for the port */
2410 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2412 struct mvpp2_prs_entry *pe;
2415 pe = mvpp2_prs_flow_find(port->priv, port->id);
2417 /* Such entry not exist */
2419 /* Go through the all entires from last to first */
2420 tid = mvpp2_prs_tcam_first_free(port->priv,
2421 MVPP2_PE_LAST_FREE_TID,
2422 MVPP2_PE_FIRST_FREE_TID);
2426 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2430 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2434 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2435 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2437 /* Update shadow table */
2438 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2441 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2442 mvpp2_prs_hw_write(port->priv, pe);
2448 /* Classifier configuration routines */
2450 /* Update classification flow table registers */
2451 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2452 struct mvpp2_cls_flow_entry *fe)
2454 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2455 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2456 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2457 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2460 /* Update classification lookup table register */
2461 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2462 struct mvpp2_cls_lookup_entry *le)
2466 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2467 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2468 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2471 /* Classifier default initialization */
2472 static void mvpp2_cls_init(struct mvpp2 *priv)
2474 struct mvpp2_cls_lookup_entry le;
2475 struct mvpp2_cls_flow_entry fe;
2478 /* Enable classifier */
2479 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2481 /* Clear classifier flow table */
2482 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2483 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2485 mvpp2_cls_flow_write(priv, &fe);
2488 /* Clear classifier lookup table */
2490 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2493 mvpp2_cls_lookup_write(priv, &le);
2496 mvpp2_cls_lookup_write(priv, &le);
2500 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2502 struct mvpp2_cls_lookup_entry le;
2505 /* Set way for the port */
2506 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2507 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2508 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2510 /* Pick the entry to be accessed in lookup ID decoding table
2511 * according to the way and lkpid.
2513 le.lkpid = port->id;
2517 /* Set initial CPU queue for receiving packets */
2518 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2519 le.data |= port->first_rxq;
2521 /* Disable classification engines */
2522 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2524 /* Update lookup ID table entry */
2525 mvpp2_cls_lookup_write(port->priv, &le);
2528 /* Set CPU queue number for oversize packets */
2529 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2533 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2534 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2536 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2537 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2539 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2540 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2541 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2544 /* Buffer Manager configuration routines */
2547 static int mvpp2_bm_pool_create(struct udevice *dev,
2549 struct mvpp2_bm_pool *bm_pool, int size)
2553 /* Number of buffer pointers must be a multiple of 16, as per
2554 * hardware constraints
2556 if (!IS_ALIGNED(size, 16))
2559 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2560 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2561 if (!bm_pool->virt_addr)
2564 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2565 MVPP2_BM_POOL_PTR_ALIGN)) {
2566 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2567 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2571 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2572 lower_32_bits(bm_pool->dma_addr));
2573 if (priv->hw_version == MVPP22)
2574 mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
2575 (upper_32_bits(bm_pool->dma_addr) &
2576 MVPP22_BM_POOL_BASE_HIGH_MASK));
2577 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2579 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2580 val |= MVPP2_BM_START_MASK;
2581 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2583 bm_pool->type = MVPP2_BM_FREE;
2584 bm_pool->size = size;
2585 bm_pool->pkt_size = 0;
2586 bm_pool->buf_num = 0;
2591 /* Set pool buffer size */
2592 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2593 struct mvpp2_bm_pool *bm_pool,
2598 bm_pool->buf_size = buf_size;
2600 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2601 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2604 /* Free all buffers from the pool */
2605 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2606 struct mvpp2_bm_pool *bm_pool)
2610 for (i = 0; i < bm_pool->buf_num; i++) {
2611 /* Allocate buffer back from the buffer manager */
2612 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2615 bm_pool->buf_num = 0;
2619 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2621 struct mvpp2_bm_pool *bm_pool)
2625 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2626 if (bm_pool->buf_num) {
2627 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2631 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2632 val |= MVPP2_BM_STOP_MASK;
2633 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2638 static int mvpp2_bm_pools_init(struct udevice *dev,
2642 struct mvpp2_bm_pool *bm_pool;
2644 /* Create all pools with maximum size */
2645 size = MVPP2_BM_POOL_SIZE_MAX;
2646 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2647 bm_pool = &priv->bm_pools[i];
2649 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2651 goto err_unroll_pools;
2652 mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
2657 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2658 for (i = i - 1; i >= 0; i--)
2659 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2663 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2667 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2668 /* Mask BM all interrupts */
2669 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2670 /* Clear BM cause register */
2671 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2674 /* Allocate and initialize BM pools */
2675 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2676 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2677 if (!priv->bm_pools)
2680 err = mvpp2_bm_pools_init(dev, priv);
2686 /* Attach long pool to rxq */
2687 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2688 int lrxq, int long_pool)
2693 /* Get queue physical ID */
2694 prxq = port->rxqs[lrxq]->id;
2696 if (port->priv->hw_version == MVPP21)
2697 mask = MVPP21_RXQ_POOL_LONG_MASK;
2699 mask = MVPP22_RXQ_POOL_LONG_MASK;
2701 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2703 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2704 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2707 /* Set pool number in a BM cookie */
2708 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2712 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2713 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2718 /* Get pool number from a BM cookie */
2719 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2721 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2724 /* Release buffer to BM */
2725 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2726 dma_addr_t buf_dma_addr,
2727 unsigned long buf_phys_addr)
2729 if (port->priv->hw_version == MVPP22) {
2732 if (sizeof(dma_addr_t) == 8)
2733 val |= upper_32_bits(buf_dma_addr) &
2734 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2736 if (sizeof(phys_addr_t) == 8)
2737 val |= (upper_32_bits(buf_phys_addr)
2738 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2739 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2741 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2744 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2745 * returned in the "cookie" field of the RX
2746 * descriptor. Instead of storing the virtual address, we
2747 * store the physical address
2749 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2750 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2753 /* Refill BM pool */
2754 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2755 dma_addr_t dma_addr,
2756 phys_addr_t phys_addr)
2758 int pool = mvpp2_bm_cookie_pool_get(bm);
2760 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2763 /* Allocate buffers for the pool */
2764 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2765 struct mvpp2_bm_pool *bm_pool, int buf_num)
2770 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2771 netdev_err(port->dev,
2772 "cannot allocate %d buffers for pool %d\n",
2773 buf_num, bm_pool->id);
2777 for (i = 0; i < buf_num; i++) {
2778 mvpp2_bm_pool_put(port, bm_pool->id,
2779 (dma_addr_t)buffer_loc.rx_buffer[i],
2780 (unsigned long)buffer_loc.rx_buffer[i]);
2784 /* Update BM driver with number of buffers added to pool */
2785 bm_pool->buf_num += i;
2790 /* Notify the driver that BM pool is being used as specific type and return the
2791 * pool pointer on success
2793 static struct mvpp2_bm_pool *
2794 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2797 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2800 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2801 netdev_err(port->dev, "mixing pool types is forbidden\n");
2805 if (new_pool->type == MVPP2_BM_FREE)
2806 new_pool->type = type;
2808 /* Allocate buffers in case BM pool is used as long pool, but packet
2809 * size doesn't match MTU or BM pool hasn't being used yet
2811 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2812 (new_pool->pkt_size == 0)) {
2815 /* Set default buffer number or free all the buffers in case
2816 * the pool is not empty
2818 pkts_num = new_pool->buf_num;
2820 pkts_num = type == MVPP2_BM_SWF_LONG ?
2821 MVPP2_BM_LONG_BUF_NUM :
2822 MVPP2_BM_SHORT_BUF_NUM;
2824 mvpp2_bm_bufs_free(NULL,
2825 port->priv, new_pool);
2827 new_pool->pkt_size = pkt_size;
2829 /* Allocate buffers for this pool */
2830 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2831 if (num != pkts_num) {
2832 dev_err(dev, "pool %d: %d of %d allocated\n",
2833 new_pool->id, num, pkts_num);
2841 /* Initialize pools for swf */
2842 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2846 if (!port->pool_long) {
2848 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2851 if (!port->pool_long)
2854 port->pool_long->port_map |= (1 << port->id);
2856 for (rxq = 0; rxq < rxq_number; rxq++)
2857 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2863 /* Port configuration routines */
2865 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2869 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2871 switch (port->phy_interface) {
2872 case PHY_INTERFACE_MODE_SGMII:
2873 val |= MVPP2_GMAC_INBAND_AN_MASK;
2875 case PHY_INTERFACE_MODE_RGMII:
2876 case PHY_INTERFACE_MODE_RGMII_ID:
2877 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2879 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2882 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2885 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2889 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2890 val |= MVPP2_GMAC_FC_ADV_EN;
2891 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2894 static void mvpp2_port_enable(struct mvpp2_port *port)
2898 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2899 val |= MVPP2_GMAC_PORT_EN_MASK;
2900 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2901 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2904 static void mvpp2_port_disable(struct mvpp2_port *port)
2908 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2909 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2910 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2913 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2914 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2918 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2919 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2920 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2923 /* Configure loopback port */
2924 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2928 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2930 if (port->speed == 1000)
2931 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2933 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2935 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2936 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2938 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2940 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2943 static void mvpp2_port_reset(struct mvpp2_port *port)
2947 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2948 ~MVPP2_GMAC_PORT_RESET_MASK;
2949 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2951 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2952 MVPP2_GMAC_PORT_RESET_MASK)
2956 /* Change maximum receive size of the port */
2957 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2961 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2962 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2963 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2964 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2965 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2968 /* PPv2.2 GoP/GMAC config */
2970 /* Set the MAC to reset or exit from reset */
2971 static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2975 /* read - modify - write */
2976 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2978 val |= MVPP2_GMAC_PORT_RESET_MASK;
2980 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
2981 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2989 * Configure port to working with Gig PCS or don't.
2991 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
2995 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2997 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
2999 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3000 /* enable / disable PCS on this port */
3001 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3006 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3010 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3012 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3014 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3015 /* enable / disable PCS on this port */
3016 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3021 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3026 * Configure minimal level of the Tx FIFO before the lower part
3027 * starts to read a packet
3029 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3030 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3031 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3032 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3033 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3035 /* Disable bypass of sync module */
3036 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3037 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3038 /* configure DP clock select according to mode */
3039 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3040 /* configure QSGMII bypass according to mode */
3041 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3042 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3044 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3046 * Configure GIG MAC to 1000Base-X mode connected to a fiber
3049 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3050 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3052 /* configure AN 0x9268 */
3053 val = MVPP2_GMAC_EN_PCS_AN |
3054 MVPP2_GMAC_AN_BYPASS_EN |
3055 MVPP2_GMAC_CONFIG_MII_SPEED |
3056 MVPP2_GMAC_CONFIG_GMII_SPEED |
3057 MVPP2_GMAC_FC_ADV_EN |
3058 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3059 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3060 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3063 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3068 * Configure minimal level of the Tx FIFO before the lower part
3069 * starts to read a packet
3071 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3072 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3073 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3074 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3075 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3077 /* Disable bypass of sync module */
3078 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3079 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3080 /* configure DP clock select according to mode */
3081 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3082 /* configure QSGMII bypass according to mode */
3083 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3084 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3086 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3087 /* configure GIG MAC to SGMII mode */
3088 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3089 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3092 val = MVPP2_GMAC_EN_PCS_AN |
3093 MVPP2_GMAC_AN_BYPASS_EN |
3094 MVPP2_GMAC_AN_SPEED_EN |
3095 MVPP2_GMAC_EN_FC_AN |
3096 MVPP2_GMAC_AN_DUPLEX_EN |
3097 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3098 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3101 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3106 * Configure minimal level of the Tx FIFO before the lower part
3107 * starts to read a packet
3109 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3110 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3111 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3112 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3113 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3115 /* Disable bypass of sync module */
3116 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3117 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3118 /* configure DP clock select according to mode */
3119 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3120 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3121 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3122 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3124 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3125 /* configure GIG MAC to SGMII mode */
3126 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3127 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3129 /* configure AN 0xb8e8 */
3130 val = MVPP2_GMAC_AN_BYPASS_EN |
3131 MVPP2_GMAC_AN_SPEED_EN |
3132 MVPP2_GMAC_EN_FC_AN |
3133 MVPP2_GMAC_AN_DUPLEX_EN |
3134 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3135 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3138 /* Set the internal mux's to the required MAC in the GOP */
3139 static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3143 /* Set TX FIFO thresholds */
3144 switch (port->phy_interface) {
3145 case PHY_INTERFACE_MODE_SGMII:
3146 if (port->phy_speed == 2500)
3147 gop_gmac_sgmii2_5_cfg(port);
3149 gop_gmac_sgmii_cfg(port);
3152 case PHY_INTERFACE_MODE_RGMII:
3153 case PHY_INTERFACE_MODE_RGMII_ID:
3154 gop_gmac_rgmii_cfg(port);
3161 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3162 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3163 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3164 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3165 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3167 /* PeriodicXonEn disable */
3168 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3169 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3170 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3175 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3179 /* relevant only for MAC0 (XLG0 and GMAC0) */
3180 if (port->gop_id > 0)
3183 /* configure 1Gig MAC mode */
3184 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3185 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3186 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3187 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3190 static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3194 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3196 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3198 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3199 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3204 /* Set the internal mux's to the required PCS in the PI */
3205 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
3210 switch (num_of_lanes) {
3224 /* configure XG MAC mode */
3225 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3226 val &= ~MVPP22_XPCS_PCSMODE_MASK;
3227 val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
3228 val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
3229 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3234 static int gop_mpcs_mode(struct mvpp2_port *port)
3238 /* configure PCS40G COMMON CONTROL */
3239 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3240 val &= ~FORWARD_ERROR_CORRECTION_MASK;
3241 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3243 /* configure PCS CLOCK RESET */
3244 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
3245 val &= ~CLK_DIVISION_RATIO_MASK;
3246 val |= 1 << CLK_DIVISION_RATIO_OFFS;
3247 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3249 val &= ~CLK_DIV_PHASE_SET_MASK;
3250 val |= MAC_CLK_RESET_MASK;
3251 val |= RX_SD_CLK_RESET_MASK;
3252 val |= TX_SD_CLK_RESET_MASK;
3253 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3258 /* Set the internal mux's to the required MAC in the GOP */
3259 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3263 /* configure 10G MAC mode */
3264 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3265 val |= MVPP22_XLG_RX_FC_EN;
3266 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3268 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3269 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3270 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3271 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3273 /* read - modify - write */
3274 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3275 val &= ~MVPP22_XLG_MODE_DMA_1G;
3276 val |= MVPP22_XLG_FORWARD_PFC_EN;
3277 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3278 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3279 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3281 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3282 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3283 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3284 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3285 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3287 /* unmask link change interrupt */
3288 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3289 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3290 val |= 1; /* unmask summary bit */
3291 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3296 /* Set PCS to reset or exit from reset */
3297 static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
3301 /* read - modify - write */
3302 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3304 val &= ~MVPP22_XPCS_PCSRESET;
3306 val |= MVPP22_XPCS_PCSRESET;
3307 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3312 /* Set the MAC to reset or exit from reset */
3313 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3317 /* read - modify - write */
3318 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3320 val &= ~MVPP22_XLG_MAC_RESETN;
3322 val |= MVPP22_XLG_MAC_RESETN;
3323 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3331 * Init physical port. Configures the port mode and all it's elements
3333 * Does not verify that the selected mode/port number is valid at the
3336 static int gop_port_init(struct mvpp2_port *port)
3338 int mac_num = port->gop_id;
3339 int num_of_act_lanes;
3341 if (mac_num >= MVPP22_GOP_MAC_NUM) {
3342 netdev_err(NULL, "%s: illegal port number %d", __func__,
3347 switch (port->phy_interface) {
3348 case PHY_INTERFACE_MODE_RGMII:
3349 case PHY_INTERFACE_MODE_RGMII_ID:
3350 gop_gmac_reset(port, 1);
3353 gop_gpcs_mode_cfg(port, 0);
3354 gop_bypass_clk_cfg(port, 1);
3357 gop_gmac_mode_cfg(port);
3359 gop_gpcs_reset(port, 0);
3362 gop_gmac_reset(port, 0);
3365 case PHY_INTERFACE_MODE_SGMII:
3367 gop_gpcs_mode_cfg(port, 1);
3370 gop_gmac_mode_cfg(port);
3371 /* select proper Mac mode */
3372 gop_xlg_2_gig_mac_cfg(port);
3375 gop_gpcs_reset(port, 0);
3377 gop_gmac_reset(port, 0);
3380 case PHY_INTERFACE_MODE_SFI:
3381 num_of_act_lanes = 2;
3384 gop_xpcs_mode(port, num_of_act_lanes);
3385 gop_mpcs_mode(port);
3387 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3390 gop_xpcs_reset(port, 0);
3393 gop_xlg_mac_reset(port, 0);
3397 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
3398 __func__, port->phy_interface);
3405 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3409 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3411 /* Enable port and MIB counters update */
3412 val |= MVPP22_XLG_PORT_EN;
3413 val &= ~MVPP22_XLG_MIBCNT_DIS;
3416 val &= ~MVPP22_XLG_PORT_EN;
3418 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3421 static void gop_port_enable(struct mvpp2_port *port, int enable)
3423 switch (port->phy_interface) {
3424 case PHY_INTERFACE_MODE_RGMII:
3425 case PHY_INTERFACE_MODE_RGMII_ID:
3426 case PHY_INTERFACE_MODE_SGMII:
3428 mvpp2_port_enable(port);
3430 mvpp2_port_disable(port);
3433 case PHY_INTERFACE_MODE_SFI:
3434 gop_xlg_mac_port_enable(port, enable);
3438 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
3439 port->phy_interface);
3444 /* RFU1 functions */
3445 static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3447 return readl(priv->rfu1_base + offset);
3450 static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3452 writel(data, priv->rfu1_base + offset);
3455 static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3460 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3461 val |= MV_NETC_GE_MAC2_SGMII;
3465 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3466 val |= MV_NETC_GE_MAC3_SGMII;
3467 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3468 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3469 val |= MV_NETC_GE_MAC3_RGMII;
3475 static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3479 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3480 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3482 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3483 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3487 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3490 static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3494 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3495 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3497 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3498 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3502 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3505 static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3509 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3510 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3512 val <<= NETC_GOP_SOFT_RESET_OFFS;
3513 val &= NETC_GOP_SOFT_RESET_MASK;
3517 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3520 static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3524 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3525 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3527 val <<= NETC_CLK_DIV_PHASE_OFFS;
3528 val &= NETC_CLK_DIV_PHASE_MASK;
3532 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3535 static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3539 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3540 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3542 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3543 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3547 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3550 static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3553 u32 reg, mask, offset;
3556 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3557 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3559 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3560 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3562 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3570 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3573 static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3577 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3578 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3580 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3581 val &= NETC_BUS_WIDTH_SELECT_MASK;
3585 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3588 static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3592 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3593 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3595 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3596 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3600 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3603 static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3604 enum mv_netc_phase phase)
3607 case MV_NETC_FIRST_PHASE:
3608 /* Set Bus Width to HB mode = 1 */
3609 gop_netc_bus_width_select(priv, 1);
3610 /* Select RGMII mode */
3611 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3614 case MV_NETC_SECOND_PHASE:
3615 /* De-assert the relevant port HB reset */
3616 gop_netc_port_rf_reset(priv, gop_id, 1);
3621 static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3622 enum mv_netc_phase phase)
3625 case MV_NETC_FIRST_PHASE:
3626 /* Set Bus Width to HB mode = 1 */
3627 gop_netc_bus_width_select(priv, 1);
3628 /* Select SGMII mode */
3630 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3634 /* Configure the sample stages */
3635 gop_netc_sample_stages_timing(priv, 0);
3636 /* Configure the ComPhy Selector */
3637 /* gop_netc_com_phy_selector_config(netComplex); */
3640 case MV_NETC_SECOND_PHASE:
3641 /* De-assert the relevant port HB reset */
3642 gop_netc_port_rf_reset(priv, gop_id, 1);
3647 static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3649 u32 c = priv->netc_config;
3651 if (c & MV_NETC_GE_MAC2_SGMII)
3652 gop_netc_mac_to_sgmii(priv, 2, phase);
3654 gop_netc_mac_to_xgmii(priv, 2, phase);
3656 if (c & MV_NETC_GE_MAC3_SGMII) {
3657 gop_netc_mac_to_sgmii(priv, 3, phase);
3659 gop_netc_mac_to_xgmii(priv, 3, phase);
3660 if (c & MV_NETC_GE_MAC3_RGMII)
3661 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3663 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3666 /* Activate gop ports 0, 2, 3 */
3667 gop_netc_active_port(priv, 0, 1);
3668 gop_netc_active_port(priv, 2, 1);
3669 gop_netc_active_port(priv, 3, 1);
3671 if (phase == MV_NETC_SECOND_PHASE) {
3672 /* Enable the GOP internal clock logic */
3673 gop_netc_gop_clock_logic_set(priv, 1);
3674 /* De-assert GOP unit reset */
3675 gop_netc_gop_reset(priv, 1);
3681 /* Set defaults to the MVPP2 port */
3682 static void mvpp2_defaults_set(struct mvpp2_port *port)
3684 int tx_port_num, val, queue, ptxq, lrxq;
3686 if (port->priv->hw_version == MVPP21) {
3687 /* Configure port to loopback if needed */
3688 if (port->flags & MVPP2_F_LOOPBACK)
3689 mvpp2_port_loopback_set(port);
3691 /* Update TX FIFO MIN Threshold */
3692 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3693 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3694 /* Min. TX threshold must be less than minimal packet length */
3695 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3696 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3699 /* Disable Legacy WRR, Disable EJP, Release from reset */
3700 tx_port_num = mvpp2_egress_port(port);
3701 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3703 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3705 /* Close bandwidth for all queues */
3706 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3707 ptxq = mvpp2_txq_phys(port->id, queue);
3708 mvpp2_write(port->priv,
3709 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3712 /* Set refill period to 1 usec, refill tokens
3713 * and bucket size to maximum
3715 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3716 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3717 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3718 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3719 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3720 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3721 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3722 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3724 /* Set MaximumLowLatencyPacketSize value to 256 */
3725 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3726 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3727 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3729 /* Enable Rx cache snoop */
3730 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3731 queue = port->rxqs[lrxq]->id;
3732 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3733 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3734 MVPP2_SNOOP_BUF_HDR_MASK;
3735 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3739 /* Enable/disable receiving packets */
3740 static void mvpp2_ingress_enable(struct mvpp2_port *port)
3745 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3746 queue = port->rxqs[lrxq]->id;
3747 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3748 val &= ~MVPP2_RXQ_DISABLE_MASK;
3749 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3753 static void mvpp2_ingress_disable(struct mvpp2_port *port)
3758 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3759 queue = port->rxqs[lrxq]->id;
3760 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3761 val |= MVPP2_RXQ_DISABLE_MASK;
3762 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3766 /* Enable transmit via physical egress queue
3767 * - HW starts take descriptors from DRAM
3769 static void mvpp2_egress_enable(struct mvpp2_port *port)
3773 int tx_port_num = mvpp2_egress_port(port);
3775 /* Enable all initialized TXs. */
3777 for (queue = 0; queue < txq_number; queue++) {
3778 struct mvpp2_tx_queue *txq = port->txqs[queue];
3780 if (txq->descs != NULL)
3781 qmap |= (1 << queue);
3784 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3785 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3788 /* Disable transmit via physical egress queue
3789 * - HW doesn't take descriptors from DRAM
3791 static void mvpp2_egress_disable(struct mvpp2_port *port)
3795 int tx_port_num = mvpp2_egress_port(port);
3797 /* Issue stop command for active channels only */
3798 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3799 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3800 MVPP2_TXP_SCHED_ENQ_MASK;
3802 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3803 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3805 /* Wait for all Tx activity to terminate. */
3808 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
3809 netdev_warn(port->dev,
3810 "Tx stop timed out, status=0x%08x\n",
3817 /* Check port TX Command register that all
3818 * Tx queues are stopped
3820 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3821 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3824 /* Rx descriptors helper methods */
3826 /* Get number of Rx descriptors occupied by received packets */
3828 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3830 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3832 return val & MVPP2_RXQ_OCCUPIED_MASK;
3835 /* Update Rx queue status with the number of occupied and available
3836 * Rx descriptor slots.
3839 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3840 int used_count, int free_count)
3842 /* Decrement the number of used descriptors and increment count
3843 * increment the number of free descriptors.
3845 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3847 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3850 /* Get pointer to next RX descriptor to be processed by SW */
3851 static inline struct mvpp2_rx_desc *
3852 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3854 int rx_desc = rxq->next_desc_to_proc;
3856 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3857 prefetch(rxq->descs + rxq->next_desc_to_proc);
3858 return rxq->descs + rx_desc;
3861 /* Set rx queue offset */
3862 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3863 int prxq, int offset)
3867 /* Convert offset from bytes to units of 32 bytes */
3868 offset = offset >> 5;
3870 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3871 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3874 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3875 MVPP2_RXQ_PACKET_OFFSET_MASK);
3877 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3880 /* Obtain BM cookie information from descriptor */
3881 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3882 struct mvpp2_rx_desc *rx_desc)
3884 int cpu = smp_processor_id();
3887 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3888 MVPP2_RXD_BM_POOL_ID_MASK) >>
3889 MVPP2_RXD_BM_POOL_ID_OFFS;
3891 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3892 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3895 /* Tx descriptors helper methods */
3897 /* Get number of Tx descriptors waiting to be transmitted by HW */
3898 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3899 struct mvpp2_tx_queue *txq)
3903 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3904 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3906 return val & MVPP2_TXQ_PENDING_MASK;
3909 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3910 static struct mvpp2_tx_desc *
3911 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3913 int tx_desc = txq->next_desc_to_proc;
3915 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3916 return txq->descs + tx_desc;
3919 /* Update HW with number of aggregated Tx descriptors to be sent */
3920 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3922 /* aggregated access - relevant TXQ number is written in TX desc */
3923 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3926 /* Get number of sent descriptors and decrement counter.
3927 * The number of sent descriptors is returned.
3930 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3931 struct mvpp2_tx_queue *txq)
3935 /* Reading status reg resets transmitted descriptor counter */
3936 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3938 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3939 MVPP2_TRANSMITTED_COUNT_OFFSET;
3942 static void mvpp2_txq_sent_counter_clear(void *arg)
3944 struct mvpp2_port *port = arg;
3947 for (queue = 0; queue < txq_number; queue++) {
3948 int id = port->txqs[queue]->id;
3950 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3954 /* Set max sizes for Tx queues */
3955 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3958 int txq, tx_port_num;
3960 mtu = port->pkt_size * 8;
3961 if (mtu > MVPP2_TXP_MTU_MAX)
3962 mtu = MVPP2_TXP_MTU_MAX;
3964 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3967 /* Indirect access to registers */
3968 tx_port_num = mvpp2_egress_port(port);
3969 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3972 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3973 val &= ~MVPP2_TXP_MTU_MAX;
3975 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3977 /* TXP token size and all TXQs token size must be larger that MTU */
3978 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3979 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3982 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3984 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3987 for (txq = 0; txq < txq_number; txq++) {
3988 val = mvpp2_read(port->priv,
3989 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3990 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3994 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3996 mvpp2_write(port->priv,
3997 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4003 /* Free Tx queue skbuffs */
4004 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4005 struct mvpp2_tx_queue *txq,
4006 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4010 for (i = 0; i < num; i++)
4011 mvpp2_txq_inc_get(txq_pcpu);
4014 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4017 int queue = fls(cause) - 1;
4019 return port->rxqs[queue];
4022 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4025 int queue = fls(cause) - 1;
4027 return port->txqs[queue];
4030 /* Rx/Tx queue initialization/cleanup methods */
4032 /* Allocate and initialize descriptors for aggr TXQ */
4033 static int mvpp2_aggr_txq_init(struct udevice *dev,
4034 struct mvpp2_tx_queue *aggr_txq,
4035 int desc_num, int cpu,
4040 /* Allocate memory for TX descriptors */
4041 aggr_txq->descs = buffer_loc.aggr_tx_descs;
4042 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
4043 if (!aggr_txq->descs)
4046 /* Make sure descriptor address is cache line size aligned */
4047 BUG_ON(aggr_txq->descs !=
4048 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4050 aggr_txq->last_desc = aggr_txq->size - 1;
4052 /* Aggr TXQ no reset WA */
4053 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4054 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4056 /* Set Tx descriptors queue starting address indirect
4059 if (priv->hw_version == MVPP21)
4060 txq_dma = aggr_txq->descs_dma;
4062 txq_dma = aggr_txq->descs_dma >>
4063 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4065 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
4066 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4071 /* Create a specified Rx queue */
4072 static int mvpp2_rxq_init(struct mvpp2_port *port,
4073 struct mvpp2_rx_queue *rxq)
4078 rxq->size = port->rx_ring_size;
4080 /* Allocate memory for RX descriptors */
4081 rxq->descs = buffer_loc.rx_descs;
4082 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
4086 BUG_ON(rxq->descs !=
4087 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4089 rxq->last_desc = rxq->size - 1;
4091 /* Zero occupied and non-occupied counters - direct access */
4092 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4094 /* Set Rx descriptors queue starting address - indirect access */
4095 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4096 if (port->priv->hw_version == MVPP21)
4097 rxq_dma = rxq->descs_dma;
4099 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4100 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
4101 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4102 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4105 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4107 /* Add number of descriptors ready for receiving packets */
4108 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4113 /* Push packets received by the RXQ to BM pool */
4114 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4115 struct mvpp2_rx_queue *rxq)
4119 rx_received = mvpp2_rxq_received(port, rxq->id);
4123 for (i = 0; i < rx_received; i++) {
4124 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4125 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
4127 mvpp2_pool_refill(port, bm,
4128 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4129 mvpp2_rxdesc_cookie_get(port, rx_desc));
4131 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4134 /* Cleanup Rx queue */
4135 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4136 struct mvpp2_rx_queue *rxq)
4138 mvpp2_rxq_drop_pkts(port, rxq);
4142 rxq->next_desc_to_proc = 0;
4145 /* Clear Rx descriptors queue starting address and size;
4146 * free descriptor number
4148 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4149 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4150 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4151 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4154 /* Create and initialize a Tx queue */
4155 static int mvpp2_txq_init(struct mvpp2_port *port,
4156 struct mvpp2_tx_queue *txq)
4159 int cpu, desc, desc_per_txq, tx_port_num;
4160 struct mvpp2_txq_pcpu *txq_pcpu;
4162 txq->size = port->tx_ring_size;
4164 /* Allocate memory for Tx descriptors */
4165 txq->descs = buffer_loc.tx_descs;
4166 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
4170 /* Make sure descriptor address is cache line size aligned */
4171 BUG_ON(txq->descs !=
4172 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4174 txq->last_desc = txq->size - 1;
4176 /* Set Tx descriptors queue starting address - indirect access */
4177 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4178 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
4179 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4180 MVPP2_TXQ_DESC_SIZE_MASK);
4181 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4182 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4183 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4184 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4185 val &= ~MVPP2_TXQ_PENDING_MASK;
4186 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4188 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4189 * for each existing TXQ.
4190 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4191 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4194 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4195 (txq->log_id * desc_per_txq);
4197 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4198 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4199 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
4201 /* WRR / EJP configuration - indirect access */
4202 tx_port_num = mvpp2_egress_port(port);
4203 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4205 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4206 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4207 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4208 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4209 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4211 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4212 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4215 for_each_present_cpu(cpu) {
4216 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4217 txq_pcpu->size = txq->size;
4223 /* Free allocated TXQ resources */
4224 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4225 struct mvpp2_tx_queue *txq)
4229 txq->next_desc_to_proc = 0;
4232 /* Set minimum bandwidth for disabled TXQs */
4233 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4235 /* Set Tx descriptors queue starting address and size */
4236 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4237 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4238 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4241 /* Cleanup Tx ports */
4242 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4244 struct mvpp2_txq_pcpu *txq_pcpu;
4245 int delay, pending, cpu;
4248 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4249 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4250 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4251 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4253 /* The napi queue has been stopped so wait for all packets
4254 * to be transmitted.
4258 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4259 netdev_warn(port->dev,
4260 "port %d: cleaning queue %d timed out\n",
4261 port->id, txq->log_id);
4267 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4270 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4271 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4273 for_each_present_cpu(cpu) {
4274 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4276 /* Release all packets */
4277 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4280 txq_pcpu->count = 0;
4281 txq_pcpu->txq_put_index = 0;
4282 txq_pcpu->txq_get_index = 0;
4286 /* Cleanup all Tx queues */
4287 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4289 struct mvpp2_tx_queue *txq;
4293 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4295 /* Reset Tx ports and delete Tx queues */
4296 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4297 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4299 for (queue = 0; queue < txq_number; queue++) {
4300 txq = port->txqs[queue];
4301 mvpp2_txq_clean(port, txq);
4302 mvpp2_txq_deinit(port, txq);
4305 mvpp2_txq_sent_counter_clear(port);
4307 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4308 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4311 /* Cleanup all Rx queues */
4312 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4316 for (queue = 0; queue < rxq_number; queue++)
4317 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4320 /* Init all Rx queues for port */
4321 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4325 for (queue = 0; queue < rxq_number; queue++) {
4326 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4333 mvpp2_cleanup_rxqs(port);
4337 /* Init all tx queues for port */
4338 static int mvpp2_setup_txqs(struct mvpp2_port *port)
4340 struct mvpp2_tx_queue *txq;
4343 for (queue = 0; queue < txq_number; queue++) {
4344 txq = port->txqs[queue];
4345 err = mvpp2_txq_init(port, txq);
4350 mvpp2_txq_sent_counter_clear(port);
4354 mvpp2_cleanup_txqs(port);
4359 static void mvpp2_link_event(struct mvpp2_port *port)
4361 struct phy_device *phydev = port->phy_dev;
4362 int status_change = 0;
4366 if ((port->speed != phydev->speed) ||
4367 (port->duplex != phydev->duplex)) {
4370 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4371 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4372 MVPP2_GMAC_CONFIG_GMII_SPEED |
4373 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4374 MVPP2_GMAC_AN_SPEED_EN |
4375 MVPP2_GMAC_AN_DUPLEX_EN);
4378 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4380 if (phydev->speed == SPEED_1000)
4381 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4382 else if (phydev->speed == SPEED_100)
4383 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4385 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4387 port->duplex = phydev->duplex;
4388 port->speed = phydev->speed;
4392 if (phydev->link != port->link) {
4393 if (!phydev->link) {
4398 port->link = phydev->link;
4402 if (status_change) {
4404 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4405 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4406 MVPP2_GMAC_FORCE_LINK_DOWN);
4407 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4408 mvpp2_egress_enable(port);
4409 mvpp2_ingress_enable(port);
4411 mvpp2_ingress_disable(port);
4412 mvpp2_egress_disable(port);
4417 /* Main RX/TX processing routines */
4419 /* Display more error info */
4420 static void mvpp2_rx_error(struct mvpp2_port *port,
4421 struct mvpp2_rx_desc *rx_desc)
4423 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4424 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
4426 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4427 case MVPP2_RXD_ERR_CRC:
4428 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
4431 case MVPP2_RXD_ERR_OVERRUN:
4432 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
4435 case MVPP2_RXD_ERR_RESOURCE:
4436 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
4442 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4443 static int mvpp2_rx_refill(struct mvpp2_port *port,
4444 struct mvpp2_bm_pool *bm_pool,
4445 u32 bm, dma_addr_t dma_addr)
4447 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
4451 /* Set hw internals when starting port */
4452 static void mvpp2_start_dev(struct mvpp2_port *port)
4454 switch (port->phy_interface) {
4455 case PHY_INTERFACE_MODE_RGMII:
4456 case PHY_INTERFACE_MODE_RGMII_ID:
4457 case PHY_INTERFACE_MODE_SGMII:
4458 mvpp2_gmac_max_rx_size_set(port);
4463 mvpp2_txp_max_tx_size_set(port);
4465 if (port->priv->hw_version == MVPP21)
4466 mvpp2_port_enable(port);
4468 gop_port_enable(port, 1);
4471 /* Set hw internals when stopping port */
4472 static void mvpp2_stop_dev(struct mvpp2_port *port)
4474 /* Stop new packets from arriving to RXQs */
4475 mvpp2_ingress_disable(port);
4477 mvpp2_egress_disable(port);
4479 if (port->priv->hw_version == MVPP21)
4480 mvpp2_port_disable(port);
4482 gop_port_enable(port, 0);
4485 static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
4487 struct phy_device *phy_dev;
4489 if (!port->init || port->link == 0) {
4490 phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
4491 dev, port->phy_interface);
4494 * If the phy doesn't match with any existing u-boot drivers the
4495 * phy framework will connect it to generic one which
4496 * uid == 0xffffffff. In this case act as if the phy wouldn't be
4497 * declared in dts. Otherwise in case of 3310 (for which the
4498 * driver doesn't exist) the link will not be correctly
4499 * detected. Removing phy entry from dts in case of 3310 is not
4500 * an option because it is required for the phy_fw_down
4504 phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
4505 netdev_warn(port->dev,
4506 "Marking phy as invalid, link will not be checked\n");
4507 /* set phy_addr to invalid value */
4508 port->phyaddr = PHY_MAX_ADDR;
4509 mvpp2_egress_enable(port);
4510 mvpp2_ingress_enable(port);
4515 port->phy_dev = phy_dev;
4517 netdev_err(port->dev, "cannot connect to phy\n");
4520 phy_dev->supported &= PHY_GBIT_FEATURES;
4521 phy_dev->advertising = phy_dev->supported;
4523 port->phy_dev = phy_dev;
4528 phy_config(phy_dev);
4529 phy_startup(phy_dev);
4531 printf("%s: No link\n", phy_dev->dev->name);
4535 mvpp2_egress_enable(port);
4536 mvpp2_ingress_enable(port);
4540 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4542 unsigned char mac_bcast[ETH_ALEN] = {
4543 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4546 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4548 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4551 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4552 port->dev_addr, true);
4554 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
4557 err = mvpp2_prs_def_flow(port);
4559 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4563 /* Allocate the Rx/Tx queues */
4564 err = mvpp2_setup_rxqs(port);
4566 netdev_err(port->dev, "cannot allocate Rx queues\n");
4570 err = mvpp2_setup_txqs(port);
4572 netdev_err(port->dev, "cannot allocate Tx queues\n");
4576 if (port->phyaddr < PHY_MAX_ADDR) {
4577 mvpp2_phy_connect(dev, port);
4578 mvpp2_link_event(port);
4580 mvpp2_egress_enable(port);
4581 mvpp2_ingress_enable(port);
4584 mvpp2_start_dev(port);
4589 /* No Device ops here in U-Boot */
4591 /* Driver initialization */
4593 static void mvpp2_port_power_up(struct mvpp2_port *port)
4595 struct mvpp2 *priv = port->priv;
4597 /* On PPv2.2 the GoP / interface configuration has already been done */
4598 if (priv->hw_version == MVPP21)
4599 mvpp2_port_mii_set(port);
4600 mvpp2_port_periodic_xon_disable(port);
4601 if (priv->hw_version == MVPP21)
4602 mvpp2_port_fc_adv_enable(port);
4603 mvpp2_port_reset(port);
4606 /* Initialize port HW */
4607 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4609 struct mvpp2 *priv = port->priv;
4610 struct mvpp2_txq_pcpu *txq_pcpu;
4611 int queue, cpu, err;
4613 if (port->first_rxq + rxq_number >
4614 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4618 mvpp2_egress_disable(port);
4619 if (priv->hw_version == MVPP21)
4620 mvpp2_port_disable(port);
4622 gop_port_enable(port, 0);
4624 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4629 /* Associate physical Tx queues to this port and initialize.
4630 * The mapping is predefined.
4632 for (queue = 0; queue < txq_number; queue++) {
4633 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4634 struct mvpp2_tx_queue *txq;
4636 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4640 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4645 txq->id = queue_phy_id;
4646 txq->log_id = queue;
4647 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4648 for_each_present_cpu(cpu) {
4649 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4650 txq_pcpu->cpu = cpu;
4653 port->txqs[queue] = txq;
4656 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4661 /* Allocate and initialize Rx queue for this port */
4662 for (queue = 0; queue < rxq_number; queue++) {
4663 struct mvpp2_rx_queue *rxq;
4665 /* Map physical Rx queue to port's logical Rx queue */
4666 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4669 /* Map this Rx queue to a physical queue */
4670 rxq->id = port->first_rxq + queue;
4671 rxq->port = port->id;
4672 rxq->logic_rxq = queue;
4674 port->rxqs[queue] = rxq;
4678 /* Create Rx descriptor rings */
4679 for (queue = 0; queue < rxq_number; queue++) {
4680 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4682 rxq->size = port->rx_ring_size;
4683 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4684 rxq->time_coal = MVPP2_RX_COAL_USEC;
4687 mvpp2_ingress_disable(port);
4689 /* Port default configuration */
4690 mvpp2_defaults_set(port);
4692 /* Port's classifier configuration */
4693 mvpp2_cls_oversize_rxq_set(port);
4694 mvpp2_cls_port_config(port);
4696 /* Provide an initial Rx packet size */
4697 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4699 /* Initialize pools for swf */
4700 err = mvpp2_swf_bm_pool_init(port);
4707 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
4709 int port_node = dev_of_offset(dev);
4710 const char *phy_mode_str;
4717 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
4721 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
4723 dev_err(&pdev->dev, "could not find phy address\n");
4726 parent = fdt_parent_offset(gd->fdt_blob, phy_node);
4727 ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
4732 /* phy_addr is set to invalid value */
4733 phyaddr = PHY_MAX_ADDR;
4736 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
4738 phy_mode = phy_get_interface_by_name(phy_mode_str);
4739 if (phy_mode == -1) {
4740 dev_err(&pdev->dev, "incorrect phy mode\n");
4744 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4746 dev_err(&pdev->dev, "missing port-id value\n");
4750 #if CONFIG_IS_ENABLED(DM_GPIO)
4751 gpio_request_by_name(dev, "phy-reset-gpios", 0,
4752 &port->phy_reset_gpio, GPIOD_IS_OUT);
4753 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
4754 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
4759 * Not sure if this DT property "phy-speed" will get accepted, so
4760 * this might change later
4762 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
4763 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
4767 if (port->priv->hw_version == MVPP21)
4768 port->first_rxq = port->id * rxq_number;
4770 port->first_rxq = port->id * port->priv->max_port_rxqs;
4771 port->phy_interface = phy_mode;
4772 port->phyaddr = phyaddr;
4777 #if CONFIG_IS_ENABLED(DM_GPIO)
4778 /* Port GPIO initialization */
4779 static void mvpp2_gpio_init(struct mvpp2_port *port)
4781 if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
4782 dm_gpio_set_value(&port->phy_reset_gpio, 1);
4784 dm_gpio_set_value(&port->phy_reset_gpio, 0);
4787 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
4788 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
4792 /* Ports initialization */
4793 static int mvpp2_port_probe(struct udevice *dev,
4794 struct mvpp2_port *port,
4800 port->tx_ring_size = MVPP2_MAX_TXD;
4801 port->rx_ring_size = MVPP2_MAX_RXD;
4803 err = mvpp2_port_init(dev, port);
4805 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
4808 mvpp2_port_power_up(port);
4810 #if CONFIG_IS_ENABLED(DM_GPIO)
4811 mvpp2_gpio_init(port);
4814 priv->port_list[port->id] = port;
4819 /* Initialize decoding windows */
4820 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4826 for (i = 0; i < 6; i++) {
4827 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4828 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4831 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4836 for (i = 0; i < dram->num_cs; i++) {
4837 const struct mbus_dram_window *cs = dram->cs + i;
4839 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4840 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4841 dram->mbus_dram_target_id);
4843 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4844 (cs->size - 1) & 0xffff0000);
4846 win_enable |= (1 << i);
4849 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4852 /* Initialize Rx FIFO's */
4853 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4857 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4858 if (priv->hw_version == MVPP22) {
4861 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4862 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4864 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4865 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4866 } else if (port == 1) {
4868 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4869 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4871 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4872 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4875 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4876 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4878 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4879 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4882 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4883 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4884 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4885 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4889 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4890 MVPP2_RX_FIFO_PORT_MIN_PKT);
4891 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4894 /* Initialize Tx FIFO's */
4895 static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4899 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4900 /* Port 0 supports 10KB TX FIFO */
4902 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4903 MVPP22_TX_FIFO_SIZE_MASK;
4905 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4906 MVPP22_TX_FIFO_SIZE_MASK;
4908 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4912 static void mvpp2_axi_init(struct mvpp2 *priv)
4914 u32 val, rdval, wrval;
4916 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4918 /* AXI Bridge Configuration */
4920 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4921 << MVPP22_AXI_ATTR_CACHE_OFFS;
4922 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4923 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4925 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4926 << MVPP22_AXI_ATTR_CACHE_OFFS;
4927 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4928 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4931 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4932 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4935 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4936 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4937 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4938 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4941 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4942 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4944 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4945 << MVPP22_AXI_CODE_CACHE_OFFS;
4946 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4947 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4948 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4949 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4951 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4952 << MVPP22_AXI_CODE_CACHE_OFFS;
4953 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4954 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4956 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4958 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4959 << MVPP22_AXI_CODE_CACHE_OFFS;
4960 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4961 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4963 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
4966 /* Initialize network controller common part HW */
4967 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
4969 const struct mbus_dram_target_info *dram_target_info;
4973 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4974 if ((rxq_number > priv->max_port_rxqs) ||
4975 (txq_number > MVPP2_MAX_TXQ)) {
4976 dev_err(&pdev->dev, "invalid queue size parameter\n");
4980 if (priv->hw_version == MVPP22)
4981 mvpp2_axi_init(priv);
4983 /* MBUS windows configuration */
4984 dram_target_info = mvebu_mbus_dram_info();
4985 if (dram_target_info)
4986 mvpp2_conf_mbus_windows(dram_target_info, priv);
4989 if (priv->hw_version == MVPP21) {
4990 /* Disable HW PHY polling */
4991 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4992 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4993 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4995 /* Enable HW PHY polling */
4996 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4997 val |= MVPP22_SMI_POLLING_EN;
4998 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5001 /* Allocate and initialize aggregated TXQs */
5002 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
5003 sizeof(struct mvpp2_tx_queue),
5005 if (!priv->aggr_txqs)
5008 for_each_present_cpu(i) {
5009 priv->aggr_txqs[i].id = i;
5010 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5011 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5012 MVPP2_AGGR_TXQ_SIZE, i, priv);
5018 mvpp2_rx_fifo_init(priv);
5021 if (priv->hw_version == MVPP22)
5022 mvpp2_tx_fifo_init(priv);
5024 if (priv->hw_version == MVPP21)
5025 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5026 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5028 /* Allow cache snoop when transmiting packets */
5029 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5031 /* Buffer Manager initialization */
5032 err = mvpp2_bm_init(dev, priv);
5036 /* Parser default initialization */
5037 err = mvpp2_prs_default_init(dev, priv);
5041 /* Classifier default initialization */
5042 mvpp2_cls_init(priv);
5047 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5049 struct mvpp2_port *port = dev_get_priv(dev);
5050 struct mvpp2_rx_desc *rx_desc;
5051 struct mvpp2_bm_pool *bm_pool;
5052 dma_addr_t dma_addr;
5054 int pool, rx_bytes, err;
5056 struct mvpp2_rx_queue *rxq;
5059 if (port->phyaddr < PHY_MAX_ADDR)
5060 if (!port->phy_dev->link)
5063 /* Process RX packets */
5064 rxq = port->rxqs[0];
5066 /* Get number of received packets and clamp the to-do */
5067 rx_received = mvpp2_rxq_received(port, rxq->id);
5069 /* Return if no packets are received */
5073 rx_desc = mvpp2_rxq_next_desc_get(rxq);
5074 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5075 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5076 rx_bytes -= MVPP2_MH_SIZE;
5077 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
5079 bm = mvpp2_bm_cookie_build(port, rx_desc);
5080 pool = mvpp2_bm_cookie_pool_get(bm);
5081 bm_pool = &port->priv->bm_pools[pool];
5083 /* In case of an error, release the requested buffer pointer
5084 * to the Buffer Manager. This request process is controlled
5085 * by the hardware, and the information about the buffer is
5086 * comprised by the RX descriptor.
5088 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5089 mvpp2_rx_error(port, rx_desc);
5090 /* Return the buffer to the pool */
5091 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
5095 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
5097 netdev_err(port->dev, "failed to refill BM pools\n");
5101 /* Update Rx queue management counters */
5103 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5105 /* give packet to stack - skip on first n bytes */
5106 data = (u8 *)dma_addr + 2 + 32;
5112 * No cache invalidation needed here, since the rx_buffer's are
5113 * located in a uncached memory region
5120 static int mvpp2_send(struct udevice *dev, void *packet, int length)
5122 struct mvpp2_port *port = dev_get_priv(dev);
5123 struct mvpp2_tx_queue *txq, *aggr_txq;
5124 struct mvpp2_tx_desc *tx_desc;
5128 if (port->phyaddr < PHY_MAX_ADDR)
5129 if (!port->phy_dev->link)
5132 txq = port->txqs[0];
5133 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5135 /* Get a descriptor for the first part of the packet */
5136 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5137 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5138 mvpp2_txdesc_size_set(port, tx_desc, length);
5139 mvpp2_txdesc_offset_set(port, tx_desc,
5140 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5141 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5142 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
5143 /* First and Last descriptor */
5144 mvpp2_txdesc_cmd_set(port, tx_desc,
5145 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5146 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
5149 flush_dcache_range((unsigned long)packet,
5150 (unsigned long)packet + ALIGN(length, PKTALIGN));
5152 /* Enable transmit */
5154 mvpp2_aggr_txq_pend_desc_add(port, 1);
5156 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5160 if (timeout++ > 10000) {
5161 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5164 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5169 if (timeout++ > 10000) {
5170 printf("timeout: packet not sent\n");
5173 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5179 static int mvpp2_start(struct udevice *dev)
5181 struct eth_pdata *pdata = dev_get_platdata(dev);
5182 struct mvpp2_port *port = dev_get_priv(dev);
5184 /* Load current MAC address */
5185 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5187 /* Reconfigure parser accept the original MAC address */
5188 mvpp2_prs_update_mac_da(port, port->dev_addr);
5190 switch (port->phy_interface) {
5191 case PHY_INTERFACE_MODE_RGMII:
5192 case PHY_INTERFACE_MODE_RGMII_ID:
5193 case PHY_INTERFACE_MODE_SGMII:
5194 mvpp2_port_power_up(port);
5199 mvpp2_open(dev, port);
5204 static void mvpp2_stop(struct udevice *dev)
5206 struct mvpp2_port *port = dev_get_priv(dev);
5208 mvpp2_stop_dev(port);
5209 mvpp2_cleanup_rxqs(port);
5210 mvpp2_cleanup_txqs(port);
5213 static int mvpp2_write_hwaddr(struct udevice *dev)
5215 struct mvpp2_port *port = dev_get_priv(dev);
5217 return mvpp2_prs_update_mac_da(port, port->dev_addr);
5220 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
5222 writel(port->phyaddr, port->priv->iface_base +
5223 MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
5228 static int mvpp2_base_probe(struct udevice *dev)
5230 struct mvpp2 *priv = dev_get_priv(dev);
5235 /* Save hw-version */
5236 priv->hw_version = dev_get_driver_data(dev);
5239 * U-Boot special buffer handling:
5241 * Allocate buffer area for descs and rx_buffers. This is only
5242 * done once for all interfaces. As only one interface can
5243 * be active. Make this area DMA-safe by disabling the D-cache
5246 /* Align buffer area for descs and rx_buffers to 1MiB */
5247 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
5248 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5249 BD_SPACE, DCACHE_OFF);
5251 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5252 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
5254 buffer_loc.tx_descs =
5255 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
5256 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
5258 buffer_loc.rx_descs =
5259 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
5260 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
5262 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5263 buffer_loc.bm_pool[i] =
5264 (unsigned long *)((unsigned long)bd_space + size);
5265 if (priv->hw_version == MVPP21)
5266 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5268 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
5271 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
5272 buffer_loc.rx_buffer[i] =
5273 (unsigned long *)((unsigned long)bd_space + size);
5274 size += RX_BUFFER_SIZE;
5277 /* Clear the complete area so that all descriptors are cleared */
5278 memset(bd_space, 0, size);
5280 /* Save base addresses for later use */
5281 priv->base = (void *)devfdt_get_addr_index(dev, 0);
5282 if (IS_ERR(priv->base))
5283 return PTR_ERR(priv->base);
5285 if (priv->hw_version == MVPP21) {
5286 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
5287 if (IS_ERR(priv->lms_base))
5288 return PTR_ERR(priv->lms_base);
5290 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
5291 if (IS_ERR(priv->iface_base))
5292 return PTR_ERR(priv->iface_base);
5294 /* Store common base addresses for all ports */
5295 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5296 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5297 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
5300 if (priv->hw_version == MVPP21)
5301 priv->max_port_rxqs = 8;
5303 priv->max_port_rxqs = 32;
5308 static int mvpp2_probe(struct udevice *dev)
5310 struct mvpp2_port *port = dev_get_priv(dev);
5311 struct mvpp2 *priv = dev_get_priv(dev->parent);
5314 /* Only call the probe function for the parent once */
5315 if (!priv->probe_done)
5316 err = mvpp2_base_probe(dev->parent);
5320 err = phy_info_parse(dev, port);
5325 * We need the port specific io base addresses at this stage, since
5326 * gop_port_init() accesses these registers
5328 if (priv->hw_version == MVPP21) {
5329 int priv_common_regs_num = 2;
5331 port->base = (void __iomem *)devfdt_get_addr_index(
5332 dev->parent, priv_common_regs_num + port->id);
5333 if (IS_ERR(port->base))
5334 return PTR_ERR(port->base);
5336 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5338 if (port->id == -1) {
5339 dev_err(&pdev->dev, "missing gop-port-id value\n");
5343 port->base = priv->iface_base + MVPP22_PORT_BASE +
5344 port->gop_id * MVPP22_PORT_OFFSET;
5346 /* Set phy address of the port */
5347 if (port->phyaddr < PHY_MAX_ADDR)
5348 mvpp22_smi_phy_addr_cfg(port);
5351 gop_port_init(port);
5354 if (!priv->probe_done) {
5355 /* Initialize network controller */
5356 err = mvpp2_init(dev, priv);
5358 dev_err(&pdev->dev, "failed to initialize controller\n");
5361 priv->num_ports = 0;
5362 priv->probe_done = 1;
5365 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5369 if (priv->hw_version == MVPP22) {
5370 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5371 port->phy_interface);
5373 /* Netcomplex configurations for all ports */
5374 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5375 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5382 * Empty BM pool and stop its activity before the OS is started
5384 static int mvpp2_remove(struct udevice *dev)
5386 struct mvpp2_port *port = dev_get_priv(dev);
5387 struct mvpp2 *priv = port->priv;
5392 if (priv->num_ports)
5395 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5396 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5401 static const struct eth_ops mvpp2_ops = {
5402 .start = mvpp2_start,
5406 .write_hwaddr = mvpp2_write_hwaddr
5409 static struct driver mvpp2_driver = {
5412 .probe = mvpp2_probe,
5413 .remove = mvpp2_remove,
5415 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
5416 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5417 .flags = DM_FLAG_ACTIVE_DMA,
5421 * Use a MISC device to bind the n instances (child nodes) of the
5422 * network base controller in UCLASS_ETH.
5424 static int mvpp2_base_bind(struct udevice *parent)
5426 const void *blob = gd->fdt_blob;
5427 int node = dev_of_offset(parent);
5428 struct uclass_driver *drv;
5429 struct udevice *dev;
5430 struct eth_pdata *plat;
5436 /* Lookup eth driver */
5437 drv = lists_uclass_lookup(UCLASS_ETH);
5439 puts("Cannot find eth driver\n");
5443 base_id_add = base_id;
5445 fdt_for_each_subnode(subnode, blob, node) {
5446 /* Increment base_id for all subnodes, also the disabled ones */
5449 /* Skip disabled ports */
5450 if (!fdtdec_get_is_enabled(blob, subnode))
5453 plat = calloc(1, sizeof(*plat));
5457 id = fdtdec_get_int(blob, subnode, "port-id", -1);
5460 name = calloc(1, 16);
5465 sprintf(name, "mvpp2-%d", id);
5467 /* Create child device UCLASS_ETH and bind it */
5468 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
5469 dev_set_of_offset(dev, subnode);
5475 static const struct udevice_id mvpp2_ids[] = {
5477 .compatible = "marvell,armada-375-pp2",
5481 .compatible = "marvell,armada-7k-pp22",
5487 U_BOOT_DRIVER(mvpp2_base) = {
5488 .name = "mvpp2_base",
5490 .of_match = mvpp2_ids,
5491 .bind = mvpp2_base_bind,
5492 .priv_auto_alloc_size = sizeof(struct mvpp2),