2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
5 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
7 * Based on the Linux version which is:
8 * Copyright (C) 2012 Marvell
10 * Rami Rosen <rosenr@marvell.com>
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * SPDX-License-Identifier: GPL-2.0
23 #include <linux/errno.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/soc.h>
29 #include <linux/compat.h>
30 #include <linux/mbus.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #if !defined(CONFIG_PHYLIB)
35 # error Marvell mvneta requires PHYLIB
38 /* Some linux -> U-Boot compatibility stuff */
39 #define netdev_err(dev, fmt, args...) \
41 #define netdev_warn(dev, fmt, args...) \
43 #define netdev_info(dev, fmt, args...) \
46 #define CONFIG_NR_CPUS 1
47 #define ETH_HLEN 14 /* Total octets in header */
49 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
50 #define WRAP (2 + ETH_HLEN + 4 + 32)
52 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
54 #define MVNETA_SMI_TIMEOUT 10000
57 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
58 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
59 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
60 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
61 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
62 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
63 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
64 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
65 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
66 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
67 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
68 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
69 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
70 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
71 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
72 #define MVNETA_PORT_RX_RESET 0x1cc0
73 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
74 #define MVNETA_PHY_ADDR 0x2000
75 #define MVNETA_PHY_ADDR_MASK 0x1f
76 #define MVNETA_SMI 0x2004
77 #define MVNETA_PHY_REG_MASK 0x1f
78 /* SMI register fields */
79 #define MVNETA_SMI_DATA_OFFS 0 /* Data */
80 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
81 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
82 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
83 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
84 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
85 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
86 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
87 #define MVNETA_MBUS_RETRY 0x2010
88 #define MVNETA_UNIT_INTR_CAUSE 0x2080
89 #define MVNETA_UNIT_CONTROL 0x20B0
90 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
91 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
92 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
93 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
94 #define MVNETA_WIN_SIZE_MASK (0xffff0000)
95 #define MVNETA_BASE_ADDR_ENABLE 0x2290
96 #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
97 #define MVNETA_PORT_ACCESS_PROTECT 0x2294
98 #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
99 #define MVNETA_PORT_CONFIG 0x2400
100 #define MVNETA_UNI_PROMISC_MODE BIT(0)
101 #define MVNETA_DEF_RXQ(q) ((q) << 1)
102 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
103 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
104 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
105 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
106 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
107 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
108 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
109 MVNETA_DEF_RXQ_ARP(q) | \
110 MVNETA_DEF_RXQ_TCP(q) | \
111 MVNETA_DEF_RXQ_UDP(q) | \
112 MVNETA_DEF_RXQ_BPDU(q) | \
113 MVNETA_TX_UNSET_ERR_SUM | \
114 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
115 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
116 #define MVNETA_MAC_ADDR_LOW 0x2414
117 #define MVNETA_MAC_ADDR_HIGH 0x2418
118 #define MVNETA_SDMA_CONFIG 0x241c
119 #define MVNETA_SDMA_BRST_SIZE_16 4
120 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
121 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
122 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
123 #define MVNETA_DESC_SWAP BIT(6)
124 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
125 #define MVNETA_PORT_STATUS 0x2444
126 #define MVNETA_TX_IN_PRGRS BIT(1)
127 #define MVNETA_TX_FIFO_EMPTY BIT(8)
128 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
129 #define MVNETA_SERDES_CFG 0x24A0
130 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
131 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
132 #define MVNETA_TYPE_PRIO 0x24bc
133 #define MVNETA_FORCE_UNI BIT(21)
134 #define MVNETA_TXQ_CMD_1 0x24e4
135 #define MVNETA_TXQ_CMD 0x2448
136 #define MVNETA_TXQ_DISABLE_SHIFT 8
137 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
138 #define MVNETA_ACC_MODE 0x2500
139 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
140 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
141 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
142 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
144 /* Exception Interrupt Port/Queue Cause register */
146 #define MVNETA_INTR_NEW_CAUSE 0x25a0
147 #define MVNETA_INTR_NEW_MASK 0x25a4
149 /* bits 0..7 = TXQ SENT, one bit per queue.
150 * bits 8..15 = RXQ OCCUP, one bit per queue.
151 * bits 16..23 = RXQ FREE, one bit per queue.
152 * bit 29 = OLD_REG_SUM, see old reg ?
153 * bit 30 = TX_ERR_SUM, one bit for 4 ports
154 * bit 31 = MISC_SUM, one bit for 4 ports
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
157 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
159 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
161 #define MVNETA_INTR_OLD_CAUSE 0x25a8
162 #define MVNETA_INTR_OLD_MASK 0x25ac
164 /* Data Path Port/Queue Cause Register */
165 #define MVNETA_INTR_MISC_CAUSE 0x25b0
166 #define MVNETA_INTR_MISC_MASK 0x25b4
167 #define MVNETA_INTR_ENABLE 0x25b8
169 #define MVNETA_RXQ_CMD 0x2680
170 #define MVNETA_RXQ_DISABLE_SHIFT 8
171 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
172 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
173 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
174 #define MVNETA_GMAC_CTRL_0 0x2c00
175 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
176 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
177 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
178 #define MVNETA_GMAC_CTRL_2 0x2c08
179 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
180 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
181 #define MVNETA_GMAC2_PORT_RESET BIT(6)
182 #define MVNETA_GMAC_STATUS 0x2c10
183 #define MVNETA_GMAC_LINK_UP BIT(0)
184 #define MVNETA_GMAC_SPEED_1000 BIT(1)
185 #define MVNETA_GMAC_SPEED_100 BIT(2)
186 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
187 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
188 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
189 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
190 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
191 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
192 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
193 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
194 #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
195 #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
196 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
197 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
198 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
199 #define MVNETA_GMAC_SET_FC_EN BIT(8)
200 #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
201 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
202 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
203 #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
204 #define MVNETA_MIB_COUNTERS_BASE 0x3080
205 #define MVNETA_MIB_LATE_COLLISION 0x7c
206 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
207 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
208 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
209 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
210 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
211 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
212 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
213 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
214 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
215 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
216 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
217 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
218 #define MVNETA_PORT_TX_RESET 0x3cf0
219 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
220 #define MVNETA_TX_MTU 0x3e0c
221 #define MVNETA_TX_TOKEN_SIZE 0x3e14
222 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
223 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
224 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
226 /* Descriptor ring Macros */
227 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
228 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
230 /* Various constants */
233 #define MVNETA_TXDONE_COAL_PKTS 16
234 #define MVNETA_RX_COAL_PKTS 32
235 #define MVNETA_RX_COAL_USEC 100
237 /* The two bytes Marvell header. Either contains a special value used
238 * by Marvell switches when a specific hardware mode is enabled (not
239 * supported by this driver) or is filled automatically by zeroes on
240 * the RX side. Those two bytes being at the front of the Ethernet
241 * header, they allow to have the IP header aligned on a 4 bytes
242 * boundary automatically: the hardware skips those two bytes on its
245 #define MVNETA_MH_SIZE 2
247 #define MVNETA_VLAN_TAG_LEN 4
249 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
250 #define MVNETA_TX_CSUM_MAX_SIZE 9800
251 #define MVNETA_ACC_MODE_EXT 1
253 /* Timeout constants */
254 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
255 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
256 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
258 #define MVNETA_TX_MTU_MAX 0x3ffff
260 /* Max number of Rx descriptors */
261 #define MVNETA_MAX_RXD 16
263 /* Max number of Tx descriptors */
264 #define MVNETA_MAX_TXD 16
266 /* descriptor aligned size */
267 #define MVNETA_DESC_ALIGNED_SIZE 32
271 struct mvneta_rx_queue *rxqs;
272 struct mvneta_tx_queue *txqs;
278 phy_interface_t phy_interface;
285 struct phy_device *phydev;
289 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
290 * layout of the transmit and reception DMA descriptors, and their
291 * layout is therefore defined by the hardware design
294 #define MVNETA_TX_L3_OFF_SHIFT 0
295 #define MVNETA_TX_IP_HLEN_SHIFT 8
296 #define MVNETA_TX_L4_UDP BIT(16)
297 #define MVNETA_TX_L3_IP6 BIT(17)
298 #define MVNETA_TXD_IP_CSUM BIT(18)
299 #define MVNETA_TXD_Z_PAD BIT(19)
300 #define MVNETA_TXD_L_DESC BIT(20)
301 #define MVNETA_TXD_F_DESC BIT(21)
302 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
303 MVNETA_TXD_L_DESC | \
305 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
306 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
308 #define MVNETA_RXD_ERR_CRC 0x0
309 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
310 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
311 #define MVNETA_RXD_ERR_LEN BIT(18)
312 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
313 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
314 #define MVNETA_RXD_L3_IP4 BIT(25)
315 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
316 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
318 struct mvneta_tx_desc {
319 u32 command; /* Options used by HW for packet transmitting.*/
320 u16 reserverd1; /* csum_l4 (for future use) */
321 u16 data_size; /* Data size of transmitted packet in bytes */
322 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
323 u32 reserved2; /* hw_cmd - (for future use, PMT) */
324 u32 reserved3[4]; /* Reserved - (for future use) */
327 struct mvneta_rx_desc {
328 u32 status; /* Info about received packet */
329 u16 reserved1; /* pnc_info - (for future use, PnC) */
330 u16 data_size; /* Size of received packet in bytes */
332 u32 buf_phys_addr; /* Physical address of the buffer */
333 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
335 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
336 u16 reserved3; /* prefetch_cmd, for future use */
337 u16 reserved4; /* csum_l4 - (for future use, PnC) */
339 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
340 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
343 struct mvneta_tx_queue {
344 /* Number of this TX queue, in the range 0-7 */
347 /* Number of TX DMA descriptors in the descriptor ring */
350 /* Index of last TX DMA descriptor that was inserted */
353 /* Index of the TX DMA descriptor to be cleaned up */
356 /* Virtual address of the TX DMA descriptors array */
357 struct mvneta_tx_desc *descs;
359 /* DMA address of the TX DMA descriptors array */
360 dma_addr_t descs_phys;
362 /* Index of the last TX DMA descriptor */
365 /* Index of the next TX DMA descriptor to process */
366 int next_desc_to_proc;
369 struct mvneta_rx_queue {
370 /* rx queue number, in the range 0-7 */
373 /* num of rx descriptors in the rx descriptor ring */
376 /* Virtual address of the RX DMA descriptors array */
377 struct mvneta_rx_desc *descs;
379 /* DMA address of the RX DMA descriptors array */
380 dma_addr_t descs_phys;
382 /* Index of the last RX DMA descriptor */
385 /* Index of the next RX DMA descriptor to process */
386 int next_desc_to_proc;
389 /* U-Boot doesn't use the queues, so set the number to 1 */
390 static int rxq_number = 1;
391 static int txq_number = 1;
394 struct buffer_location {
395 struct mvneta_tx_desc *tx_descs;
396 struct mvneta_rx_desc *rx_descs;
401 * All 4 interfaces use the same global buffer, since only one interface
402 * can be enabled at once
404 static struct buffer_location buffer_loc;
407 * Page table entries are set to 1MB, or multiples of 1MB
408 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
410 #define BD_SPACE (1 << 20)
413 * Dummy implementation that can be overwritten by a board
416 __weak int board_network_enable(struct mii_dev *bus)
421 /* Utility/helper methods */
423 /* Write helper method */
424 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
426 writel(data, pp->base + offset);
429 /* Read helper method */
430 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
432 return readl(pp->base + offset);
435 /* Clear all MIB counters */
436 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
440 /* Perform dummy reads from MIB counters */
441 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
442 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
445 /* Rx descriptors helper methods */
447 /* Checks whether the RX descriptor having this status is both the first
448 * and the last descriptor for the RX packet. Each RX packet is currently
449 * received through a single RX descriptor, so not having each RX
450 * descriptor with its first and last bits set is an error
452 static int mvneta_rxq_desc_is_first_last(u32 status)
454 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
455 MVNETA_RXD_FIRST_LAST_DESC;
458 /* Add number of descriptors ready to receive new packets */
459 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
460 struct mvneta_rx_queue *rxq,
463 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
466 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
467 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
468 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
469 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
470 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
473 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
474 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
477 /* Get number of RX descriptors occupied by received packets */
478 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
479 struct mvneta_rx_queue *rxq)
483 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
484 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
487 /* Update num of rx desc called upon return from rx path or
488 * from mvneta_rxq_drop_pkts().
490 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
491 struct mvneta_rx_queue *rxq,
492 int rx_done, int rx_filled)
496 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
498 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
499 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
503 /* Only 255 descriptors can be added at once */
504 while ((rx_done > 0) || (rx_filled > 0)) {
505 if (rx_done <= 0xff) {
512 if (rx_filled <= 0xff) {
513 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
516 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
519 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
523 /* Get pointer to next RX descriptor to be processed by SW */
524 static struct mvneta_rx_desc *
525 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
527 int rx_desc = rxq->next_desc_to_proc;
529 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
530 return rxq->descs + rx_desc;
533 /* Tx descriptors helper methods */
535 /* Update HW with number of TX descriptors to be sent */
536 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
537 struct mvneta_tx_queue *txq,
542 /* Only 255 descriptors can be added at once ; Assume caller
543 * process TX descriptors in quanta less than 256
546 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
549 /* Get pointer to next TX descriptor to be processed (send) by HW */
550 static struct mvneta_tx_desc *
551 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
553 int tx_desc = txq->next_desc_to_proc;
555 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
556 return txq->descs + tx_desc;
559 /* Set rxq buf size */
560 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
561 struct mvneta_rx_queue *rxq,
566 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
568 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
569 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
571 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
574 static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
576 /* phy_addr is set to invalid value for fixed link */
577 return pp->phyaddr > PHY_MAX_ADDR;
581 /* Start the Ethernet port RX and TX activity */
582 static void mvneta_port_up(struct mvneta_port *pp)
587 /* Enable all initialized TXs. */
588 mvneta_mib_counters_clear(pp);
590 for (queue = 0; queue < txq_number; queue++) {
591 struct mvneta_tx_queue *txq = &pp->txqs[queue];
592 if (txq->descs != NULL)
593 q_map |= (1 << queue);
595 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
597 /* Enable all initialized RXQs. */
599 for (queue = 0; queue < rxq_number; queue++) {
600 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
601 if (rxq->descs != NULL)
602 q_map |= (1 << queue);
604 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
607 /* Stop the Ethernet port activity */
608 static void mvneta_port_down(struct mvneta_port *pp)
613 /* Stop Rx port activity. Check port Rx activity. */
614 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
616 /* Issue stop command for active channels only */
618 mvreg_write(pp, MVNETA_RXQ_CMD,
619 val << MVNETA_RXQ_DISABLE_SHIFT);
621 /* Wait for all Rx activity to terminate. */
624 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
626 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
632 val = mvreg_read(pp, MVNETA_RXQ_CMD);
633 } while (val & 0xff);
635 /* Stop Tx port activity. Check port Tx activity. Issue stop
636 * command for active channels only
638 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
641 mvreg_write(pp, MVNETA_TXQ_CMD,
642 (val << MVNETA_TXQ_DISABLE_SHIFT));
644 /* Wait for all Tx activity to terminate. */
647 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
649 "TIMEOUT for TX stopped status=0x%08x\n",
655 /* Check TX Command reg that all Txqs are stopped */
656 val = mvreg_read(pp, MVNETA_TXQ_CMD);
658 } while (val & 0xff);
660 /* Double check to verify that TX FIFO is empty */
663 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
665 "TX FIFO empty timeout status=0x08%x\n",
671 val = mvreg_read(pp, MVNETA_PORT_STATUS);
672 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
673 (val & MVNETA_TX_IN_PRGRS));
678 /* Enable the port by setting the port enable bit of the MAC control register */
679 static void mvneta_port_enable(struct mvneta_port *pp)
684 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
685 val |= MVNETA_GMAC0_PORT_ENABLE;
686 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
689 /* Disable the port and wait for about 200 usec before retuning */
690 static void mvneta_port_disable(struct mvneta_port *pp)
694 /* Reset the Enable bit in the Serial Control Register */
695 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
696 val &= ~MVNETA_GMAC0_PORT_ENABLE;
697 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
702 /* Multicast tables methods */
704 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
705 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
713 val = 0x1 | (queue << 1);
714 val |= (val << 24) | (val << 16) | (val << 8);
717 for (offset = 0; offset <= 0xc; offset += 4)
718 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
721 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
722 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
730 val = 0x1 | (queue << 1);
731 val |= (val << 24) | (val << 16) | (val << 8);
734 for (offset = 0; offset <= 0xfc; offset += 4)
735 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
738 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
739 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
745 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
748 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
749 val = 0x1 | (queue << 1);
750 val |= (val << 24) | (val << 16) | (val << 8);
753 for (offset = 0; offset <= 0xfc; offset += 4)
754 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
757 /* This method sets defaults to the NETA port:
758 * Clears interrupt Cause and Mask registers.
759 * Clears all MAC tables.
760 * Sets defaults to all registers.
761 * Resets RX and TX descriptor rings.
763 * This method can be called after mvneta_port_down() to return the port
764 * settings to defaults.
766 static void mvneta_defaults_set(struct mvneta_port *pp)
772 /* Clear all Cause registers */
773 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
774 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
775 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
777 /* Mask all interrupts */
778 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
779 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
780 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
781 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
783 /* Enable MBUS Retry bit16 */
784 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
786 /* Set CPU queue access map - all CPUs have access to all RX
787 * queues and to all TX queues
789 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
790 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
791 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
792 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
794 /* Reset RX and TX DMAs */
795 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
796 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
798 /* Disable Legacy WRR, Disable EJP, Release from reset */
799 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
800 for (queue = 0; queue < txq_number; queue++) {
801 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
802 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
805 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
806 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
808 /* Set Port Acceleration Mode */
809 val = MVNETA_ACC_MODE_EXT;
810 mvreg_write(pp, MVNETA_ACC_MODE, val);
812 /* Update val of portCfg register accordingly with all RxQueue types */
813 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
814 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
817 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
818 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
820 /* Build PORT_SDMA_CONFIG_REG */
823 /* Default burst size */
824 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
825 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
826 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
828 /* Assign port SDMA configuration */
829 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
831 /* Enable PHY polling in hardware if not in fixed-link mode */
832 if (!mvneta_port_is_fixed_link(pp)) {
833 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
834 val |= MVNETA_PHY_POLLING_ENABLE;
835 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
838 mvneta_set_ucast_table(pp, -1);
839 mvneta_set_special_mcast_table(pp, -1);
840 mvneta_set_other_mcast_table(pp, -1);
843 /* Set unicast address */
844 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
847 unsigned int unicast_reg;
848 unsigned int tbl_offset;
849 unsigned int reg_offset;
851 /* Locate the Unicast table entry */
852 last_nibble = (0xf & last_nibble);
854 /* offset from unicast tbl base */
855 tbl_offset = (last_nibble / 4) * 4;
857 /* offset within the above reg */
858 reg_offset = last_nibble % 4;
860 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
863 /* Clear accepts frame bit at specified unicast DA tbl entry */
864 unicast_reg &= ~(0xff << (8 * reg_offset));
866 unicast_reg &= ~(0xff << (8 * reg_offset));
867 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
870 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
873 /* Set mac address */
874 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
881 mac_l = (addr[4] << 8) | (addr[5]);
882 mac_h = (addr[0] << 24) | (addr[1] << 16) |
883 (addr[2] << 8) | (addr[3] << 0);
885 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
886 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
889 /* Accept frames of this address */
890 mvneta_set_ucast_addr(pp, addr[5], queue);
893 static int mvneta_write_hwaddr(struct udevice *dev)
895 mvneta_mac_addr_set(dev_get_priv(dev),
896 ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
902 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
903 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
904 u32 phys_addr, u32 cookie)
906 rx_desc->buf_cookie = cookie;
907 rx_desc->buf_phys_addr = phys_addr;
910 /* Decrement sent descriptors counter */
911 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
912 struct mvneta_tx_queue *txq,
917 /* Only 255 TX descriptors can be updated at once */
918 while (sent_desc > 0xff) {
919 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
920 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
921 sent_desc = sent_desc - 0xff;
924 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
925 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
928 /* Get number of TX descriptors already sent by HW */
929 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
930 struct mvneta_tx_queue *txq)
935 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
936 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
937 MVNETA_TXQ_SENT_DESC_SHIFT;
942 /* Display more error info */
943 static void mvneta_rx_error(struct mvneta_port *pp,
944 struct mvneta_rx_desc *rx_desc)
946 u32 status = rx_desc->status;
948 if (!mvneta_rxq_desc_is_first_last(status)) {
950 "bad rx status %08x (buffer oversize), size=%d\n",
951 status, rx_desc->data_size);
955 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
956 case MVNETA_RXD_ERR_CRC:
957 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
958 status, rx_desc->data_size);
960 case MVNETA_RXD_ERR_OVERRUN:
961 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
962 status, rx_desc->data_size);
964 case MVNETA_RXD_ERR_LEN:
965 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
966 status, rx_desc->data_size);
968 case MVNETA_RXD_ERR_RESOURCE:
969 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
970 status, rx_desc->data_size);
975 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
978 return &pp->rxqs[rxq];
982 /* Drop packets received by the RXQ and free buffers */
983 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
984 struct mvneta_rx_queue *rxq)
988 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
990 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
993 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
994 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
999 for (i = 0; i < num; i++) {
1002 /* U-Boot special: Fill in the rx buffer addresses */
1003 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
1004 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
1007 /* Add this number of RX descriptors as non occupied (ready to
1010 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1015 /* Rx/Tx queue initialization/cleanup methods */
1017 /* Create a specified RX queue */
1018 static int mvneta_rxq_init(struct mvneta_port *pp,
1019 struct mvneta_rx_queue *rxq)
1022 rxq->size = pp->rx_ring_size;
1024 /* Allocate memory for RX descriptors */
1025 rxq->descs_phys = (dma_addr_t)rxq->descs;
1026 if (rxq->descs == NULL)
1029 rxq->last_desc = rxq->size - 1;
1031 /* Set Rx descriptors queue starting address */
1032 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1033 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1035 /* Fill RXQ with buffers from RX pool */
1036 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1037 mvneta_rxq_fill(pp, rxq, rxq->size);
1042 /* Cleanup Rx queue */
1043 static void mvneta_rxq_deinit(struct mvneta_port *pp,
1044 struct mvneta_rx_queue *rxq)
1046 mvneta_rxq_drop_pkts(pp, rxq);
1050 rxq->next_desc_to_proc = 0;
1051 rxq->descs_phys = 0;
1054 /* Create and initialize a tx queue */
1055 static int mvneta_txq_init(struct mvneta_port *pp,
1056 struct mvneta_tx_queue *txq)
1058 txq->size = pp->tx_ring_size;
1060 /* Allocate memory for TX descriptors */
1061 txq->descs_phys = (dma_addr_t)txq->descs;
1062 if (txq->descs == NULL)
1065 txq->last_desc = txq->size - 1;
1067 /* Set maximum bandwidth for enabled TXQs */
1068 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1069 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1071 /* Set Tx descriptors queue starting address */
1072 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1073 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1078 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1079 static void mvneta_txq_deinit(struct mvneta_port *pp,
1080 struct mvneta_tx_queue *txq)
1084 txq->next_desc_to_proc = 0;
1085 txq->descs_phys = 0;
1087 /* Set minimum bandwidth for disabled TXQs */
1088 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1089 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1091 /* Set Tx descriptors queue starting address and size */
1092 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1093 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1096 /* Cleanup all Tx queues */
1097 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1101 for (queue = 0; queue < txq_number; queue++)
1102 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1105 /* Cleanup all Rx queues */
1106 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1110 for (queue = 0; queue < rxq_number; queue++)
1111 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1115 /* Init all Rx queues */
1116 static int mvneta_setup_rxqs(struct mvneta_port *pp)
1120 for (queue = 0; queue < rxq_number; queue++) {
1121 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1123 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
1125 mvneta_cleanup_rxqs(pp);
1133 /* Init all tx queues */
1134 static int mvneta_setup_txqs(struct mvneta_port *pp)
1138 for (queue = 0; queue < txq_number; queue++) {
1139 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1141 netdev_err(pp->dev, "%s: can't create txq=%d\n",
1143 mvneta_cleanup_txqs(pp);
1151 static void mvneta_start_dev(struct mvneta_port *pp)
1153 /* start the Rx/Tx activity */
1154 mvneta_port_enable(pp);
1157 static void mvneta_adjust_link(struct udevice *dev)
1159 struct mvneta_port *pp = dev_get_priv(dev);
1160 struct phy_device *phydev = pp->phydev;
1161 int status_change = 0;
1163 if (mvneta_port_is_fixed_link(pp)) {
1164 debug("Using fixed link, skip link adjust\n");
1169 if ((pp->speed != phydev->speed) ||
1170 (pp->duplex != phydev->duplex)) {
1173 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1174 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1175 MVNETA_GMAC_CONFIG_GMII_SPEED |
1176 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1177 MVNETA_GMAC_AN_SPEED_EN |
1178 MVNETA_GMAC_AN_DUPLEX_EN);
1181 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1183 if (phydev->speed == SPEED_1000)
1184 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1186 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1188 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1190 pp->duplex = phydev->duplex;
1191 pp->speed = phydev->speed;
1195 if (phydev->link != pp->link) {
1196 if (!phydev->link) {
1201 pp->link = phydev->link;
1205 if (status_change) {
1207 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1208 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1209 MVNETA_GMAC_FORCE_LINK_DOWN);
1210 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1213 mvneta_port_down(pp);
1218 static int mvneta_open(struct udevice *dev)
1220 struct mvneta_port *pp = dev_get_priv(dev);
1223 ret = mvneta_setup_rxqs(pp);
1227 ret = mvneta_setup_txqs(pp);
1231 mvneta_adjust_link(dev);
1233 mvneta_start_dev(pp);
1239 static int mvneta_init2(struct mvneta_port *pp)
1244 mvneta_port_disable(pp);
1246 /* Set port default values */
1247 mvneta_defaults_set(pp);
1249 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1254 /* U-Boot special: use preallocated area */
1255 pp->txqs[0].descs = buffer_loc.tx_descs;
1257 /* Initialize TX descriptor rings */
1258 for (queue = 0; queue < txq_number; queue++) {
1259 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1261 txq->size = pp->tx_ring_size;
1264 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1271 /* U-Boot special: use preallocated area */
1272 pp->rxqs[0].descs = buffer_loc.rx_descs;
1274 /* Create Rx descriptor rings */
1275 for (queue = 0; queue < rxq_number; queue++) {
1276 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1278 rxq->size = pp->rx_ring_size;
1284 /* platform glue : initialize decoding windows */
1287 * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
1288 * First layer is: GbE Address window that resides inside the GBE unit,
1289 * Second layer is: Fabric address window which is located in the NIC400
1291 * To simplify the address decode configuration for Armada3700, we bypass the
1292 * first layer of GBE decode window by setting the first window to 4GB.
1294 static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
1297 * Set window size to 4GB, to bypass GBE address decode, leave the
1298 * work to MBUS decode window
1300 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
1302 /* Enable GBE address decode window 0 by set bit 0 to 0 */
1303 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
1304 MVNETA_BASE_ADDR_ENABLE_BIT);
1306 /* Set GBE address decode window 0 to full Access (read or write) */
1307 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
1308 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
1311 static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1313 const struct mbus_dram_target_info *dram;
1318 dram = mvebu_mbus_dram_info();
1319 for (i = 0; i < 6; i++) {
1320 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1321 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1324 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1330 for (i = 0; i < dram->num_cs; i++) {
1331 const struct mbus_dram_window *cs = dram->cs + i;
1332 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1333 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1335 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1336 (cs->size - 1) & 0xffff0000);
1338 win_enable &= ~(1 << i);
1339 win_protect |= 3 << (2 * i);
1342 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1345 /* Power up the port */
1346 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1350 /* MAC Cause register should be cleared */
1351 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1353 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1355 /* Even though it might look weird, when we're configured in
1356 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1359 case PHY_INTERFACE_MODE_QSGMII:
1360 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1361 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1363 case PHY_INTERFACE_MODE_SGMII:
1364 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1365 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1367 case PHY_INTERFACE_MODE_RGMII:
1368 case PHY_INTERFACE_MODE_RGMII_ID:
1369 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1375 /* Cancel Port Reset */
1376 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1377 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1379 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1380 MVNETA_GMAC2_PORT_RESET) != 0)
1386 /* Device initialization routine */
1387 static int mvneta_init(struct udevice *dev)
1389 struct eth_pdata *pdata = dev_get_platdata(dev);
1390 struct mvneta_port *pp = dev_get_priv(dev);
1393 pp->tx_ring_size = MVNETA_MAX_TXD;
1394 pp->rx_ring_size = MVNETA_MAX_RXD;
1396 err = mvneta_init2(pp);
1398 dev_err(&pdev->dev, "can't init eth hal\n");
1402 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
1404 err = mvneta_port_power_up(pp, pp->phy_interface);
1406 dev_err(&pdev->dev, "can't power up port\n");
1410 /* Call open() now as it needs to be done before runing send() */
1416 /* U-Boot only functions follow here */
1418 /* SMI / MDIO functions */
1420 static int smi_wait_ready(struct mvneta_port *pp)
1422 u32 timeout = MVNETA_SMI_TIMEOUT;
1425 /* wait till the SMI is not busy */
1427 /* read smi register */
1428 smi_reg = mvreg_read(pp, MVNETA_SMI);
1429 if (timeout-- == 0) {
1430 printf("Error: SMI busy timeout\n");
1433 } while (smi_reg & MVNETA_SMI_BUSY);
1439 * mvneta_mdio_read - miiphy_read callback function.
1441 * Returns 16bit phy register value, or 0xffff on error
1443 static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
1445 struct mvneta_port *pp = bus->priv;
1449 /* check parameters */
1450 if (addr > MVNETA_PHY_ADDR_MASK) {
1451 printf("Error: Invalid PHY address %d\n", addr);
1455 if (reg > MVNETA_PHY_REG_MASK) {
1456 printf("Err: Invalid register offset %d\n", reg);
1460 /* wait till the SMI is not busy */
1461 if (smi_wait_ready(pp) < 0)
1464 /* fill the phy address and regiser offset and read opcode */
1465 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1466 | (reg << MVNETA_SMI_REG_ADDR_OFFS)
1467 | MVNETA_SMI_OPCODE_READ;
1469 /* write the smi register */
1470 mvreg_write(pp, MVNETA_SMI, smi_reg);
1472 /* wait till read value is ready */
1473 timeout = MVNETA_SMI_TIMEOUT;
1476 /* read smi register */
1477 smi_reg = mvreg_read(pp, MVNETA_SMI);
1478 if (timeout-- == 0) {
1479 printf("Err: SMI read ready timeout\n");
1482 } while (!(smi_reg & MVNETA_SMI_READ_VALID));
1484 /* Wait for the data to update in the SMI register */
1485 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
1488 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
1492 * mvneta_mdio_write - miiphy_write callback function.
1494 * Returns 0 if write succeed, -EINVAL on bad parameters
1497 static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1500 struct mvneta_port *pp = bus->priv;
1503 /* check parameters */
1504 if (addr > MVNETA_PHY_ADDR_MASK) {
1505 printf("Error: Invalid PHY address %d\n", addr);
1509 if (reg > MVNETA_PHY_REG_MASK) {
1510 printf("Err: Invalid register offset %d\n", reg);
1514 /* wait till the SMI is not busy */
1515 if (smi_wait_ready(pp) < 0)
1518 /* fill the phy addr and reg offset and write opcode and data */
1519 smi_reg = value << MVNETA_SMI_DATA_OFFS;
1520 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1521 | (reg << MVNETA_SMI_REG_ADDR_OFFS);
1522 smi_reg &= ~MVNETA_SMI_OPCODE_READ;
1524 /* write the smi register */
1525 mvreg_write(pp, MVNETA_SMI, smi_reg);
1530 static int mvneta_start(struct udevice *dev)
1532 struct mvneta_port *pp = dev_get_priv(dev);
1533 struct phy_device *phydev;
1535 mvneta_port_power_up(pp, pp->phy_interface);
1537 if (!pp->init || pp->link == 0) {
1538 if (mvneta_port_is_fixed_link(pp)) {
1545 val = MVNETA_GMAC_FORCE_LINK_UP |
1546 MVNETA_GMAC_IB_BYPASS_AN_EN |
1547 MVNETA_GMAC_SET_FC_EN |
1548 MVNETA_GMAC_ADVERT_FC_EN |
1549 MVNETA_GMAC_SAMPLE_TX_CFG_EN;
1552 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1554 if (pp->speed == SPEED_1000)
1555 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1556 else if (pp->speed == SPEED_100)
1557 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1559 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1561 /* Set phy address of the port */
1562 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
1564 phydev = phy_connect(pp->bus, pp->phyaddr, dev,
1567 pp->phydev = phydev;
1569 phy_startup(phydev);
1570 if (!phydev->link) {
1571 printf("%s: No link.\n", phydev->dev->name);
1575 /* Full init on first call */
1582 /* Upon all following calls, this is enough */
1584 mvneta_port_enable(pp);
1589 static int mvneta_send(struct udevice *dev, void *packet, int length)
1591 struct mvneta_port *pp = dev_get_priv(dev);
1592 struct mvneta_tx_queue *txq = &pp->txqs[0];
1593 struct mvneta_tx_desc *tx_desc;
1597 /* Get a descriptor for the first part of the packet */
1598 tx_desc = mvneta_txq_next_desc_get(txq);
1600 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
1601 tx_desc->data_size = length;
1602 flush_dcache_range((ulong)packet,
1603 (ulong)packet + ALIGN(length, PKTALIGN));
1605 /* First and Last descriptor */
1606 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1607 mvneta_txq_pend_desc_add(pp, txq, 1);
1609 /* Wait for packet to be sent (queue might help with speed here) */
1610 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1611 while (!sent_desc) {
1612 if (timeout++ > 10000) {
1613 printf("timeout: packet not sent\n");
1616 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1619 /* txDone has increased - hw sent packet */
1620 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1625 static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
1627 struct mvneta_port *pp = dev_get_priv(dev);
1629 struct mvneta_rx_queue *rxq;
1633 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1634 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1637 struct mvneta_rx_desc *rx_desc;
1638 unsigned char *data;
1642 * No cache invalidation needed here, since the desc's are
1643 * located in a uncached memory region
1645 rx_desc = mvneta_rxq_next_desc_get(rxq);
1647 rx_status = rx_desc->status;
1648 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1649 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1650 mvneta_rx_error(pp, rx_desc);
1651 /* leave the descriptor untouched */
1655 /* 2 bytes for marvell header. 4 bytes for crc */
1656 rx_bytes = rx_desc->data_size - 6;
1658 /* give packet to stack - skip on first 2 bytes */
1659 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
1661 * No cache invalidation needed here, since the rx_buffer's are
1662 * located in a uncached memory region
1667 * Only mark one descriptor as free
1668 * since only one was processed
1670 mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
1676 static int mvneta_probe(struct udevice *dev)
1678 struct eth_pdata *pdata = dev_get_platdata(dev);
1679 struct mvneta_port *pp = dev_get_priv(dev);
1680 void *blob = (void *)gd->fdt_blob;
1681 int node = dev_of_offset(dev);
1682 struct mii_dev *bus;
1689 * Allocate buffer area for descs and rx_buffers. This is only
1690 * done once for all interfaces. As only one interface can
1691 * be active. Make this area DMA safe by disabling the D-cache
1693 if (!buffer_loc.tx_descs) {
1694 /* Align buffer area for descs and rx_buffers to 1MiB */
1695 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
1696 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
1698 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
1699 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
1700 ((phys_addr_t)bd_space +
1701 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
1702 buffer_loc.rx_buffers = (phys_addr_t)
1704 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
1705 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
1708 pp->base = (void __iomem *)pdata->iobase;
1710 /* Configure MBUS address windows */
1711 if (device_is_compatible(dev, "marvell,armada-3700-neta"))
1712 mvneta_bypass_mbus_windows(pp);
1714 mvneta_conf_mbus_windows(pp);
1716 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
1717 pp->phy_interface = pdata->phy_interface;
1719 /* fetch 'fixed-link' property from 'neta' node */
1720 fl_node = fdt_subnode_offset(blob, node, "fixed-link");
1721 if (fl_node != -FDT_ERR_NOTFOUND) {
1722 /* set phy_addr to invalid value for fixed link */
1723 pp->phyaddr = PHY_MAX_ADDR + 1;
1724 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1725 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1727 /* Now read phyaddr from DT */
1728 addr = fdtdec_get_int(blob, node, "phy", 0);
1729 addr = fdt_node_offset_by_phandle(blob, addr);
1730 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1735 printf("Failed to allocate MDIO bus\n");
1739 bus->read = mvneta_mdio_read;
1740 bus->write = mvneta_mdio_write;
1741 snprintf(bus->name, sizeof(bus->name), dev->name);
1742 bus->priv = (void *)pp;
1745 ret = mdio_register(bus);
1749 return board_network_enable(bus);
1752 static void mvneta_stop(struct udevice *dev)
1754 struct mvneta_port *pp = dev_get_priv(dev);
1756 mvneta_port_down(pp);
1757 mvneta_port_disable(pp);
1760 static const struct eth_ops mvneta_ops = {
1761 .start = mvneta_start,
1762 .send = mvneta_send,
1763 .recv = mvneta_recv,
1764 .stop = mvneta_stop,
1765 .write_hwaddr = mvneta_write_hwaddr,
1768 static int mvneta_ofdata_to_platdata(struct udevice *dev)
1770 struct eth_pdata *pdata = dev_get_platdata(dev);
1771 const char *phy_mode;
1773 pdata->iobase = devfdt_get_addr(dev);
1775 /* Get phy-mode / phy_interface from DT */
1776 pdata->phy_interface = -1;
1777 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1780 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1781 if (pdata->phy_interface == -1) {
1782 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1789 static const struct udevice_id mvneta_ids[] = {
1790 { .compatible = "marvell,armada-370-neta" },
1791 { .compatible = "marvell,armada-xp-neta" },
1792 { .compatible = "marvell,armada-3700-neta" },
1796 U_BOOT_DRIVER(mvneta) = {
1799 .of_match = mvneta_ids,
1800 .ofdata_to_platdata = mvneta_ofdata_to_platdata,
1801 .probe = mvneta_probe,
1803 .priv_auto_alloc_size = sizeof(struct mvneta_port),
1804 .platdata_auto_alloc_size = sizeof(struct eth_pdata),