1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 * Ingo Assmus <ingo.assmus@keymile.com>
10 * based on - Driver for MV64360X ethernet ports
11 * Copyright (C) 2002 rabeeh@galileo.co.il
21 #include <asm/global_data.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <asm/types.h>
26 #include <asm/system.h>
27 #include <asm/byteorder.h>
28 #include <asm/arch/cpu.h>
30 #if defined(CONFIG_ARCH_KIRKWOOD)
31 #include <asm/arch/soc.h>
32 #elif defined(CONFIG_ARCH_ORION5X)
33 #include <asm/arch/orion5x.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 #ifndef CONFIG_MVGBE_PORTS
41 # define CONFIG_MVGBE_PORTS {0, 0}
44 #define MV_PHY_ADR_REQUEST 0xee
45 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
46 #define MVGBE_PGADR_REG 22
48 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
49 static int smi_wait_ready(struct mvgbe_device *dmvgbe)
53 ret = wait_for_bit_le32(&MVGBE_SMI_REG, MVGBE_PHY_SMI_BUSY_MASK, false,
54 MVGBE_PHY_SMI_TIMEOUT_MS, false);
56 printf("Error: SMI busy timeout\n");
63 static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
64 int devad, int reg_ofs)
66 struct mvgbe_registers *regs = dmvgbe->regs;
71 /* Phyadr read request */
72 if (phy_adr == MV_PHY_ADR_REQUEST &&
73 reg_ofs == MV_PHY_ADR_REQUEST) {
75 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
78 /* check parameters */
79 if (phy_adr > PHYADR_MASK) {
80 printf("Err..(%s) Invalid PHY address %d\n",
84 if (reg_ofs > PHYREG_MASK) {
85 printf("Err..(%s) Invalid register offset %d\n",
90 /* wait till the SMI is not busy */
91 if (smi_wait_ready(dmvgbe) < 0)
94 /* fill the phy address and regiser offset and read opcode */
95 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
96 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
97 | MVGBE_PHY_SMI_OPCODE_READ;
99 /* write the smi register */
100 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
102 /*wait till read value is ready */
103 timeout = MVGBE_PHY_SMI_TIMEOUT;
106 /* read smi register */
107 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
108 if (timeout-- == 0) {
109 printf("Err..(%s) SMI read ready timeout\n",
113 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
115 /* Wait for the data to update in the SMI register */
116 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
119 data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
121 debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs,
128 * smi_reg_read - miiphy_read callback function.
130 * Returns 16bit phy register value, or -EFAULT on error
132 static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
136 struct mvgbe_device *dmvgbe = bus->priv;
138 struct eth_device *dev = eth_get_dev_by_name(bus->name);
139 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
142 return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
145 static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
146 int devad, int reg_ofs, u16 data)
148 struct mvgbe_registers *regs = dmvgbe->regs;
151 /* Phyadr write request*/
152 if (phy_adr == MV_PHY_ADR_REQUEST &&
153 reg_ofs == MV_PHY_ADR_REQUEST) {
154 MVGBE_REG_WR(regs->phyadr, data);
158 /* check parameters */
159 if (phy_adr > PHYADR_MASK) {
160 printf("Err..(%s) Invalid phy address\n", __func__);
163 if (reg_ofs > PHYREG_MASK) {
164 printf("Err..(%s) Invalid register offset\n", __func__);
168 /* wait till the SMI is not busy */
169 if (smi_wait_ready(dmvgbe) < 0)
172 /* fill the phy addr and reg offset and write opcode and data */
173 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
174 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
175 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
176 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
178 /* write the smi register */
179 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
185 * smi_reg_write - miiphy_write callback function.
187 * Returns 0 if write succeed, -EFAULT on error
189 static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
190 int reg_ofs, u16 data)
193 struct mvgbe_device *dmvgbe = bus->priv;
195 struct eth_device *dev = eth_get_dev_by_name(bus->name);
196 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
199 return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
203 /* Stop and checks all queues */
204 static void stop_queue(u32 * qreg)
208 reg_data = readl(qreg);
210 if (reg_data & 0xFF) {
211 /* Issue stop command for active channels only */
212 writel((reg_data << 8), qreg);
214 /* Wait for all queue activity to terminate. */
217 * Check port cause register that all queues
220 reg_data = readl(qreg);
222 while (reg_data & 0xFF);
227 * set_access_control - Config address decode parameters for Ethernet unit
229 * This function configures the address decode parameters for the Gigabit
230 * Ethernet Controller according the given parameters struct.
232 * @regs Register struct pointer.
233 * @param Address decode parameter struct.
235 static void set_access_control(struct mvgbe_registers *regs,
236 struct mvgbe_winparam *param)
240 /* Set access control register */
241 access_prot_reg = MVGBE_REG_RD(regs->epap);
242 /* clear window permission */
243 access_prot_reg &= (~(3 << (param->win * 2)));
244 access_prot_reg |= (param->access_ctrl << (param->win * 2));
245 MVGBE_REG_WR(regs->epap, access_prot_reg);
247 /* Set window Size reg (SR) */
248 MVGBE_REG_WR(regs->barsz[param->win].size,
249 (((param->size / 0x10000) - 1) << 16));
251 /* Set window Base address reg (BA) */
252 MVGBE_REG_WR(regs->barsz[param->win].bar,
253 (param->target | param->attrib | param->base_addr));
254 /* High address remap reg (HARR) */
256 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
258 /* Base address enable reg (BARER) */
259 if (param->enable == 1)
260 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
262 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
265 static void set_dram_access(struct mvgbe_registers *regs)
267 struct mvgbe_winparam win_param;
270 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
271 /* Set access parameters for DRAM bank i */
272 win_param.win = i; /* Use Ethernet window i */
273 /* Window target - DDR */
274 win_param.target = MVGBE_TARGET_DRAM;
275 /* Enable full access */
276 win_param.access_ctrl = EWIN_ACCESS_FULL;
277 win_param.high_addr = 0;
278 /* Get bank base and size */
279 win_param.base_addr = gd->bd->bi_dram[i].start;
280 win_param.size = gd->bd->bi_dram[i].size;
281 if (win_param.size == 0)
282 win_param.enable = 0;
284 win_param.enable = 1; /* Enable the access */
286 /* Enable DRAM bank */
289 win_param.attrib = EBAR_DRAM_CS0;
292 win_param.attrib = EBAR_DRAM_CS1;
295 win_param.attrib = EBAR_DRAM_CS2;
298 win_param.attrib = EBAR_DRAM_CS3;
301 /* invalid bank, disable access */
302 win_param.enable = 0;
303 win_param.attrib = 0;
306 /* Set the access control for address window(EPAPR) RD/WR */
307 set_access_control(regs, &win_param);
312 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
314 * Go through all the DA filter tables (Unicast, Special Multicast & Other
315 * Multicast) and set each entry to 0.
317 static void port_init_mac_tables(struct mvgbe_registers *regs)
321 /* Clear DA filter unicast table (Ex_dFUT) */
322 for (table_index = 0; table_index < 4; ++table_index)
323 MVGBE_REG_WR(regs->dfut[table_index], 0);
325 for (table_index = 0; table_index < 64; ++table_index) {
326 /* Clear DA filter special multicast table (Ex_dFSMT) */
327 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
328 /* Clear DA filter other multicast table (Ex_dFOMT) */
329 MVGBE_REG_WR(regs->dfomt[table_index], 0);
334 * port_uc_addr - This function Set the port unicast address table
336 * This function locates the proper entry in the Unicast table for the
337 * specified MAC nibble and sets its properties according to function
339 * This function add/removes MAC addresses from the port unicast address
342 * @uc_nibble Unicast MAC Address last nibble.
343 * @option 0 = Add, 1 = remove address.
345 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
347 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
354 /* Locate the Unicast table entry */
355 uc_nibble = (0xf & uc_nibble);
356 /* Register offset from unicast table base */
357 tbl_offset = (uc_nibble / 4);
358 /* Entry offset within the above register */
359 reg_offset = uc_nibble % 4;
362 case REJECT_MAC_ADDR:
364 * Clear accepts frame bit at specified unicast
367 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
368 unicast_reg &= (0xFF << (8 * reg_offset));
369 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
371 case ACCEPT_MAC_ADDR:
372 /* Set accepts frame bit at unicast DA filter table entry */
373 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
374 unicast_reg &= (0xFF << (8 * reg_offset));
375 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
376 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
385 * port_uc_addr_set - This function Set the port Unicast address.
387 static void port_uc_addr_set(struct mvgbe_device *dmvgbe, u8 *p_addr)
389 struct mvgbe_registers *regs = dmvgbe->regs;
393 mac_l = (p_addr[4] << 8) | (p_addr[5]);
394 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
397 MVGBE_REG_WR(regs->macal, mac_l);
398 MVGBE_REG_WR(regs->macah, mac_h);
400 /* Accept frames of this address */
401 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
405 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
407 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
409 struct mvgbe_rxdesc *p_rx_desc;
412 /* initialize the Rx descriptors ring */
413 p_rx_desc = dmvgbe->p_rxdesc;
414 for (i = 0; i < RINGSZ; i++) {
416 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
417 p_rx_desc->buf_size = PKTSIZE_ALIGN;
418 p_rx_desc->byte_cnt = 0;
419 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
420 if (i == (RINGSZ - 1))
421 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
423 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
424 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
425 p_rx_desc = p_rx_desc->nxtdesc_p;
428 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
431 static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
434 struct mvgbe_registers *regs = dmvgbe->regs;
435 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
436 !defined(CONFIG_PHYLIB) && \
437 !defined(CONFIG_DM_ETH) && \
438 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
442 mvgbe_init_rx_desc_ring(dmvgbe);
444 /* Clear the ethernet port interrupts */
445 MVGBE_REG_WR(regs->ic, 0);
446 MVGBE_REG_WR(regs->ice, 0);
447 /* Unmask RX buffer and TX end interrupt */
448 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
449 /* Unmask phy and link status changes interrupts */
450 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
452 set_dram_access(regs);
453 port_init_mac_tables(regs);
454 port_uc_addr_set(dmvgbe, enetaddr);
456 /* Assign port configuration and command. */
457 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
458 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
459 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
461 /* Assign port SDMA configuration */
462 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
463 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
464 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
465 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
466 /* Turn off the port/RXUQ bandwidth limitation */
467 MVGBE_REG_WR(regs->pmtu, 0);
469 /* Set maximum receive buffer to 9700 bytes */
470 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
471 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
473 /* Enable port initially */
474 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
477 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
478 * disable the leaky bucket mechanism .
480 MVGBE_REG_WR(regs->pmtu, 0);
482 /* Assignment of Rx CRDB of given RXUQ */
483 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
484 /* ensure previous write is done before enabling Rx DMA */
486 /* Enable port Rx. */
487 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
489 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
490 !defined(CONFIG_PHYLIB) && \
491 !defined(CONFIG_DM_ETH) && \
492 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
493 /* Wait up to 5s for the link status */
494 for (i = 0; i < 5; i++) {
497 miiphy_read(name, MV_PHY_ADR_REQUEST,
498 MV_PHY_ADR_REQUEST, &phyadr);
499 /* Return if we get link up */
500 if (miiphy_link(name, phyadr))
505 printf("No link on %s\n", name);
511 #ifndef CONFIG_DM_ETH
512 static int mvgbe_init(struct eth_device *dev)
514 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
516 return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name);
520 static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
522 struct mvgbe_registers *regs = dmvgbe->regs;
524 /* Disable all gigE address decoder */
525 MVGBE_REG_WR(regs->bare, 0x3f);
527 stop_queue(®s->tqc);
528 stop_queue(®s->rqc);
531 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
532 /* Set port is not reset */
533 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
534 #ifdef CONFIG_SYS_MII_MODE
535 /* Set MMI interface up */
536 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
538 /* Disable & mask ethernet port interrupts */
539 MVGBE_REG_WR(regs->ic, 0);
540 MVGBE_REG_WR(regs->ice, 0);
541 MVGBE_REG_WR(regs->pim, 0);
542 MVGBE_REG_WR(regs->peim, 0);
545 #ifndef CONFIG_DM_ETH
546 static int mvgbe_halt(struct eth_device *dev)
548 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
550 __mvgbe_halt(dmvgbe);
557 static int mvgbe_write_hwaddr(struct udevice *dev)
559 struct eth_pdata *pdata = dev_get_plat(dev);
561 port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr);
566 static int mvgbe_write_hwaddr(struct eth_device *dev)
568 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
570 /* Programs net device MAC address after initialization */
571 port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr);
576 static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
579 struct mvgbe_registers *regs = dmvgbe->regs;
580 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
581 void *p = (void *)dataptr;
585 /* Copy buffer if it's misaligned */
586 if ((u32) dataptr & 0x07) {
587 if (datasize > PKTSIZE_ALIGN) {
588 printf("Non-aligned data too large (%d)\n",
593 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
594 p = dmvgbe->p_aligned_txbuf;
597 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
598 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
599 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
600 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
601 p_txdesc->buf_ptr = (u8 *) p;
602 p_txdesc->byte_cnt = datasize;
604 /* Set this tc desc as zeroth TXUQ */
605 txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
606 writel((u32) p_txdesc, txuq0_reg_addr);
608 /* ensure tx desc writes above are performed before we start Tx DMA */
611 /* Apply send command using zeroth TXUQ */
612 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
615 * wait for packet xmit completion
617 cmd_sts = readl(&p_txdesc->cmd_sts);
618 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
619 /* return fail if error is detected */
620 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
621 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
622 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
623 printf("Err..(%s) in xmit packet\n", __func__);
626 cmd_sts = readl(&p_txdesc->cmd_sts);
631 #ifndef CONFIG_DM_ETH
632 static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
634 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
636 return __mvgbe_send(dmvgbe, dataptr, datasize);
640 static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
642 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
645 u32 rxdesc_curr_addr;
651 /* wait untill rx packet available or timeout */
653 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
656 debug("%s time out...\n", __func__);
659 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
661 if (p_rxdesc_curr->byte_cnt != 0) {
662 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
663 __func__, (u32) p_rxdesc_curr->byte_cnt,
664 (u32) p_rxdesc_curr->buf_ptr,
665 (u32) p_rxdesc_curr->cmd_sts);
669 * In case received a packet without first/last bits on
670 * OR the error summary bit is on,
671 * the packets needs to be dropeed.
673 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
676 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
677 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
679 printf("Err..(%s) Dropping packet spread on"
680 " multiple descriptors\n", __func__);
682 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
684 printf("Err..(%s) Dropping packet with errors\n",
688 /* !!! call higher layer processing */
689 debug("%s: Sending Received packet to"
690 " upper layer (net_process_received_packet)\n",
693 data = (p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET);
694 rx_bytes = (int)(p_rxdesc_curr->byte_cnt -
700 * free these descriptors and point next in the ring
702 p_rxdesc_curr->cmd_sts =
703 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
704 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
705 p_rxdesc_curr->byte_cnt = 0;
707 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
708 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
713 #ifndef CONFIG_DM_ETH
714 static int mvgbe_recv(struct eth_device *dev)
716 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
720 ret = __mvgbe_recv(dmvgbe, &packet);
724 net_process_received_packet(packet, ret);
730 #if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
731 #if defined(CONFIG_DM_ETH)
732 static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
734 phy_interface_t phy_interface,
737 static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
739 phy_interface_t phy_interface,
743 struct phy_device *phydev;
745 /* Set phy address of the port */
746 miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST,
749 /* Make sure the selected PHY page is 0 before connecting */
750 miiphy_write(dev->name, phyid, MVGBE_PGADR_REG, 0);
752 phydev = phy_connect(bus, phyid, dev, phy_interface);
754 printf("phy_connect failed\n");
763 #endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */
765 #if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH)
766 int mvgbe_phylib_init(struct eth_device *dev, int phyid)
769 struct phy_device *phydev;
774 printf("mdio_alloc failed\n");
777 bus->read = smi_reg_read;
778 bus->write = smi_reg_write;
779 strcpy(bus->name, dev->name);
781 ret = mdio_register(bus);
783 printf("mdio_register failed\n");
788 phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid);
796 static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
798 dmvgbe->p_rxdesc = memalign(PKTALIGN,
799 MV_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
800 if (!dmvgbe->p_rxdesc)
803 dmvgbe->p_rxbuf = memalign(PKTALIGN,
804 RINGSZ * PKTSIZE_ALIGN + 1);
805 if (!dmvgbe->p_rxbuf)
808 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
809 if (!dmvgbe->p_aligned_txbuf)
812 dmvgbe->p_txdesc = memalign(PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
813 if (!dmvgbe->p_txdesc)
819 free(dmvgbe->p_aligned_txbuf);
821 free(dmvgbe->p_rxbuf);
823 free(dmvgbe->p_rxdesc);
828 #ifndef CONFIG_DM_ETH
829 int mvgbe_initialize(struct bd_info *bis)
831 struct mvgbe_device *dmvgbe;
832 struct eth_device *dev;
835 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
837 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
838 /*skip if port is configured not to use */
839 if (used_ports[devnum] == 0)
842 dmvgbe = malloc(sizeof(struct mvgbe_device));
846 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
847 ret = mvgbe_alloc_buffers(dmvgbe);
849 printf("Err.. %s Failed to allocate memory\n",
857 /* must be less than sizeof(dev->name) */
858 sprintf(dev->name, "egiga%d", devnum);
862 dmvgbe->regs = (void *)MVGBE0_BASE;
864 #if defined(MVGBE1_BASE)
866 dmvgbe->regs = (void *)MVGBE1_BASE;
869 default: /* this should never happen */
870 printf("Err..(%s) Invalid device number %d\n",
875 dev->init = (void *)mvgbe_init;
876 dev->halt = (void *)mvgbe_halt;
877 dev->send = (void *)mvgbe_send;
878 dev->recv = (void *)mvgbe_recv;
879 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
883 #if defined(CONFIG_PHYLIB)
884 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
885 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
887 struct mii_dev *mdiodev = mdio_alloc();
890 strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
891 mdiodev->read = smi_reg_read;
892 mdiodev->write = smi_reg_write;
894 retval = mdio_register(mdiodev);
897 /* Set phy address of the port */
898 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
899 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
907 static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
909 return dmvgbe->phyaddr > PHY_MAX_ADDR;
912 static int mvgbe_start(struct udevice *dev)
914 struct eth_pdata *pdata = dev_get_plat(dev);
915 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
918 ret = __mvgbe_init(dmvgbe, pdata->enetaddr, dev->name);
922 if (!mvgbe_port_is_fixed_link(dmvgbe)) {
923 dmvgbe->phydev = __mvgbe_phy_init(dev, dmvgbe->bus,
924 dmvgbe->phy_interface,
933 static int mvgbe_send(struct udevice *dev, void *packet, int length)
935 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
937 return __mvgbe_send(dmvgbe, packet, length);
940 static int mvgbe_recv(struct udevice *dev, int flags, uchar **packetp)
942 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
944 return __mvgbe_recv(dmvgbe, packetp);
947 static void mvgbe_stop(struct udevice *dev)
949 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
951 __mvgbe_halt(dmvgbe);
954 static int mvgbe_probe(struct udevice *dev)
956 struct eth_pdata *pdata = dev_get_plat(dev);
957 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
961 ret = mvgbe_alloc_buffers(dmvgbe);
965 dmvgbe->regs = (void __iomem *)pdata->iobase;
969 printf("Failed to allocate MDIO bus\n");
973 bus->read = smi_reg_read;
974 bus->write = smi_reg_write;
975 snprintf(bus->name, sizeof(bus->name), dev->name);
979 ret = mdio_register(bus);
986 static const struct eth_ops mvgbe_ops = {
987 .start = mvgbe_start,
991 .write_hwaddr = mvgbe_write_hwaddr,
994 static int mvgbe_of_to_plat(struct udevice *dev)
996 struct eth_pdata *pdata = dev_get_plat(dev);
997 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
998 void *blob = (void *)gd->fdt_blob;
999 int node = dev_of_offset(dev);
1004 pdata->iobase = dev_read_addr(dev);
1005 pdata->phy_interface = -1;
1007 pnode = fdt_node_offset_by_compatible(blob, node,
1008 "marvell,kirkwood-eth-port");
1010 /* Get phy-mode / phy_interface from DT */
1011 pdata->phy_interface = dev_read_phy_mode(dev);
1012 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
1013 pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
1015 dmvgbe->phy_interface = pdata->phy_interface;
1017 /* fetch 'fixed-link' property */
1018 fl_node = fdt_subnode_offset(blob, pnode, "fixed-link");
1019 if (fl_node != -FDT_ERR_NOTFOUND) {
1020 /* set phy_addr to invalid value for fixed link */
1021 dmvgbe->phyaddr = PHY_MAX_ADDR + 1;
1022 dmvgbe->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1023 dmvgbe->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1025 /* Now read phyaddr from DT */
1026 addr = fdtdec_lookup_phandle(blob, pnode, "phy-handle");
1028 dmvgbe->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1034 static const struct udevice_id mvgbe_ids[] = {
1035 { .compatible = "marvell,kirkwood-eth" },
1039 U_BOOT_DRIVER(mvgbe) = {
1042 .of_match = mvgbe_ids,
1043 .of_to_plat = mvgbe_of_to_plat,
1044 .probe = mvgbe_probe,
1046 .priv_auto = sizeof(struct mvgbe_device),
1047 .plat_auto = sizeof(struct eth_pdata),
1049 #endif /* CONFIG_DM_ETH */