1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 * Ingo Assmus <ingo.assmus@keymile.com>
10 * based on - Driver for MV64360X ethernet ports
11 * Copyright (C) 2002 rabeeh@galileo.co.il
22 #include <linux/delay.h>
23 #include <linux/errno.h>
24 #include <asm/types.h>
25 #include <asm/system.h>
26 #include <asm/byteorder.h>
27 #include <asm/arch/cpu.h>
29 #if defined(CONFIG_ARCH_KIRKWOOD)
30 #include <asm/arch/soc.h>
31 #elif defined(CONFIG_ARCH_ORION5X)
32 #include <asm/arch/orion5x.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 #ifndef CONFIG_MVGBE_PORTS
40 # define CONFIG_MVGBE_PORTS {0, 0}
43 #define MV_PHY_ADR_REQUEST 0xee
44 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
46 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
47 static int smi_wait_ready(struct mvgbe_device *dmvgbe)
51 ret = wait_for_bit_le32(&MVGBE_SMI_REG, MVGBE_PHY_SMI_BUSY_MASK, false,
52 MVGBE_PHY_SMI_TIMEOUT_MS, false);
54 printf("Error: SMI busy timeout\n");
61 static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
62 int devad, int reg_ofs)
64 struct mvgbe_registers *regs = dmvgbe->regs;
69 /* Phyadr read request */
70 if (phy_adr == MV_PHY_ADR_REQUEST &&
71 reg_ofs == MV_PHY_ADR_REQUEST) {
73 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
76 /* check parameters */
77 if (phy_adr > PHYADR_MASK) {
78 printf("Err..(%s) Invalid PHY address %d\n",
82 if (reg_ofs > PHYREG_MASK) {
83 printf("Err..(%s) Invalid register offset %d\n",
88 /* wait till the SMI is not busy */
89 if (smi_wait_ready(dmvgbe) < 0)
92 /* fill the phy address and regiser offset and read opcode */
93 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
94 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
95 | MVGBE_PHY_SMI_OPCODE_READ;
97 /* write the smi register */
98 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
100 /*wait till read value is ready */
101 timeout = MVGBE_PHY_SMI_TIMEOUT;
104 /* read smi register */
105 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
106 if (timeout-- == 0) {
107 printf("Err..(%s) SMI read ready timeout\n",
111 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
113 /* Wait for the data to update in the SMI register */
114 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
117 data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
119 debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs,
126 * smi_reg_read - miiphy_read callback function.
128 * Returns 16bit phy register value, or -EFAULT on error
130 static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
134 struct mvgbe_device *dmvgbe = bus->priv;
136 struct eth_device *dev = eth_get_dev_by_name(bus->name);
137 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
140 return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
143 static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
144 int devad, int reg_ofs, u16 data)
146 struct mvgbe_registers *regs = dmvgbe->regs;
149 /* Phyadr write request*/
150 if (phy_adr == MV_PHY_ADR_REQUEST &&
151 reg_ofs == MV_PHY_ADR_REQUEST) {
152 MVGBE_REG_WR(regs->phyadr, data);
156 /* check parameters */
157 if (phy_adr > PHYADR_MASK) {
158 printf("Err..(%s) Invalid phy address\n", __func__);
161 if (reg_ofs > PHYREG_MASK) {
162 printf("Err..(%s) Invalid register offset\n", __func__);
166 /* wait till the SMI is not busy */
167 if (smi_wait_ready(dmvgbe) < 0)
170 /* fill the phy addr and reg offset and write opcode and data */
171 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
172 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
173 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
174 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
176 /* write the smi register */
177 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
183 * smi_reg_write - miiphy_write callback function.
185 * Returns 0 if write succeed, -EFAULT on error
187 static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
188 int reg_ofs, u16 data)
191 struct mvgbe_device *dmvgbe = bus->priv;
193 struct eth_device *dev = eth_get_dev_by_name(bus->name);
194 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
197 return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
201 /* Stop and checks all queues */
202 static void stop_queue(u32 * qreg)
206 reg_data = readl(qreg);
208 if (reg_data & 0xFF) {
209 /* Issue stop command for active channels only */
210 writel((reg_data << 8), qreg);
212 /* Wait for all queue activity to terminate. */
215 * Check port cause register that all queues
218 reg_data = readl(qreg);
220 while (reg_data & 0xFF);
225 * set_access_control - Config address decode parameters for Ethernet unit
227 * This function configures the address decode parameters for the Gigabit
228 * Ethernet Controller according the given parameters struct.
230 * @regs Register struct pointer.
231 * @param Address decode parameter struct.
233 static void set_access_control(struct mvgbe_registers *regs,
234 struct mvgbe_winparam *param)
238 /* Set access control register */
239 access_prot_reg = MVGBE_REG_RD(regs->epap);
240 /* clear window permission */
241 access_prot_reg &= (~(3 << (param->win * 2)));
242 access_prot_reg |= (param->access_ctrl << (param->win * 2));
243 MVGBE_REG_WR(regs->epap, access_prot_reg);
245 /* Set window Size reg (SR) */
246 MVGBE_REG_WR(regs->barsz[param->win].size,
247 (((param->size / 0x10000) - 1) << 16));
249 /* Set window Base address reg (BA) */
250 MVGBE_REG_WR(regs->barsz[param->win].bar,
251 (param->target | param->attrib | param->base_addr));
252 /* High address remap reg (HARR) */
254 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
256 /* Base address enable reg (BARER) */
257 if (param->enable == 1)
258 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
260 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
263 static void set_dram_access(struct mvgbe_registers *regs)
265 struct mvgbe_winparam win_param;
268 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
269 /* Set access parameters for DRAM bank i */
270 win_param.win = i; /* Use Ethernet window i */
271 /* Window target - DDR */
272 win_param.target = MVGBE_TARGET_DRAM;
273 /* Enable full access */
274 win_param.access_ctrl = EWIN_ACCESS_FULL;
275 win_param.high_addr = 0;
276 /* Get bank base and size */
277 win_param.base_addr = gd->bd->bi_dram[i].start;
278 win_param.size = gd->bd->bi_dram[i].size;
279 if (win_param.size == 0)
280 win_param.enable = 0;
282 win_param.enable = 1; /* Enable the access */
284 /* Enable DRAM bank */
287 win_param.attrib = EBAR_DRAM_CS0;
290 win_param.attrib = EBAR_DRAM_CS1;
293 win_param.attrib = EBAR_DRAM_CS2;
296 win_param.attrib = EBAR_DRAM_CS3;
299 /* invalid bank, disable access */
300 win_param.enable = 0;
301 win_param.attrib = 0;
304 /* Set the access control for address window(EPAPR) RD/WR */
305 set_access_control(regs, &win_param);
310 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
312 * Go through all the DA filter tables (Unicast, Special Multicast & Other
313 * Multicast) and set each entry to 0.
315 static void port_init_mac_tables(struct mvgbe_registers *regs)
319 /* Clear DA filter unicast table (Ex_dFUT) */
320 for (table_index = 0; table_index < 4; ++table_index)
321 MVGBE_REG_WR(regs->dfut[table_index], 0);
323 for (table_index = 0; table_index < 64; ++table_index) {
324 /* Clear DA filter special multicast table (Ex_dFSMT) */
325 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
326 /* Clear DA filter other multicast table (Ex_dFOMT) */
327 MVGBE_REG_WR(regs->dfomt[table_index], 0);
332 * port_uc_addr - This function Set the port unicast address table
334 * This function locates the proper entry in the Unicast table for the
335 * specified MAC nibble and sets its properties according to function
337 * This function add/removes MAC addresses from the port unicast address
340 * @uc_nibble Unicast MAC Address last nibble.
341 * @option 0 = Add, 1 = remove address.
343 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
345 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
352 /* Locate the Unicast table entry */
353 uc_nibble = (0xf & uc_nibble);
354 /* Register offset from unicast table base */
355 tbl_offset = (uc_nibble / 4);
356 /* Entry offset within the above register */
357 reg_offset = uc_nibble % 4;
360 case REJECT_MAC_ADDR:
362 * Clear accepts frame bit at specified unicast
365 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
366 unicast_reg &= (0xFF << (8 * reg_offset));
367 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
369 case ACCEPT_MAC_ADDR:
370 /* Set accepts frame bit at unicast DA filter table entry */
371 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
372 unicast_reg &= (0xFF << (8 * reg_offset));
373 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
374 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
383 * port_uc_addr_set - This function Set the port Unicast address.
385 static void port_uc_addr_set(struct mvgbe_device *dmvgbe, u8 *p_addr)
387 struct mvgbe_registers *regs = dmvgbe->regs;
391 mac_l = (p_addr[4] << 8) | (p_addr[5]);
392 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
395 MVGBE_REG_WR(regs->macal, mac_l);
396 MVGBE_REG_WR(regs->macah, mac_h);
398 /* Accept frames of this address */
399 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
403 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
405 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
407 struct mvgbe_rxdesc *p_rx_desc;
410 /* initialize the Rx descriptors ring */
411 p_rx_desc = dmvgbe->p_rxdesc;
412 for (i = 0; i < RINGSZ; i++) {
414 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
415 p_rx_desc->buf_size = PKTSIZE_ALIGN;
416 p_rx_desc->byte_cnt = 0;
417 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
418 if (i == (RINGSZ - 1))
419 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
421 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
422 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
423 p_rx_desc = p_rx_desc->nxtdesc_p;
426 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
429 static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
432 struct mvgbe_registers *regs = dmvgbe->regs;
433 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
434 !defined(CONFIG_PHYLIB) && \
435 !defined(CONFIG_DM_ETH) && \
436 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
440 mvgbe_init_rx_desc_ring(dmvgbe);
442 /* Clear the ethernet port interrupts */
443 MVGBE_REG_WR(regs->ic, 0);
444 MVGBE_REG_WR(regs->ice, 0);
445 /* Unmask RX buffer and TX end interrupt */
446 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
447 /* Unmask phy and link status changes interrupts */
448 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
450 set_dram_access(regs);
451 port_init_mac_tables(regs);
452 port_uc_addr_set(dmvgbe, enetaddr);
454 /* Assign port configuration and command. */
455 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
456 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
457 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
459 /* Assign port SDMA configuration */
460 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
461 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
462 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
463 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
464 /* Turn off the port/RXUQ bandwidth limitation */
465 MVGBE_REG_WR(regs->pmtu, 0);
467 /* Set maximum receive buffer to 9700 bytes */
468 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
469 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
471 /* Enable port initially */
472 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
475 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
476 * disable the leaky bucket mechanism .
478 MVGBE_REG_WR(regs->pmtu, 0);
480 /* Assignment of Rx CRDB of given RXUQ */
481 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
482 /* ensure previous write is done before enabling Rx DMA */
484 /* Enable port Rx. */
485 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
487 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
488 !defined(CONFIG_PHYLIB) && \
489 !defined(CONFIG_DM_ETH) && \
490 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
491 /* Wait up to 5s for the link status */
492 for (i = 0; i < 5; i++) {
495 miiphy_read(name, MV_PHY_ADR_REQUEST,
496 MV_PHY_ADR_REQUEST, &phyadr);
497 /* Return if we get link up */
498 if (miiphy_link(name, phyadr))
503 printf("No link on %s\n", name);
509 #ifndef CONFIG_DM_ETH
510 static int mvgbe_init(struct eth_device *dev)
512 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
514 return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name);
518 static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
520 struct mvgbe_registers *regs = dmvgbe->regs;
522 /* Disable all gigE address decoder */
523 MVGBE_REG_WR(regs->bare, 0x3f);
525 stop_queue(®s->tqc);
526 stop_queue(®s->rqc);
529 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
530 /* Set port is not reset */
531 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
532 #ifdef CONFIG_SYS_MII_MODE
533 /* Set MMI interface up */
534 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
536 /* Disable & mask ethernet port interrupts */
537 MVGBE_REG_WR(regs->ic, 0);
538 MVGBE_REG_WR(regs->ice, 0);
539 MVGBE_REG_WR(regs->pim, 0);
540 MVGBE_REG_WR(regs->peim, 0);
543 #ifndef CONFIG_DM_ETH
544 static int mvgbe_halt(struct eth_device *dev)
546 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
548 __mvgbe_halt(dmvgbe);
555 static int mvgbe_write_hwaddr(struct udevice *dev)
557 struct eth_pdata *pdata = dev_get_platdata(dev);
559 port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr);
564 static int mvgbe_write_hwaddr(struct eth_device *dev)
566 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
568 /* Programs net device MAC address after initialization */
569 port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr);
574 static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
577 struct mvgbe_registers *regs = dmvgbe->regs;
578 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
579 void *p = (void *)dataptr;
583 /* Copy buffer if it's misaligned */
584 if ((u32) dataptr & 0x07) {
585 if (datasize > PKTSIZE_ALIGN) {
586 printf("Non-aligned data too large (%d)\n",
591 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
592 p = dmvgbe->p_aligned_txbuf;
595 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
596 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
597 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
598 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
599 p_txdesc->buf_ptr = (u8 *) p;
600 p_txdesc->byte_cnt = datasize;
602 /* Set this tc desc as zeroth TXUQ */
603 txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
604 writel((u32) p_txdesc, txuq0_reg_addr);
606 /* ensure tx desc writes above are performed before we start Tx DMA */
609 /* Apply send command using zeroth TXUQ */
610 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
613 * wait for packet xmit completion
615 cmd_sts = readl(&p_txdesc->cmd_sts);
616 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
617 /* return fail if error is detected */
618 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
619 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
620 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
621 printf("Err..(%s) in xmit packet\n", __func__);
624 cmd_sts = readl(&p_txdesc->cmd_sts);
629 #ifndef CONFIG_DM_ETH
630 static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
632 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
634 return __mvgbe_send(dmvgbe, dataptr, datasize);
638 static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
640 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
643 u32 rxdesc_curr_addr;
649 /* wait untill rx packet available or timeout */
651 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
654 debug("%s time out...\n", __func__);
657 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
659 if (p_rxdesc_curr->byte_cnt != 0) {
660 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
661 __func__, (u32) p_rxdesc_curr->byte_cnt,
662 (u32) p_rxdesc_curr->buf_ptr,
663 (u32) p_rxdesc_curr->cmd_sts);
667 * In case received a packet without first/last bits on
668 * OR the error summary bit is on,
669 * the packets needs to be dropeed.
671 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
674 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
675 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
677 printf("Err..(%s) Dropping packet spread on"
678 " multiple descriptors\n", __func__);
680 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
682 printf("Err..(%s) Dropping packet with errors\n",
686 /* !!! call higher layer processing */
687 debug("%s: Sending Received packet to"
688 " upper layer (net_process_received_packet)\n",
691 data = (p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET);
692 rx_bytes = (int)(p_rxdesc_curr->byte_cnt -
698 * free these descriptors and point next in the ring
700 p_rxdesc_curr->cmd_sts =
701 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
702 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
703 p_rxdesc_curr->byte_cnt = 0;
705 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
706 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
711 #ifndef CONFIG_DM_ETH
712 static int mvgbe_recv(struct eth_device *dev)
714 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
718 ret = __mvgbe_recv(dmvgbe, &packet);
722 net_process_received_packet(packet, ret);
728 #if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
729 #if defined(CONFIG_DM_ETH)
730 static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
732 phy_interface_t phy_interface,
735 static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
737 phy_interface_t phy_interface,
741 struct phy_device *phydev;
743 /* Set phy address of the port */
744 miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST,
747 phydev = phy_connect(bus, phyid, dev, phy_interface);
749 printf("phy_connect failed\n");
758 #endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */
760 #if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH)
761 int mvgbe_phylib_init(struct eth_device *dev, int phyid)
764 struct phy_device *phydev;
769 printf("mdio_alloc failed\n");
772 bus->read = smi_reg_read;
773 bus->write = smi_reg_write;
774 strcpy(bus->name, dev->name);
776 ret = mdio_register(bus);
778 printf("mdio_register failed\n");
783 phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid);
791 static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
793 dmvgbe->p_rxdesc = memalign(PKTALIGN,
794 MV_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
795 if (!dmvgbe->p_rxdesc)
798 dmvgbe->p_rxbuf = memalign(PKTALIGN,
799 RINGSZ * PKTSIZE_ALIGN + 1);
800 if (!dmvgbe->p_rxbuf)
803 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
804 if (!dmvgbe->p_aligned_txbuf)
807 dmvgbe->p_txdesc = memalign(PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
808 if (!dmvgbe->p_txdesc)
814 free(dmvgbe->p_aligned_txbuf);
816 free(dmvgbe->p_rxbuf);
818 free(dmvgbe->p_rxdesc);
823 #ifndef CONFIG_DM_ETH
824 int mvgbe_initialize(struct bd_info *bis)
826 struct mvgbe_device *dmvgbe;
827 struct eth_device *dev;
830 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
832 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
833 /*skip if port is configured not to use */
834 if (used_ports[devnum] == 0)
837 dmvgbe = malloc(sizeof(struct mvgbe_device));
841 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
842 ret = mvgbe_alloc_buffers(dmvgbe);
844 printf("Err.. %s Failed to allocate memory\n",
852 /* must be less than sizeof(dev->name) */
853 sprintf(dev->name, "egiga%d", devnum);
857 dmvgbe->regs = (void *)MVGBE0_BASE;
859 #if defined(MVGBE1_BASE)
861 dmvgbe->regs = (void *)MVGBE1_BASE;
864 default: /* this should never happen */
865 printf("Err..(%s) Invalid device number %d\n",
870 dev->init = (void *)mvgbe_init;
871 dev->halt = (void *)mvgbe_halt;
872 dev->send = (void *)mvgbe_send;
873 dev->recv = (void *)mvgbe_recv;
874 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
878 #if defined(CONFIG_PHYLIB)
879 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
880 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
882 struct mii_dev *mdiodev = mdio_alloc();
885 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
886 mdiodev->read = smi_reg_read;
887 mdiodev->write = smi_reg_write;
889 retval = mdio_register(mdiodev);
892 /* Set phy address of the port */
893 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
894 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
902 static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
904 return dmvgbe->phyaddr > PHY_MAX_ADDR;
907 static int mvgbe_start(struct udevice *dev)
909 struct eth_pdata *pdata = dev_get_platdata(dev);
910 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
913 ret = __mvgbe_init(dmvgbe, pdata->enetaddr, dev->name);
917 if (!mvgbe_port_is_fixed_link(dmvgbe)) {
918 dmvgbe->phydev = __mvgbe_phy_init(dev, dmvgbe->bus,
919 dmvgbe->phy_interface,
928 static int mvgbe_send(struct udevice *dev, void *packet, int length)
930 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
932 return __mvgbe_send(dmvgbe, packet, length);
935 static int mvgbe_recv(struct udevice *dev, int flags, uchar **packetp)
937 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
939 return __mvgbe_recv(dmvgbe, packetp);
942 static void mvgbe_stop(struct udevice *dev)
944 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
946 __mvgbe_halt(dmvgbe);
949 static int mvgbe_probe(struct udevice *dev)
951 struct eth_pdata *pdata = dev_get_platdata(dev);
952 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
956 ret = mvgbe_alloc_buffers(dmvgbe);
960 dmvgbe->regs = (void __iomem *)pdata->iobase;
964 printf("Failed to allocate MDIO bus\n");
968 bus->read = smi_reg_read;
969 bus->write = smi_reg_write;
970 snprintf(bus->name, sizeof(bus->name), dev->name);
974 ret = mdio_register(bus);
981 static const struct eth_ops mvgbe_ops = {
982 .start = mvgbe_start,
986 .write_hwaddr = mvgbe_write_hwaddr,
989 static int mvgbe_ofdata_to_platdata(struct udevice *dev)
991 struct eth_pdata *pdata = dev_get_platdata(dev);
992 struct mvgbe_device *dmvgbe = dev_get_priv(dev);
993 void *blob = (void *)gd->fdt_blob;
994 int node = dev_of_offset(dev);
995 const char *phy_mode;
1000 pdata->iobase = devfdt_get_addr(dev);
1001 pdata->phy_interface = -1;
1003 pnode = fdt_node_offset_by_compatible(blob, node,
1004 "marvell,kirkwood-eth-port");
1006 /* Get phy-mode / phy_interface from DT */
1007 phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL);
1009 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1011 pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
1013 dmvgbe->phy_interface = pdata->phy_interface;
1015 /* fetch 'fixed-link' property */
1016 fl_node = fdt_subnode_offset(blob, pnode, "fixed-link");
1017 if (fl_node != -FDT_ERR_NOTFOUND) {
1018 /* set phy_addr to invalid value for fixed link */
1019 dmvgbe->phyaddr = PHY_MAX_ADDR + 1;
1020 dmvgbe->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1021 dmvgbe->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1023 /* Now read phyaddr from DT */
1024 addr = fdtdec_lookup_phandle(blob, pnode, "phy-handle");
1026 dmvgbe->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1032 static const struct udevice_id mvgbe_ids[] = {
1033 { .compatible = "marvell,kirkwood-eth" },
1037 U_BOOT_DRIVER(mvgbe) = {
1040 .of_match = mvgbe_ids,
1041 .ofdata_to_platdata = mvgbe_ofdata_to_platdata,
1042 .probe = mvgbe_probe,
1044 .priv_auto_alloc_size = sizeof(struct mvgbe_device),
1045 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1047 #endif /* CONFIG_DM_ETH */