1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 * Author: Mark Lee <mark-mc.lee@mediatek.com>
12 /* Frame Engine Register Bases */
13 #define PDMA_BASE 0x0800
14 #define GDMA1_BASE 0x0500
15 #define GDMA2_BASE 0x1500
16 #define GMAC_BASE 0x10000
18 /* Ethernet subsystem registers */
20 #define ETHSYS_SYSCFG0_REG 0x14
21 #define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
22 #define SYSCFG0_GE_MODE_M 0x3
23 #define SYSCFG0_SGMII_SEL_M (0x3 << 8)
24 #define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
26 #define ETHSYS_CLKCFG0_REG 0x2c
27 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
29 /* SYSCFG0_GE_MODE: GE Modes */
30 #define GE_MODE_RGMII 0
32 #define GE_MODE_MII_PHY 2
33 #define GE_MODE_RMII 3
35 /* SGMII subsystem config registers */
36 #define SGMSYS_PCS_CONTROL_1 0x0
37 #define SGMII_LINK_STATUS BIT(18)
38 #define SGMII_AN_ENABLE BIT(12)
39 #define SGMII_AN_RESTART BIT(9)
41 #define SGMSYS_SGMII_MODE 0x20
42 #define SGMII_FORCE_MODE 0x31120019
44 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
45 #define SGMII_PHYA_PWD BIT(4)
47 #define SGMSYS_GEN2_SPEED 0x2028
48 #define SGMSYS_SPEED_2500 BIT(2)
50 /* Frame Engine Registers */
53 #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
54 #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
55 #define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
56 #define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
58 #define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
59 #define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
60 #define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
61 #define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
63 #define PDMA_GLO_CFG_REG 0x204
64 #define TX_WB_DDONE BIT(6)
65 #define RX_DMA_BUSY BIT(3)
66 #define RX_DMA_EN BIT(2)
67 #define TX_DMA_BUSY BIT(1)
68 #define TX_DMA_EN BIT(0)
70 #define PDMA_RST_IDX_REG 0x208
71 #define RST_DRX_IDX0 BIT(16)
72 #define RST_DTX_IDX0 BIT(0)
75 #define GDMA_IG_CTRL_REG 0x000
76 #define GDM_ICS_EN BIT(22)
77 #define GDM_TCS_EN BIT(21)
78 #define GDM_UCS_EN BIT(20)
79 #define STRP_CRC BIT(16)
81 #define MYMAC_DP_M 0xf000
89 #define GDMA_MAC_LSB_REG 0x008
91 #define GDMA_MAC_MSB_REG 0x00c
93 /* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
103 #define GMAC_PIAC_REG 0x0004
104 #define PHY_ACS_ST BIT(31)
105 #define MDIO_REG_ADDR_S 25
106 #define MDIO_REG_ADDR_M 0x3e000000
107 #define MDIO_PHY_ADDR_S 20
108 #define MDIO_PHY_ADDR_M 0x1f00000
109 #define MDIO_CMD_S 18
110 #define MDIO_CMD_M 0xc0000
112 #define MDIO_ST_M 0x30000
113 #define MDIO_RW_DATA_S 0
114 #define MDIO_RW_DATA_M 0xffff
116 /* MDIO_CMD: MDIO commands */
117 #define MDIO_CMD_ADDR 0
118 #define MDIO_CMD_WRITE 1
119 #define MDIO_CMD_READ 2
120 #define MDIO_CMD_READ_C45 3
122 /* MDIO_ST: MDIO start field */
123 #define MDIO_ST_C45 0
124 #define MDIO_ST_C22 1
126 #define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
127 #define MAC_RX_PKT_LEN_S 24
128 #define MAC_RX_PKT_LEN_M 0x3000000
130 #define IPG_CFG_M 0xc0000
131 #define MAC_MODE BIT(16)
132 #define FORCE_MODE BIT(15)
133 #define MAC_TX_EN BIT(14)
134 #define MAC_RX_EN BIT(13)
135 #define BKOFF_EN BIT(9)
136 #define BACKPR_EN BIT(8)
137 #define FORCE_RX_FC BIT(5)
138 #define FORCE_TX_FC BIT(4)
139 #define FORCE_SPD_S 2
140 #define FORCE_SPD_M 0x0c
141 #define FORCE_DPX BIT(1)
142 #define FORCE_LINK BIT(0)
144 /* Values of IPG_CFG */
146 #define IPG_96BIT_WITH_SHORT_IPG 1
149 /* MAC_RX_PKT_LEN: Max RX packet length */
150 #define MAC_RX_PKT_LEN_1518 0
151 #define MAC_RX_PKT_LEN_1536 1
152 #define MAC_RX_PKT_LEN_1552 2
153 #define MAC_RX_PKT_LEN_JUMBO 3
155 /* FORCE_SPD: Forced link speed */
158 #define SPEED_1000M 2
160 #define GMAC_TRGMII_RCK_CTRL 0x300
161 #define RX_RST BIT(31)
162 #define RXC_DQSISEL BIT(30)
164 #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
165 #define TD_DM_DRVN_S 4
166 #define TD_DM_DRVN_M 0xf0
167 #define TD_DM_DRVP_S 0
168 #define TD_DM_DRVP_M 0x0f
170 /* MT7530 Registers */
172 #define PCR_REG(p) (0x2004 + (p) * 0x100)
173 #define PORT_MATRIX_S 16
174 #define PORT_MATRIX_M 0xff0000
176 #define PVC_REG(p) (0x2010 + (p) * 0x100)
177 #define STAG_VPID_S 16
178 #define STAG_VPID_M 0xffff0000
179 #define VLAN_ATTR_S 6
180 #define VLAN_ATTR_M 0xc0
182 /* VLAN_ATTR: VLAN attributes */
183 #define VLAN_ATTR_USER 0
184 #define VLAN_ATTR_STACK 1
185 #define VLAN_ATTR_TRANSLATION 2
186 #define VLAN_ATTR_TRANSPARENT 3
188 #define PMCR_REG(p) (0x3000 + (p) * 0x100)
189 /* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
190 * MT7531 specific fields are defined below
192 #define FORCE_MODE_EEE1G BIT(25)
193 #define FORCE_MODE_EEE100 BIT(26)
194 #define FORCE_MODE_TX_FC BIT(27)
195 #define FORCE_MODE_RX_FC BIT(28)
196 #define FORCE_MODE_DPX BIT(29)
197 #define FORCE_MODE_SPD BIT(30)
198 #define FORCE_MODE_LNK BIT(31)
199 #define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\
200 FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
201 FORCE_MODE_DPX | FORCE_MODE_SPD | \
204 /* MT7531 SGMII Registers */
205 #define MT7531_SGMII_REG_BASE 0x5000
206 #define MT7531_SGMII_REG_PORT_BASE 0x1000
207 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
208 (p) * MT7531_SGMII_REG_PORT_BASE + (r))
209 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00)
210 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20)
211 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8)
212 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128)
213 /* XXX: all fields of MT7531 SGMII are defined under SGMSYS */
215 /* MT753x System Control Register */
216 #define SYS_CTRL_REG 0x7000
217 #define SW_PHY_RST BIT(2)
218 #define SW_SYS_RST BIT(1)
219 #define SW_REG_RST BIT(0)
222 #define MT7531_PHY_IAC 0x701c
223 /* XXX: all fields are defined under GMAC_PIAC_REG */
225 #define MT7531_CLKGEN_CTRL 0x7500
226 #define CLK_SKEW_OUT_S 8
227 #define CLK_SKEW_OUT_M 0x300
228 #define CLK_SKEW_IN_S 6
229 #define CLK_SKEW_IN_M 0xc0
230 #define RXCLK_NO_DELAY BIT(5)
231 #define TXCLK_NO_REVERSE BIT(4)
233 #define GP_MODE_M 0x06
234 #define GP_CLK_EN BIT(0)
236 /* Values of GP_MODE */
237 #define GP_MODE_RGMII 0
238 #define GP_MODE_MII 1
239 #define GP_MODE_REV_MII 2
241 /* Values of CLK_SKEW_IN */
242 #define CLK_SKEW_IN_NO_CHANGE 0
243 #define CLK_SKEW_IN_DELAY_100PPS 1
244 #define CLK_SKEW_IN_DELAY_200PPS 2
245 #define CLK_SKEW_IN_REVERSE 3
247 /* Values of CLK_SKEW_OUT */
248 #define CLK_SKEW_OUT_NO_CHANGE 0
249 #define CLK_SKEW_OUT_DELAY_100PPS 1
250 #define CLK_SKEW_OUT_DELAY_200PPS 2
251 #define CLK_SKEW_OUT_REVERSE 3
253 #define HWTRAP_REG 0x7800
254 /* MT7530 Modified Hardware Trap Status Registers */
255 #define MHWTRAP_REG 0x7804
256 #define CHG_TRAP BIT(16)
257 #define LOOPDET_DIS BIT(14)
258 #define P5_INTF_SEL_S 13
259 #define P5_INTF_SEL_M 0x2000
260 #define SMI_ADDR_S 11
261 #define SMI_ADDR_M 0x1800
262 #define XTAL_FSEL_S 9
263 #define XTAL_FSEL_M 0x600
264 #define P6_INTF_DIS BIT(8)
265 #define P5_INTF_MODE_S 7
266 #define P5_INTF_MODE_M 0x80
267 #define P5_INTF_DIS BIT(6)
268 #define C_MDIO_BPS BIT(5)
269 #define CHIP_MODE_S 0
270 #define CHIP_MODE_M 0x0f
272 /* P5_INTF_SEL: Interface type of Port5 */
273 #define P5_INTF_SEL_GPHY 0
274 #define P5_INTF_SEL_GMAC5 1
276 /* P5_INTF_MODE: Interface mode of Port5 */
277 #define P5_INTF_MODE_GMII_MII 0
278 #define P5_INTF_MODE_RGMII 1
280 #define MT7530_P6ECR 0x7830
281 #define P6_INTF_MODE_M 0x3
282 #define P6_INTF_MODE_S 0
284 /* P6_INTF_MODE: Interface mode of Port6 */
285 #define P6_INTF_MODE_RGMII 0
286 #define P6_INTF_MODE_TRGMII 1
288 #define NUM_TRGMII_CTRL 5
290 #define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
292 #define RD_TAP_M 0x7f
294 #define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
295 /* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
297 /* TOP Signals Status Register */
298 #define MT7531_TOP_SIG_SR 0x780c
299 #define PAD_MCM_SMI_EN BIT(0)
300 #define PAD_DUAL_SGMII_EN BIT(1)
302 /* MT7531 PLLGP Registers */
303 #define MT7531_PLLGP_EN 0x7820
304 #define EN_COREPLL BIT(2)
305 #define SW_CLKSW BIT(1)
306 #define SW_PLLGP BIT(0)
308 #define MT7531_PLLGP_CR0 0x78a8
309 #define RG_COREPLL_EN BIT(22)
310 #define RG_COREPLL_POSDIV_S 23
311 #define RG_COREPLL_POSDIV_M 0x3800000
312 #define RG_COREPLL_SDM_PCW_S 1
313 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
314 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
316 /* MT7531 RGMII and SGMII PLL clock */
317 #define MT7531_ANA_PLLGP_CR2 0x78b0
318 #define MT7531_ANA_PLLGP_CR5 0x78bc
320 /* MT7531 GPIO GROUP IOLB SMT0 Control */
321 #define MT7531_SMT0_IOLB 0x7f04
322 #define SMT_IOLB_5_SMI_MDC_EN BIT(5)
324 /* MT7530 GPHY MDIO Indirect Access Registers */
325 #define MII_MMD_ACC_CTL_REG 0x0d
327 #define MMD_CMD_M 0xc000
328 #define MMD_DEVAD_S 0
329 #define MMD_DEVAD_M 0x1f
331 /* MMD_CMD: MMD commands */
334 #define MMD_DATA_RW_POST_INC 2
335 #define MMD_DATA_W_POST_INC 3
337 #define MII_MMD_ADDR_DATA_REG 0x0e
339 /* MT7530 GPHY MDIO MMD Registers */
340 #define CORE_PLL_GROUP2 0x401
341 #define RG_SYSPLL_EN_NORMAL BIT(15)
342 #define RG_SYSPLL_VODEN BIT(14)
343 #define RG_SYSPLL_POSDIV_S 5
344 #define RG_SYSPLL_POSDIV_M 0x60
346 #define CORE_PLL_GROUP4 0x403
347 #define MT7531_BYPASS_MODE BIT(4)
348 #define MT7531_POWER_ON_OFF BIT(5)
349 #define RG_SYSPLL_DDSFBK_EN BIT(12)
350 #define RG_SYSPLL_BIAS_EN BIT(11)
351 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
353 #define CORE_PLL_GROUP5 0x404
354 #define RG_LCDDS_PCW_NCPO1_S 0
355 #define RG_LCDDS_PCW_NCPO1_M 0xffff
357 #define CORE_PLL_GROUP6 0x405
358 #define RG_LCDDS_PCW_NCPO0_S 0
359 #define RG_LCDDS_PCW_NCPO0_M 0xffff
361 #define CORE_PLL_GROUP7 0x406
362 #define RG_LCDDS_PWDB BIT(15)
363 #define RG_LCDDS_ISO_EN BIT(13)
364 #define RG_LCCDS_C_S 4
365 #define RG_LCCDS_C_M 0x70
366 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
368 #define CORE_PLL_GROUP10 0x409
369 #define RG_LCDDS_SSC_DELTA_S 0
370 #define RG_LCDDS_SSC_DELTA_M 0xfff
372 #define CORE_PLL_GROUP11 0x40a
373 #define RG_LCDDS_SSC_DELTA1_S 0
374 #define RG_LCDDS_SSC_DELTA1_M 0xfff
376 #define CORE_GSWPLL_GRP1 0x40d
377 #define RG_GSWPLL_POSDIV_200M_S 12
378 #define RG_GSWPLL_POSDIV_200M_M 0x3000
379 #define RG_GSWPLL_EN_PRE BIT(11)
380 #define RG_GSWPLL_FBKDIV_200M_S 0
381 #define RG_GSWPLL_FBKDIV_200M_M 0xff
383 #define CORE_GSWPLL_GRP2 0x40e
384 #define RG_GSWPLL_POSDIV_500M_S 8
385 #define RG_GSWPLL_POSDIV_500M_M 0x300
386 #define RG_GSWPLL_FBKDIV_500M_S 0
387 #define RG_GSWPLL_FBKDIV_500M_M 0xff
389 #define CORE_TRGMII_GSW_CLK_CG 0x410
390 #define REG_GSWCK_EN BIT(0)
391 #define REG_TRGMIICK_EN BIT(1)
393 /* Extend PHY Control Register 3 */
394 #define PHY_EXT_REG_14 0x14
396 /* Fields of PHY_EXT_REG_14 */
397 #define PHY_EN_DOWN_SHFIT BIT(4)
399 /* Extend PHY Control Register 4 */
400 #define PHY_EXT_REG_17 0x17
402 /* Fields of PHY_EXT_REG_17 */
403 #define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
405 /* PHY RXADC Control Register 7 */
406 #define PHY_DEV1E_REG_0C6 0x0c6
408 /* Fields of PHY_DEV1E_REG_0C6 */
409 #define PHY_POWER_SAVING_S 8
410 #define PHY_POWER_SAVING_M 0x300
411 #define PHY_POWER_SAVING_TX 0x0
413 #endif /* _MTK_ETH_H_ */