1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 * Author: Mark Lee <mark-mc.lee@mediatek.com>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
15 enum mkt_eth_capabilities {
17 MTK_TRGMII_MT7621_CLK_BIT,
21 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
24 #define MTK_TRGMII BIT(MTK_TRGMII_BIT)
25 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
26 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
28 /* Supported path present on SoCs */
29 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
31 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
33 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
35 #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
37 #define MT7623_CAPS (MTK_GMAC1_TRGMII)
39 #define MT7986_CAPS (MTK_NETSYS_V2)
41 /* Frame Engine Register Bases */
42 #define PDMA_V1_BASE 0x0800
43 #define PDMA_V2_BASE 0x6000
44 #define GDMA1_BASE 0x0500
45 #define GDMA2_BASE 0x1500
46 #define GMAC_BASE 0x10000
48 /* Ethernet subsystem registers */
50 #define ETHSYS_SYSCFG0_REG 0x14
51 #define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
52 #define SYSCFG0_GE_MODE_M 0x3
53 #define SYSCFG0_SGMII_SEL_M (0x3 << 8)
54 #define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
56 #define ETHSYS_CLKCFG0_REG 0x2c
57 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
59 /* SYSCFG0_GE_MODE: GE Modes */
60 #define GE_MODE_RGMII 0
62 #define GE_MODE_MII_PHY 2
63 #define GE_MODE_RMII 3
65 /* SGMII subsystem config registers */
66 #define SGMSYS_PCS_CONTROL_1 0x0
67 #define SGMII_LINK_STATUS BIT(18)
68 #define SGMII_AN_ENABLE BIT(12)
69 #define SGMII_AN_RESTART BIT(9)
71 #define SGMSYS_SGMII_MODE 0x20
72 #define SGMII_FORCE_MODE 0x31120019
74 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
75 #define SGMII_PHYA_PWD BIT(4)
77 #define SGMSYS_QPHY_WRAP_CTRL 0xec
78 #define SGMII_PN_SWAP_TX_RX 0x03
80 #define SGMSYS_GEN2_SPEED 0x2028
81 #define SGMSYS_GEN2_SPEED_V2 0x128
82 #define SGMSYS_SPEED_2500 BIT(2)
84 /* Frame Engine Registers */
85 #define FE_GLO_MISC_REG 0x124
86 #define PDMA_VER_V2 BIT(4)
89 #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
90 #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
91 #define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
92 #define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
94 #define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
95 #define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
96 #define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
97 #define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
99 #define PDMA_GLO_CFG_REG 0x204
100 #define TX_WB_DDONE BIT(6)
101 #define RX_DMA_BUSY BIT(3)
102 #define RX_DMA_EN BIT(2)
103 #define TX_DMA_BUSY BIT(1)
104 #define TX_DMA_EN BIT(0)
106 #define PDMA_RST_IDX_REG 0x208
107 #define RST_DRX_IDX0 BIT(16)
108 #define RST_DTX_IDX0 BIT(0)
111 #define GDMA_IG_CTRL_REG 0x000
112 #define GDM_ICS_EN BIT(22)
113 #define GDM_TCS_EN BIT(21)
114 #define GDM_UCS_EN BIT(20)
115 #define STRP_CRC BIT(16)
116 #define MYMAC_DP_S 12
117 #define MYMAC_DP_M 0xf000
119 #define BC_DP_M 0xf00
125 #define GDMA_MAC_LSB_REG 0x008
127 #define GDMA_MAC_MSB_REG 0x00c
129 /* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
139 #define GMAC_PIAC_REG 0x0004
140 #define PHY_ACS_ST BIT(31)
141 #define MDIO_REG_ADDR_S 25
142 #define MDIO_REG_ADDR_M 0x3e000000
143 #define MDIO_PHY_ADDR_S 20
144 #define MDIO_PHY_ADDR_M 0x1f00000
145 #define MDIO_CMD_S 18
146 #define MDIO_CMD_M 0xc0000
148 #define MDIO_ST_M 0x30000
149 #define MDIO_RW_DATA_S 0
150 #define MDIO_RW_DATA_M 0xffff
152 /* MDIO_CMD: MDIO commands */
153 #define MDIO_CMD_ADDR 0
154 #define MDIO_CMD_WRITE 1
155 #define MDIO_CMD_READ 2
156 #define MDIO_CMD_READ_C45 3
158 /* MDIO_ST: MDIO start field */
159 #define MDIO_ST_C45 0
160 #define MDIO_ST_C22 1
162 #define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
163 #define MAC_RX_PKT_LEN_S 24
164 #define MAC_RX_PKT_LEN_M 0x3000000
166 #define IPG_CFG_M 0xc0000
167 #define MAC_MODE BIT(16)
168 #define FORCE_MODE BIT(15)
169 #define MAC_TX_EN BIT(14)
170 #define MAC_RX_EN BIT(13)
171 #define BKOFF_EN BIT(9)
172 #define BACKPR_EN BIT(8)
173 #define FORCE_RX_FC BIT(5)
174 #define FORCE_TX_FC BIT(4)
175 #define FORCE_SPD_S 2
176 #define FORCE_SPD_M 0x0c
177 #define FORCE_DPX BIT(1)
178 #define FORCE_LINK BIT(0)
180 /* Values of IPG_CFG */
182 #define IPG_96BIT_WITH_SHORT_IPG 1
185 /* MAC_RX_PKT_LEN: Max RX packet length */
186 #define MAC_RX_PKT_LEN_1518 0
187 #define MAC_RX_PKT_LEN_1536 1
188 #define MAC_RX_PKT_LEN_1552 2
189 #define MAC_RX_PKT_LEN_JUMBO 3
191 /* FORCE_SPD: Forced link speed */
194 #define SPEED_1000M 2
196 #define GMAC_TRGMII_RCK_CTRL 0x300
197 #define RX_RST BIT(31)
198 #define RXC_DQSISEL BIT(30)
200 #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
201 #define TD_DM_DRVN_S 4
202 #define TD_DM_DRVN_M 0xf0
203 #define TD_DM_DRVP_S 0
204 #define TD_DM_DRVP_M 0x0f
206 /* MT7530 Registers */
208 #define PCR_REG(p) (0x2004 + (p) * 0x100)
209 #define PORT_MATRIX_S 16
210 #define PORT_MATRIX_M 0xff0000
212 #define PVC_REG(p) (0x2010 + (p) * 0x100)
213 #define STAG_VPID_S 16
214 #define STAG_VPID_M 0xffff0000
215 #define VLAN_ATTR_S 6
216 #define VLAN_ATTR_M 0xc0
218 /* VLAN_ATTR: VLAN attributes */
219 #define VLAN_ATTR_USER 0
220 #define VLAN_ATTR_STACK 1
221 #define VLAN_ATTR_TRANSLATION 2
222 #define VLAN_ATTR_TRANSPARENT 3
224 #define PMCR_REG(p) (0x3000 + (p) * 0x100)
225 /* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
226 * MT7531 specific fields are defined below
228 #define FORCE_MODE_EEE1G BIT(25)
229 #define FORCE_MODE_EEE100 BIT(26)
230 #define FORCE_MODE_TX_FC BIT(27)
231 #define FORCE_MODE_RX_FC BIT(28)
232 #define FORCE_MODE_DPX BIT(29)
233 #define FORCE_MODE_SPD BIT(30)
234 #define FORCE_MODE_LNK BIT(31)
235 #define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\
236 FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
237 FORCE_MODE_DPX | FORCE_MODE_SPD | \
240 /* MT7531 SGMII Registers */
241 #define MT7531_SGMII_REG_BASE 0x5000
242 #define MT7531_SGMII_REG_PORT_BASE 0x1000
243 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
244 (p) * MT7531_SGMII_REG_PORT_BASE + (r))
245 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00)
246 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20)
247 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8)
248 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128)
249 /* XXX: all fields of MT7531 SGMII are defined under SGMSYS */
251 /* MT753x System Control Register */
252 #define SYS_CTRL_REG 0x7000
253 #define SW_PHY_RST BIT(2)
254 #define SW_SYS_RST BIT(1)
255 #define SW_REG_RST BIT(0)
258 #define MT7531_PHY_IAC 0x701c
259 /* XXX: all fields are defined under GMAC_PIAC_REG */
261 #define MT7531_CLKGEN_CTRL 0x7500
262 #define CLK_SKEW_OUT_S 8
263 #define CLK_SKEW_OUT_M 0x300
264 #define CLK_SKEW_IN_S 6
265 #define CLK_SKEW_IN_M 0xc0
266 #define RXCLK_NO_DELAY BIT(5)
267 #define TXCLK_NO_REVERSE BIT(4)
269 #define GP_MODE_M 0x06
270 #define GP_CLK_EN BIT(0)
272 /* Values of GP_MODE */
273 #define GP_MODE_RGMII 0
274 #define GP_MODE_MII 1
275 #define GP_MODE_REV_MII 2
277 /* Values of CLK_SKEW_IN */
278 #define CLK_SKEW_IN_NO_CHANGE 0
279 #define CLK_SKEW_IN_DELAY_100PPS 1
280 #define CLK_SKEW_IN_DELAY_200PPS 2
281 #define CLK_SKEW_IN_REVERSE 3
283 /* Values of CLK_SKEW_OUT */
284 #define CLK_SKEW_OUT_NO_CHANGE 0
285 #define CLK_SKEW_OUT_DELAY_100PPS 1
286 #define CLK_SKEW_OUT_DELAY_200PPS 2
287 #define CLK_SKEW_OUT_REVERSE 3
289 #define HWTRAP_REG 0x7800
290 /* MT7530 Modified Hardware Trap Status Registers */
291 #define MHWTRAP_REG 0x7804
292 #define CHG_TRAP BIT(16)
293 #define LOOPDET_DIS BIT(14)
294 #define P5_INTF_SEL_S 13
295 #define P5_INTF_SEL_M 0x2000
296 #define SMI_ADDR_S 11
297 #define SMI_ADDR_M 0x1800
298 #define XTAL_FSEL_S 9
299 #define XTAL_FSEL_M 0x600
300 #define P6_INTF_DIS BIT(8)
301 #define P5_INTF_MODE_S 7
302 #define P5_INTF_MODE_M 0x80
303 #define P5_INTF_DIS BIT(6)
304 #define C_MDIO_BPS BIT(5)
305 #define CHIP_MODE_S 0
306 #define CHIP_MODE_M 0x0f
308 /* P5_INTF_SEL: Interface type of Port5 */
309 #define P5_INTF_SEL_GPHY 0
310 #define P5_INTF_SEL_GMAC5 1
312 /* P5_INTF_MODE: Interface mode of Port5 */
313 #define P5_INTF_MODE_GMII_MII 0
314 #define P5_INTF_MODE_RGMII 1
316 #define MT7530_P6ECR 0x7830
317 #define P6_INTF_MODE_M 0x3
318 #define P6_INTF_MODE_S 0
320 /* P6_INTF_MODE: Interface mode of Port6 */
321 #define P6_INTF_MODE_RGMII 0
322 #define P6_INTF_MODE_TRGMII 1
324 #define NUM_TRGMII_CTRL 5
326 #define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
328 #define RD_TAP_M 0x7f
330 #define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
331 /* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
333 /* TOP Signals Status Register */
334 #define MT7531_TOP_SIG_SR 0x780c
335 #define PAD_MCM_SMI_EN BIT(0)
336 #define PAD_DUAL_SGMII_EN BIT(1)
338 /* MT7531 PLLGP Registers */
339 #define MT7531_PLLGP_EN 0x7820
340 #define EN_COREPLL BIT(2)
341 #define SW_CLKSW BIT(1)
342 #define SW_PLLGP BIT(0)
344 #define MT7531_PLLGP_CR0 0x78a8
345 #define RG_COREPLL_EN BIT(22)
346 #define RG_COREPLL_POSDIV_S 23
347 #define RG_COREPLL_POSDIV_M 0x3800000
348 #define RG_COREPLL_SDM_PCW_S 1
349 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
350 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
352 /* MT7531 RGMII and SGMII PLL clock */
353 #define MT7531_ANA_PLLGP_CR2 0x78b0
354 #define MT7531_ANA_PLLGP_CR5 0x78bc
356 /* MT7531 GPIO GROUP IOLB SMT0 Control */
357 #define MT7531_SMT0_IOLB 0x7f04
358 #define SMT_IOLB_5_SMI_MDC_EN BIT(5)
360 /* MT7530 GPHY MDIO Indirect Access Registers */
361 #define MII_MMD_ACC_CTL_REG 0x0d
363 #define MMD_CMD_M 0xc000
364 #define MMD_DEVAD_S 0
365 #define MMD_DEVAD_M 0x1f
367 /* MMD_CMD: MMD commands */
370 #define MMD_DATA_RW_POST_INC 2
371 #define MMD_DATA_W_POST_INC 3
373 #define MII_MMD_ADDR_DATA_REG 0x0e
375 /* MT7530 GPHY MDIO MMD Registers */
376 #define CORE_PLL_GROUP2 0x401
377 #define RG_SYSPLL_EN_NORMAL BIT(15)
378 #define RG_SYSPLL_VODEN BIT(14)
379 #define RG_SYSPLL_POSDIV_S 5
380 #define RG_SYSPLL_POSDIV_M 0x60
382 #define CORE_PLL_GROUP4 0x403
383 #define MT7531_BYPASS_MODE BIT(4)
384 #define MT7531_POWER_ON_OFF BIT(5)
385 #define RG_SYSPLL_DDSFBK_EN BIT(12)
386 #define RG_SYSPLL_BIAS_EN BIT(11)
387 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
389 #define CORE_PLL_GROUP5 0x404
390 #define RG_LCDDS_PCW_NCPO1_S 0
391 #define RG_LCDDS_PCW_NCPO1_M 0xffff
393 #define CORE_PLL_GROUP6 0x405
394 #define RG_LCDDS_PCW_NCPO0_S 0
395 #define RG_LCDDS_PCW_NCPO0_M 0xffff
397 #define CORE_PLL_GROUP7 0x406
398 #define RG_LCDDS_PWDB BIT(15)
399 #define RG_LCDDS_ISO_EN BIT(13)
400 #define RG_LCCDS_C_S 4
401 #define RG_LCCDS_C_M 0x70
402 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
404 #define CORE_PLL_GROUP10 0x409
405 #define RG_LCDDS_SSC_DELTA_S 0
406 #define RG_LCDDS_SSC_DELTA_M 0xfff
408 #define CORE_PLL_GROUP11 0x40a
409 #define RG_LCDDS_SSC_DELTA1_S 0
410 #define RG_LCDDS_SSC_DELTA1_M 0xfff
412 #define CORE_GSWPLL_GRP1 0x40d
413 #define RG_GSWPLL_POSDIV_200M_S 12
414 #define RG_GSWPLL_POSDIV_200M_M 0x3000
415 #define RG_GSWPLL_EN_PRE BIT(11)
416 #define RG_GSWPLL_FBKDIV_200M_S 0
417 #define RG_GSWPLL_FBKDIV_200M_M 0xff
419 #define CORE_GSWPLL_GRP2 0x40e
420 #define RG_GSWPLL_POSDIV_500M_S 8
421 #define RG_GSWPLL_POSDIV_500M_M 0x300
422 #define RG_GSWPLL_FBKDIV_500M_S 0
423 #define RG_GSWPLL_FBKDIV_500M_M 0xff
425 #define CORE_TRGMII_GSW_CLK_CG 0x410
426 #define REG_GSWCK_EN BIT(0)
427 #define REG_TRGMIICK_EN BIT(1)
429 /* Extend PHY Control Register 3 */
430 #define PHY_EXT_REG_14 0x14
432 /* Fields of PHY_EXT_REG_14 */
433 #define PHY_EN_DOWN_SHFIT BIT(4)
435 /* Extend PHY Control Register 4 */
436 #define PHY_EXT_REG_17 0x17
438 /* Fields of PHY_EXT_REG_17 */
439 #define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
441 /* PHY RXADC Control Register 7 */
442 #define PHY_DEV1E_REG_0C6 0x0c6
444 /* Fields of PHY_DEV1E_REG_0C6 */
445 #define PHY_POWER_SAVING_S 8
446 #define PHY_POWER_SAVING_M 0x300
447 #define PHY_POWER_SAVING_TX 0x0
449 /* PDMA descriptors */
455 } __packed __aligned(4);
457 struct mtk_rx_dma_v2 {
466 } __packed __aligned(4);
473 } __packed __aligned(4);
475 struct mtk_tx_dma_v2 {
484 } __packed __aligned(4);
486 /* PDMA TXD fields */
487 #define PDMA_TXD2_DDONE BIT(31)
488 #define PDMA_TXD2_LS0 BIT(30)
489 #define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16)
490 #define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v))
491 #define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8)
492 #define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v))
494 #define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25)
495 #define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v))
496 #define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24)
497 #define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v))
499 #define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16)
500 #define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v))
502 /* PDMA RXD fields */
503 #define PDMA_RXD2_DDONE BIT(31)
504 #define PDMA_RXD2_LS0 BIT(30)
505 #define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16)
506 #define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v))
507 #define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v))
508 #define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8)
509 #define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v))
510 #define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v))
512 #endif /* _MTK_ETH_H_ */