1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 * Author: Mark Lee <mark-mc.lee@mediatek.com>
20 #include <dm/device_compat.h>
21 #include <linux/err.h>
22 #include <linux/ioport.h>
23 #include <linux/mdio.h>
24 #include <linux/mii.h>
28 #define NUM_TX_DESC 24
29 #define NUM_RX_DESC 24
30 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
31 #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
32 #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
34 #define MT753X_NUM_PHYS 5
35 #define MT753X_NUM_PORTS 7
36 #define MT753X_DFL_SMI_ADDR 31
37 #define MT753X_SMI_ADDR_MASK 0x1f
39 #define MT753X_PHY_ADDR(base, addr) \
40 (((base) + (addr)) & 0x1f)
42 #define GDMA_FWD_TO_CPU \
48 (DP_PDMA << MYMAC_DP_S) | \
49 (DP_PDMA << BC_DP_S) | \
50 (DP_PDMA << MC_DP_S) | \
53 #define GDMA_FWD_DISCARD \
59 (DP_DISCARD << MYMAC_DP_S) | \
60 (DP_DISCARD << BC_DP_S) | \
61 (DP_DISCARD << MC_DP_S) | \
62 (DP_DISCARD << UN_DP_S))
64 struct pdma_rxd_info1 {
68 struct pdma_rxd_info2 {
77 struct pdma_rxd_info3 {
81 struct pdma_rxd_info4 {
95 struct pdma_rxd_info1 rxd_info1;
96 struct pdma_rxd_info2 rxd_info2;
97 struct pdma_rxd_info3 rxd_info3;
98 struct pdma_rxd_info4 rxd_info4;
101 struct pdma_txd_info1 {
105 struct pdma_txd_info2 {
114 struct pdma_txd_info3 {
118 struct pdma_txd_info4 {
129 struct pdma_txd_info1 txd_info1;
130 struct pdma_txd_info2 txd_info2;
131 struct pdma_txd_info3 txd_info3;
132 struct pdma_txd_info4 txd_info4;
147 struct mtk_eth_priv {
148 char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
150 struct pdma_txdesc *tx_ring_noc;
151 struct pdma_rxdesc *rx_ring_noc;
153 int rx_dma_owner_idx0;
154 int tx_cpu_owner_idx0;
156 void __iomem *fe_base;
157 void __iomem *gmac_base;
158 void __iomem *ethsys_base;
159 void __iomem *sgmii_base;
161 struct mii_dev *mdio_bus;
162 int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
163 int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
164 int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
165 int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
174 struct phy_device *phydev;
179 int (*switch_init)(struct mtk_eth_priv *priv);
183 struct gpio_desc rst_gpio;
186 struct reset_ctl rst_fe;
187 struct reset_ctl rst_mcm;
190 static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
192 writel(val, priv->fe_base + PDMA_BASE + reg);
195 static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
198 clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set);
201 static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
207 gdma_base = GDMA2_BASE;
209 gdma_base = GDMA1_BASE;
211 writel(val, priv->fe_base + gdma_base + reg);
214 static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
216 return readl(priv->gmac_base + reg);
219 static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
221 writel(val, priv->gmac_base + reg);
224 static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
226 clrsetbits_le32(priv->gmac_base + reg, clr, set);
229 static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
232 clrsetbits_le32(priv->ethsys_base + reg, clr, set);
235 /* Direct MDIO clause 22/45 access via SoC */
236 static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
242 val = (st << MDIO_ST_S) |
243 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
244 (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
245 (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
247 if (cmd == MDIO_CMD_WRITE)
248 val |= data & MDIO_RW_DATA_M;
250 mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
252 ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
253 PHY_ACS_ST, 0, 5000, 0);
255 pr_warn("MDIO access timeout\n");
259 if (cmd == MDIO_CMD_READ) {
260 val = mtk_gmac_read(priv, GMAC_PIAC_REG);
261 return val & MDIO_RW_DATA_M;
267 /* Direct MDIO clause 22 read via SoC */
268 static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
270 return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
273 /* Direct MDIO clause 22 write via SoC */
274 static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
276 return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
279 /* Direct MDIO clause 45 read via SoC */
280 static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
284 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
288 return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
292 /* Direct MDIO clause 45 write via SoC */
293 static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
298 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
302 return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
306 /* Indirect MDIO clause 45 read via MII registers */
307 static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
312 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
313 (MMD_ADDR << MMD_CMD_S) |
314 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
318 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
322 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
323 (MMD_DATA << MMD_CMD_S) |
324 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
328 return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
331 /* Indirect MDIO clause 45 write via MII registers */
332 static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
337 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
338 (MMD_ADDR << MMD_CMD_S) |
339 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
343 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
347 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
348 (MMD_DATA << MMD_CMD_S) |
349 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
353 return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
357 * MT7530 Internal Register Address Bits
358 * -------------------------------------------------------------------
359 * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
360 * |----------------------------------------|---------------|--------|
361 * | Page Address | Reg Address | Unused |
362 * -------------------------------------------------------------------
365 static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
367 int ret, low_word, high_word;
369 /* Write page address */
370 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
375 low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf);
380 high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10);
385 *data = ((u32)high_word << 16) | (low_word & 0xffff);
390 static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
394 /* Write page address */
395 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
400 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf,
405 /* Write high word */
406 return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16);
409 static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
414 mt753x_reg_read(priv, reg, &val);
417 mt753x_reg_write(priv, reg, val);
420 /* Indirect MDIO clause 22/45 access */
421 static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data,
428 val = (st << MDIO_ST_S) |
429 ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
430 ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
431 ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
433 if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
434 val |= data & MDIO_RW_DATA_M;
436 mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
439 timeout = get_timer(0);
441 mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
443 if ((val & PHY_ACS_ST) == 0)
446 if (get_timer(timeout) > timeout_ms)
450 if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
451 mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
452 ret = val & MDIO_RW_DATA_M;
458 static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
462 if (phy >= MT753X_NUM_PHYS)
465 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
467 return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ,
471 static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg,
476 if (phy >= MT753X_NUM_PHYS)
479 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
481 return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE,
485 int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
490 if (addr >= MT753X_NUM_PHYS)
493 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
495 ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
500 return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45,
504 static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
510 if (addr >= MT753X_NUM_PHYS)
513 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
515 ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
520 return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE,
524 static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
526 struct mtk_eth_priv *priv = bus->priv;
529 return priv->mii_read(priv, addr, reg);
531 return priv->mmd_read(priv, addr, devad, reg);
534 static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
537 struct mtk_eth_priv *priv = bus->priv;
540 return priv->mii_write(priv, addr, reg, val);
542 return priv->mmd_write(priv, addr, devad, reg, val);
545 static int mtk_mdio_register(struct udevice *dev)
547 struct mtk_eth_priv *priv = dev_get_priv(dev);
548 struct mii_dev *mdio_bus = mdio_alloc();
554 /* Assign MDIO access APIs according to the switch/phy */
557 priv->mii_read = mtk_mii_read;
558 priv->mii_write = mtk_mii_write;
559 priv->mmd_read = mtk_mmd_ind_read;
560 priv->mmd_write = mtk_mmd_ind_write;
563 priv->mii_read = mt7531_mii_ind_read;
564 priv->mii_write = mt7531_mii_ind_write;
565 priv->mmd_read = mt7531_mmd_ind_read;
566 priv->mmd_write = mt7531_mmd_ind_write;
569 priv->mii_read = mtk_mii_read;
570 priv->mii_write = mtk_mii_write;
571 priv->mmd_read = mtk_mmd_read;
572 priv->mmd_write = mtk_mmd_write;
575 mdio_bus->read = mtk_mdio_read;
576 mdio_bus->write = mtk_mdio_write;
577 snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
579 mdio_bus->priv = (void *)priv;
581 ret = mdio_register(mdio_bus);
586 priv->mdio_bus = mdio_bus;
591 static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg)
593 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
595 return priv->mmd_read(priv, phy_addr, 0x1f, reg);
598 static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
600 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
602 priv->mmd_write(priv, phy_addr, 0x1f, reg, val);
605 static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
607 u32 ncpo1, ssc_delta;
610 case PHY_INTERFACE_MODE_RGMII:
615 printf("error: xMII mode %d not supported\n", mode);
619 /* Disable MT7530 core clock */
620 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
622 /* Disable MT7530 PLL */
623 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
624 (2 << RG_GSWPLL_POSDIV_200M_S) |
625 (32 << RG_GSWPLL_FBKDIV_200M_S));
627 /* For MT7530 core clock = 500Mhz */
628 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2,
629 (1 << RG_GSWPLL_POSDIV_500M_S) |
630 (25 << RG_GSWPLL_FBKDIV_500M_S));
632 /* Enable MT7530 PLL */
633 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
634 (2 << RG_GSWPLL_POSDIV_200M_S) |
635 (32 << RG_GSWPLL_FBKDIV_200M_S) |
640 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
642 /* Setup the MT7530 TRGMII Tx Clock */
643 mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
644 mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0);
645 mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
646 mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
647 mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
648 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
650 mt753x_core_reg_write(priv, CORE_PLL_GROUP2,
651 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
652 (1 << RG_SYSPLL_POSDIV_S));
654 mt753x_core_reg_write(priv, CORE_PLL_GROUP7,
655 RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
656 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
658 /* Enable MT7530 core clock */
659 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
660 REG_GSWCK_EN | REG_TRGMIICK_EN);
665 static int mt7530_setup(struct mtk_eth_priv *priv)
667 u16 phy_addr, phy_val;
671 /* Select 250MHz clk for RGMII mode */
672 mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
673 ETHSYS_TRGMII_CLK_SEL362_5, 0);
675 /* Modify HWTRAP first to allow direct access to internal PHYs */
676 mt753x_reg_read(priv, HWTRAP_REG, &val);
679 mt753x_reg_write(priv, MHWTRAP_REG, val);
681 /* Calculate the phy base address */
682 val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
683 priv->mt753x_phy_base = (val | 0x7) + 1;
686 for (i = 0; i < MT753X_NUM_PHYS; i++) {
687 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
688 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
689 phy_val |= BMCR_PDOWN;
690 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
693 /* Force MAC link down before reset */
694 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
695 mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
698 mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
701 val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
702 MAC_MODE | FORCE_MODE |
703 MAC_TX_EN | MAC_RX_EN |
704 BKOFF_EN | BACKPR_EN |
705 (SPEED_1000M << FORCE_SPD_S) |
706 FORCE_DPX | FORCE_LINK;
708 /* MT7530 Port6: Forced 1000M/FD, FC disabled */
709 mt753x_reg_write(priv, PMCR_REG(6), val);
711 /* MT7530 Port5: Forced link down */
712 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
714 /* MT7530 Port6: Set to RGMII */
715 mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
717 /* Hardware Trap: Enable Port6, Disable Port5 */
718 mt753x_reg_read(priv, HWTRAP_REG, &val);
719 val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
720 (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
721 (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
722 val &= ~(C_MDIO_BPS | P6_INTF_DIS);
723 mt753x_reg_write(priv, MHWTRAP_REG, val);
725 /* Setup switch core pll */
726 mt7530_pad_clk_setup(priv, priv->phy_interface);
728 /* Lower Tx Driving for TRGMII path */
729 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
730 mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
731 (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
733 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
734 mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
737 for (i = 0; i < MT753X_NUM_PHYS; i++) {
738 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
739 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
740 phy_val &= ~BMCR_PDOWN;
741 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
747 static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm)
749 /* Step 1 : Disable MT7531 COREPLL */
750 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0);
752 /* Step 2: switch to XTAL output */
753 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW);
755 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0);
757 /* Step 3: disable PLLGP and enable program PLLGP */
758 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP);
760 /* Step 4: program COREPLL output frequency to 500MHz */
761 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M,
762 2 << RG_COREPLL_POSDIV_S);
765 /* Currently, support XTAL 25Mhz only */
766 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M,
767 0x140000 << RG_COREPLL_SDM_PCW_S);
769 /* Set feedback divide ratio update signal to high */
770 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG,
771 RG_COREPLL_SDM_PCW_CHG);
773 /* Wait for at least 16 XTAL clocks */
776 /* Step 5: set feedback divide ratio update signal to low */
777 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0);
779 /* add enable 325M clock for SGMII */
780 mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
782 /* add enable 250SSC clock for RGMII */
783 mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
785 /*Step 6: Enable MT7531 PLL */
786 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN);
788 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL);
793 static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv,
796 if (port != 5 && port != 6) {
797 printf("mt7531: port %d is not a SGMII port\n", port);
801 /* Set SGMII GEN2 speed(2.5G) */
802 mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
803 SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
805 /* Disable SGMII AN */
806 mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
809 /* SGMII force mode setting */
810 mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE);
812 /* Release PHYA power down state */
813 mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
819 static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port)
824 printf("error: RGMII mode is not available for port %d\n",
829 mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val);
832 val |= GP_MODE_RGMII << GP_MODE_S;
833 val |= TXCLK_NO_REVERSE;
834 val |= RXCLK_NO_DELAY;
835 val &= ~CLK_SKEW_IN_M;
836 val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;
837 val &= ~CLK_SKEW_OUT_M;
838 val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;
839 mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val);
844 static void mt7531_phy_setting(struct mtk_eth_priv *priv)
849 for (i = 0; i < MT753X_NUM_PHYS; i++) {
850 /* Enable HW auto downshift */
851 priv->mii_write(priv, i, 0x1f, 0x1);
852 val = priv->mii_read(priv, i, PHY_EXT_REG_14);
853 val |= PHY_EN_DOWN_SHFIT;
854 priv->mii_write(priv, i, PHY_EXT_REG_14, val);
856 /* PHY link down power saving enable */
857 val = priv->mii_read(priv, i, PHY_EXT_REG_17);
858 val |= PHY_LINKDOWN_POWER_SAVING_EN;
859 priv->mii_write(priv, i, PHY_EXT_REG_17, val);
861 val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6);
862 val &= ~PHY_POWER_SAVING_M;
863 val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
864 priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val);
868 static int mt7531_setup(struct mtk_eth_priv *priv)
870 u16 phy_addr, phy_val;
876 priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
877 MT753X_SMI_ADDR_MASK;
880 for (i = 0; i < MT753X_NUM_PHYS; i++) {
881 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
882 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
883 phy_val |= BMCR_PDOWN;
884 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
887 /* Force MAC link down before reset */
888 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
889 mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
891 /* Switch soft reset */
892 mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
895 /* Enable MDC input Schmitt Trigger */
896 mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN,
897 SMT_IOLB_5_SMI_MDC_EN);
899 mt7531_core_pll_setup(priv, priv->mcm);
901 mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val);
902 port5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
904 /* port5 support either RGMII or SGMII, port6 only support SGMII. */
905 switch (priv->phy_interface) {
906 case PHY_INTERFACE_MODE_RGMII:
908 mt7531_port_rgmii_init(priv, 5);
910 case PHY_INTERFACE_MODE_SGMII:
911 mt7531_port_sgmii_init(priv, 6);
913 mt7531_port_sgmii_init(priv, 5);
919 pmcr = MT7531_FORCE_MODE |
920 (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
921 MAC_MODE | MAC_TX_EN | MAC_RX_EN |
922 BKOFF_EN | BACKPR_EN |
923 FORCE_RX_FC | FORCE_TX_FC |
924 (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
927 mt753x_reg_write(priv, PMCR_REG(5), pmcr);
928 mt753x_reg_write(priv, PMCR_REG(6), pmcr);
931 for (i = 0; i < MT753X_NUM_PHYS; i++) {
932 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
933 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
934 phy_val &= ~BMCR_PDOWN;
935 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
938 mt7531_phy_setting(priv);
940 /* Enable Internal PHYs */
941 val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4);
942 val |= MT7531_BYPASS_MODE;
943 val &= ~MT7531_POWER_ON_OFF;
944 mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val);
949 int mt753x_switch_init(struct mtk_eth_priv *priv)
954 /* Global reset switch */
956 reset_assert(&priv->rst_mcm);
958 reset_deassert(&priv->rst_mcm);
960 } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
961 dm_gpio_set_value(&priv->rst_gpio, 0);
963 dm_gpio_set_value(&priv->rst_gpio, 1);
967 ret = priv->switch_init(priv);
971 /* Set port isolation */
972 for (i = 0; i < MT753X_NUM_PORTS; i++) {
973 /* Set port matrix mode */
975 mt753x_reg_write(priv, PCR_REG(i),
976 (0x40 << PORT_MATRIX_S));
978 mt753x_reg_write(priv, PCR_REG(i),
979 (0x3f << PORT_MATRIX_S));
981 /* Set port mode to user port */
982 mt753x_reg_write(priv, PVC_REG(i),
983 (0x8100 << STAG_VPID_S) |
984 (VLAN_ATTR_USER << VLAN_ATTR_S));
990 static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
992 u16 lcl_adv = 0, rmt_adv = 0;
996 mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
997 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
998 MAC_MODE | FORCE_MODE |
999 MAC_TX_EN | MAC_RX_EN |
1000 BKOFF_EN | BACKPR_EN;
1002 switch (priv->phydev->speed) {
1004 mcr |= (SPEED_10M << FORCE_SPD_S);
1007 mcr |= (SPEED_100M << FORCE_SPD_S);
1010 mcr |= (SPEED_1000M << FORCE_SPD_S);
1014 if (priv->phydev->link)
1017 if (priv->phydev->duplex) {
1020 if (priv->phydev->pause)
1021 rmt_adv = LPA_PAUSE_CAP;
1022 if (priv->phydev->asym_pause)
1023 rmt_adv |= LPA_PAUSE_ASYM;
1025 if (priv->phydev->advertising & ADVERTISED_Pause)
1026 lcl_adv |= ADVERTISE_PAUSE_CAP;
1027 if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
1028 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1030 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1032 if (flowctrl & FLOW_CTRL_TX)
1034 if (flowctrl & FLOW_CTRL_RX)
1037 debug("rx pause %s, tx pause %s\n",
1038 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
1039 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
1042 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
1045 static int mtk_phy_start(struct mtk_eth_priv *priv)
1047 struct phy_device *phydev = priv->phydev;
1050 ret = phy_startup(phydev);
1053 debug("Could not initialize PHY %s\n", phydev->dev->name);
1057 if (!phydev->link) {
1058 debug("%s: link down.\n", phydev->dev->name);
1062 mtk_phy_link_adjust(priv);
1064 debug("Speed: %d, %s duplex%s\n", phydev->speed,
1065 (phydev->duplex) ? "full" : "half",
1066 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
1071 static int mtk_phy_probe(struct udevice *dev)
1073 struct mtk_eth_priv *priv = dev_get_priv(dev);
1074 struct phy_device *phydev;
1076 phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
1077 priv->phy_interface);
1081 phydev->supported &= PHY_GBIT_FEATURES;
1082 phydev->advertising = phydev->supported;
1084 priv->phydev = phydev;
1090 static void mtk_sgmii_init(struct mtk_eth_priv *priv)
1092 /* Set SGMII GEN2 speed(2.5G) */
1093 clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED,
1094 SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
1096 /* Disable SGMII AN */
1097 clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
1098 SGMII_AN_ENABLE, 0);
1100 /* SGMII force mode setting */
1101 writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
1103 /* Release PHYA power down state */
1104 clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
1108 static void mtk_mac_init(struct mtk_eth_priv *priv)
1113 switch (priv->phy_interface) {
1114 case PHY_INTERFACE_MODE_RGMII_RXID:
1115 case PHY_INTERFACE_MODE_RGMII:
1116 ge_mode = GE_MODE_RGMII;
1118 case PHY_INTERFACE_MODE_SGMII:
1119 ge_mode = GE_MODE_RGMII;
1120 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
1121 SYSCFG0_SGMII_SEL(priv->gmac_id));
1122 mtk_sgmii_init(priv);
1124 case PHY_INTERFACE_MODE_MII:
1125 case PHY_INTERFACE_MODE_GMII:
1126 ge_mode = GE_MODE_MII;
1128 case PHY_INTERFACE_MODE_RMII:
1129 ge_mode = GE_MODE_RMII;
1135 /* set the gmac to the right mode */
1136 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
1137 SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
1138 ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
1140 if (priv->force_mode) {
1141 mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
1142 (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
1143 MAC_MODE | FORCE_MODE |
1144 MAC_TX_EN | MAC_RX_EN |
1145 BKOFF_EN | BACKPR_EN |
1148 switch (priv->speed) {
1150 mcr |= SPEED_10M << FORCE_SPD_S;
1153 mcr |= SPEED_100M << FORCE_SPD_S;
1156 mcr |= SPEED_1000M << FORCE_SPD_S;
1163 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
1166 if (priv->soc == SOC_MT7623) {
1167 /* Lower Tx Driving for TRGMII path */
1168 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
1169 mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
1170 (8 << TD_DM_DRVP_S) |
1171 (8 << TD_DM_DRVN_S));
1173 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
1174 RX_RST | RXC_DQSISEL);
1175 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
1179 static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
1181 char *pkt_base = priv->pkt_pool;
1184 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
1187 memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc));
1188 memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
1189 memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
1191 flush_dcache_range((ulong)pkt_base,
1192 (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE));
1194 priv->rx_dma_owner_idx0 = 0;
1195 priv->tx_cpu_owner_idx0 = 0;
1197 for (i = 0; i < NUM_TX_DESC; i++) {
1198 priv->tx_ring_noc[i].txd_info2.LS0 = 1;
1199 priv->tx_ring_noc[i].txd_info2.DDONE = 1;
1200 priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1;
1202 priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base);
1203 pkt_base += PKTSIZE_ALIGN;
1206 for (i = 0; i < NUM_RX_DESC; i++) {
1207 priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
1208 priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base);
1209 pkt_base += PKTSIZE_ALIGN;
1212 mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
1213 virt_to_phys(priv->tx_ring_noc));
1214 mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
1215 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
1217 mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
1218 virt_to_phys(priv->rx_ring_noc));
1219 mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
1220 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
1222 mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
1225 static int mtk_eth_start(struct udevice *dev)
1227 struct mtk_eth_priv *priv = dev_get_priv(dev);
1231 reset_assert(&priv->rst_fe);
1233 reset_deassert(&priv->rst_fe);
1236 /* Packets forward to PDMA */
1237 mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
1239 if (priv->gmac_id == 0)
1240 mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
1242 mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
1246 mtk_eth_fifo_init(priv);
1249 if (priv->sw == SW_NONE) {
1250 ret = mtk_phy_start(priv);
1255 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
1256 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
1262 static void mtk_eth_stop(struct udevice *dev)
1264 struct mtk_eth_priv *priv = dev_get_priv(dev);
1266 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
1267 TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
1270 wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG,
1271 RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
1274 static int mtk_eth_write_hwaddr(struct udevice *dev)
1276 struct eth_pdata *pdata = dev_get_platdata(dev);
1277 struct mtk_eth_priv *priv = dev_get_priv(dev);
1278 unsigned char *mac = pdata->enetaddr;
1279 u32 macaddr_lsb, macaddr_msb;
1281 macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
1282 macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
1283 ((u32)mac[4] << 8) | (u32)mac[5];
1285 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
1286 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
1291 static int mtk_eth_send(struct udevice *dev, void *packet, int length)
1293 struct mtk_eth_priv *priv = dev_get_priv(dev);
1294 u32 idx = priv->tx_cpu_owner_idx0;
1297 if (!priv->tx_ring_noc[idx].txd_info2.DDONE) {
1298 debug("mtk-eth: TX DMA descriptor ring is full\n");
1302 pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
1303 memcpy(pkt_base, packet, length);
1304 flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
1305 roundup(length, ARCH_DMA_MINALIGN));
1307 priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
1308 priv->tx_ring_noc[idx].txd_info2.DDONE = 0;
1310 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
1311 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
1316 static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1318 struct mtk_eth_priv *priv = dev_get_priv(dev);
1319 u32 idx = priv->rx_dma_owner_idx0;
1323 if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) {
1324 debug("mtk-eth: RX DMA descriptor ring is empty\n");
1328 length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
1329 pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
1330 invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base +
1331 roundup(length, ARCH_DMA_MINALIGN));
1334 *packetp = pkt_base;
1339 static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
1341 struct mtk_eth_priv *priv = dev_get_priv(dev);
1342 u32 idx = priv->rx_dma_owner_idx0;
1344 priv->rx_ring_noc[idx].rxd_info2.DDONE = 0;
1345 priv->rx_ring_noc[idx].rxd_info2.LS0 = 0;
1346 priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
1348 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
1349 priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
1354 static int mtk_eth_probe(struct udevice *dev)
1356 struct eth_pdata *pdata = dev_get_platdata(dev);
1357 struct mtk_eth_priv *priv = dev_get_priv(dev);
1358 ulong iobase = pdata->iobase;
1361 /* Frame Engine Register Base */
1362 priv->fe_base = (void *)iobase;
1364 /* GMAC Register Base */
1365 priv->gmac_base = (void *)(iobase + GMAC_BASE);
1368 ret = mtk_mdio_register(dev);
1372 /* Prepare for tx/rx rings */
1373 priv->tx_ring_noc = (struct pdma_txdesc *)
1374 noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC,
1376 priv->rx_ring_noc = (struct pdma_rxdesc *)
1377 noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC,
1383 /* Probe phy if switch is not specified */
1384 if (priv->sw == SW_NONE)
1385 return mtk_phy_probe(dev);
1387 /* Initialize switch */
1388 return mt753x_switch_init(priv);
1391 static int mtk_eth_remove(struct udevice *dev)
1393 struct mtk_eth_priv *priv = dev_get_priv(dev);
1395 /* MDIO unregister */
1396 mdio_unregister(priv->mdio_bus);
1397 mdio_free(priv->mdio_bus);
1399 /* Stop possibly started DMA */
1405 static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
1407 struct eth_pdata *pdata = dev_get_platdata(dev);
1408 struct mtk_eth_priv *priv = dev_get_priv(dev);
1409 struct ofnode_phandle_args args;
1410 struct regmap *regmap;
1415 priv->soc = dev_get_driver_data(dev);
1417 pdata->iobase = devfdt_get_addr(dev);
1419 /* get corresponding ethsys phandle */
1420 ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
1425 regmap = syscon_node_to_regmap(args.node);
1427 return PTR_ERR(regmap);
1429 priv->ethsys_base = regmap_get_range(regmap, 0);
1430 if (!priv->ethsys_base) {
1431 dev_err(dev, "Unable to find ethsys\n");
1435 /* Reset controllers */
1436 ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
1438 printf("error: Unable to get reset ctrl for frame engine\n");
1442 priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
1444 /* Interface mode is required */
1445 str = dev_read_string(dev, "phy-mode");
1447 pdata->phy_interface = phy_get_interface_by_name(str);
1448 priv->phy_interface = pdata->phy_interface;
1450 printf("error: phy-mode is not set\n");
1454 /* Force mode or autoneg */
1455 subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
1456 if (ofnode_valid(subnode)) {
1457 priv->force_mode = 1;
1458 priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
1459 priv->duplex = ofnode_read_bool(subnode, "full-duplex");
1461 if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
1462 priv->speed != SPEED_1000) {
1463 printf("error: no valid speed set in fixed-link\n");
1468 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1469 /* get corresponding sgmii phandle */
1470 ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
1475 regmap = syscon_node_to_regmap(args.node);
1478 return PTR_ERR(regmap);
1480 priv->sgmii_base = regmap_get_range(regmap, 0);
1482 if (!priv->sgmii_base) {
1483 dev_err(dev, "Unable to find sgmii\n");
1488 /* check for switch first, otherwise phy will be used */
1490 priv->switch_init = NULL;
1491 str = dev_read_string(dev, "mediatek,switch");
1494 if (!strcmp(str, "mt7530")) {
1495 priv->sw = SW_MT7530;
1496 priv->switch_init = mt7530_setup;
1497 priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
1498 } else if (!strcmp(str, "mt7531")) {
1499 priv->sw = SW_MT7531;
1500 priv->switch_init = mt7531_setup;
1501 priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
1503 printf("error: unsupported switch\n");
1507 priv->mcm = dev_read_bool(dev, "mediatek,mcm");
1509 ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
1511 printf("error: no reset ctrl for mcm\n");
1515 gpio_request_by_name(dev, "reset-gpios", 0,
1516 &priv->rst_gpio, GPIOD_IS_OUT);
1519 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
1522 printf("error: phy-handle is not specified\n");
1526 priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
1527 if (priv->phy_addr < 0) {
1528 printf("error: phy address is not specified\n");
1536 static const struct udevice_id mtk_eth_ids[] = {
1537 { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
1538 { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
1539 { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
1543 static const struct eth_ops mtk_eth_ops = {
1544 .start = mtk_eth_start,
1545 .stop = mtk_eth_stop,
1546 .send = mtk_eth_send,
1547 .recv = mtk_eth_recv,
1548 .free_pkt = mtk_eth_free_pkt,
1549 .write_hwaddr = mtk_eth_write_hwaddr,
1552 U_BOOT_DRIVER(mtk_eth) = {
1555 .of_match = mtk_eth_ids,
1556 .ofdata_to_platdata = mtk_eth_ofdata_to_platdata,
1557 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1558 .probe = mtk_eth_probe,
1559 .remove = mtk_eth_remove,
1560 .ops = &mtk_eth_ops,
1561 .priv_auto_alloc_size = sizeof(struct mtk_eth_priv),
1562 .flags = DM_FLAG_ALLOC_PRIV_DMA,