drivers/net/mscc_eswitch/serval_switch.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Microsemi Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <config.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <dm/of_access.h>
  12 #include <dm/of_addr.h>
  13 #include <fdt_support.h>
  14 #include <linux/io.h>
  15 #include <linux/ioport.h>
  16 #include <miiphy.h>
  17 #include <net.h>
  18 #include <wait_bit.h>
  19
  20 #include "mscc_xfer.h"
  21 #include "mscc_mac_table.h"
  22 #include "mscc_miim.h"
  23
  24 #define ANA_PORT_VLAN_CFG(x)                    (0xc000 + 0x100 * (x))
  25 #define         ANA_PORT_VLAN_CFG_AWARE_ENA             BIT(20)
  26 #define         ANA_PORT_VLAN_CFG_POP_CNT(x)            ((x) << 18)
  27 #define ANA_PORT_PORT_CFG(x)                    (0xc070 + 0x100 * (x))
  28 #define         ANA_PORT_PORT_CFG_RECV_ENA              BIT(6)
  29 #define ANA_PGID(x)                             (0x9c00 + 4 * (x))
  30
  31 #define HSIO_ANA_SERDES1G_DES_CFG               0x3c
  32 #define         HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)            ((x) << 1)
  33 #define         HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x)             ((x) << 5)
  34 #define         HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x)          ((x) << 8)
  35 #define         HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x)           ((x) << 13)
  36 #define HSIO_ANA_SERDES1G_IB_CFG                0x40
  37 #define         HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x)       (x)
  38 #define         HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x)             ((x) << 6)
  39 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP        BIT(9)
  40 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV             BIT(11)
  41 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM           BIT(13)
  42 #define         HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x)             ((x) << 19)
  43 #define         HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x)         ((x) << 24)
  44 #define HSIO_ANA_SERDES1G_OB_CFG                0x44
  45 #define         HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x)       (x)
  46 #define         HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)            ((x) << 4)
  47 #define         HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x)       ((x) << 10)
  48 #define         HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)            ((x) << 13)
  49 #define         HSIO_ANA_SERDES1G_OB_CFG_SLP(x)                 ((x) << 17)
  50 #define HSIO_ANA_SERDES1G_SER_CFG               0x48
  51 #define HSIO_ANA_SERDES1G_COMMON_CFG            0x4c
  52 #define         HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE            BIT(0)
  53 #define         HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE           BIT(18)
  54 #define         HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST            BIT(31)
  55 #define HSIO_ANA_SERDES1G_PLL_CFG               0x50
  56 #define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA               BIT(7)
  57 #define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x)      ((x) << 8)
  58 #define         HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2           BIT(21)
  59 #define HSIO_DIG_SERDES1G_DFT_CFG0              0x58
  60 #define HSIO_DIG_SERDES1G_MISC_CFG              0x6c
  61 #define         HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST             BIT(0)
  62 #define HSIO_MCB_SERDES1G_CFG                   0x74
  63 #define         HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT       BIT(31)
  64 #define         HSIO_MCB_SERDES1G_CFG_ADDR(x)           (x)
  65
  66 #define SYS_FRM_AGING                           0x584
  67 #define         SYS_FRM_AGING_ENA                       BIT(20)
  68 #define SYS_SYSTEM_RST_CFG                      0x518
  69 #define         SYS_SYSTEM_RST_MEM_INIT                 BIT(5)
  70 #define         SYS_SYSTEM_RST_MEM_ENA                  BIT(6)
  71 #define         SYS_SYSTEM_RST_CORE_ENA                 BIT(7)
  72 #define SYS_PORT_MODE(x)                        (0x524 + 0x4 * (x))
  73 #define         SYS_PORT_MODE_INCL_INJ_HDR(x)           ((x) << 4)
  74 #define         SYS_PORT_MODE_INCL_XTR_HDR(x)           ((x) << 2)
  75 #define SYS_PAUSE_CFG(x)                        (0x65c + 0x4 * (x))
  76 #define         SYS_PAUSE_CFG_PAUSE_ENA                 BIT(0)
  77
  78 #define QSYS_SWITCH_PORT_MODE(x)                (0x15a34 + 0x4 * (x))
  79 #define         QSYS_SWITCH_PORT_MODE_PORT_ENA          BIT(13)
  80 #define QSYS_EGR_NO_SHARING                     0x15a9c
  81 #define QSYS_QMAP                               0x15adc
  82
  83 /* Port registers */
  84 #define DEV_CLOCK_CFG                           0x0
  85 #define DEV_CLOCK_CFG_LINK_SPEED_1000                   1
  86 #define DEV_MAC_ENA_CFG                         0x10
  87 #define         DEV_MAC_ENA_CFG_RX_ENA                  BIT(4)
  88 #define         DEV_MAC_ENA_CFG_TX_ENA                  BIT(0)
  89 #define DEV_MAC_IFG_CFG                         0x24
  90 #define         DEV_MAC_IFG_CFG_TX_IFG(x)               ((x) << 8)
  91 #define         DEV_MAC_IFG_CFG_RX_IFG2(x)              ((x) << 4)
  92 #define         DEV_MAC_IFG_CFG_RX_IFG1(x)              (x)
  93 #define PCS1G_CFG                               0x3c
  94 #define         PCS1G_MODE_CFG_SGMII_MODE_ENA           BIT(0)
  95 #define PCS1G_MODE_CFG                          0x40
  96 #define PCS1G_SD_CFG                            0x44
  97 #define PCS1G_ANEG_CFG                          0x48
  98 #define         PCS1G_ANEG_CFG_ADV_ABILITY(x)           ((x) << 16)
  99
 100 #define QS_XTR_GRP_CFG(x)                       (4 * (x))
 101 #define         QS_XTR_GRP_CFG_MODE(x)                  ((x) << 2)
 102 #define         QS_XTR_GRP_CFG_BYTE_SWAP                BIT(0)
 103 #define QS_INJ_GRP_CFG(x)                       (0x24 + (x) * 4)
 104 #define         QS_INJ_GRP_CFG_MODE(x)                  ((x) << 2)
 105 #define         QS_INJ_GRP_CFG_BYTE_SWAP                BIT(0)
 106
 107 #define IFH_INJ_BYPASS          BIT(31)
 108 #define IFH_TAG_TYPE_C          0
 109 #define MAC_VID                 1
 110 #define CPU_PORT                11
 111 #define INTERNAL_PORT_MSK       0xFF
 112 #define IFH_LEN                 4
 113 #define ETH_ALEN                6
 114 #define PGID_BROADCAST          13
 115 #define PGID_UNICAST            14
 116
 117 static const char *const regs_names[] = {
 118         "port0", "port1", "port2", "port3", "port4", "port5", "port6",
 119         "port7", "port8", "port9", "port10",
 120         "ana", "qs", "qsys", "rew", "sys", "hsio",
 121 };
 122
 123 #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
 124 #define MAX_PORT 11
 125
 126 enum serval_ctrl_regs {
 127         ANA = MAX_PORT,
 128         QS,
 129         QSYS,
 130         REW,
 131         SYS,
 132         HSIO,
 133 };
 134
 135 #define SERVAL_MIIM_BUS_COUNT 2
 136
 137 struct serval_phy_port_t {
 138         size_t phy_addr;
 139         struct mii_dev *bus;
 140         u8 serdes_index;
 141         u8 phy_mode;
 142 };
 143
 144 struct serval_private {
 145         void __iomem *regs[REGS_NAMES_COUNT];
 146         struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
 147         struct serval_phy_port_t ports[MAX_PORT];
 148 };
 149
 150 static const unsigned long serval_regs_qs[] = {
 151         [MSCC_QS_XTR_RD] = 0x8,
 152         [MSCC_QS_XTR_FLUSH] = 0x18,
 153         [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
 154         [MSCC_QS_INJ_WR] = 0x2c,
 155         [MSCC_QS_INJ_CTRL] = 0x34,
 156 };
 157
 158 static const unsigned long serval_regs_ana_table[] = {
 159         [MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
 160         [MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
 161         [MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
 162 };
 163
 164 static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
 165 static int miim_count = -1;
 166
 167 static void serval_cpu_capture_setup(struct serval_private *priv)
 168 {
 169         int i;
 170
 171         /* map the 8 CPU extraction queues to CPU port 11 */
 172         writel(0, priv->regs[QSYS] + QSYS_QMAP);
 173
 174         for (i = 0; i <= 1; i++) {
 175                 /*
 176                  * Do byte-swap and expect status after last data word
 177                  * Extraction: Mode: manual extraction) | Byte_swap
 178                  */
 179                 writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
 180                        priv->regs[QS] + QS_XTR_GRP_CFG(i));
 181                 /*
 182                  * Injection: Mode: manual extraction | Byte_swap
 183                  */
 184                 writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
 185                        priv->regs[QS] + QS_INJ_GRP_CFG(i));
 186         }
 187
 188         for (i = 0; i <= 1; i++)
 189                 /* Enable IFH insertion/parsing on CPU ports */
 190                 writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
 191                        SYS_PORT_MODE_INCL_XTR_HDR(1),
 192                        priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
 193         /*
 194          * Setup the CPU port as VLAN aware to support switching frames
 195          * based on tags
 196          */
 197         writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 198                MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
 199
 200         /* Disable learning (only RECV_ENA must be set) */
 201         writel(ANA_PORT_PORT_CFG_RECV_ENA,
 202                priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
 203
 204         /* Enable switching to/from cpu port */
 205         setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
 206                      QSYS_SWITCH_PORT_MODE_PORT_ENA);
 207
 208         /* No pause on CPU port - not needed (off by default) */
 209         clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
 210                      SYS_PAUSE_CFG_PAUSE_ENA);
 211
 212         setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
 213 }
 214
 215 static void serval_port_init(struct serval_private *priv, int port)
 216 {
 217         void __iomem *regs = priv->regs[port];
 218
 219         /* Enable PCS */
 220         writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
 221
 222         /* Disable Signal Detect */
 223         writel(0, regs + PCS1G_SD_CFG);
 224
 225         /* Enable MAC RX and TX */
 226         writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
 227                regs + DEV_MAC_ENA_CFG);
 228
 229         /* Clear sgmii_mode_ena */
 230         writel(0, regs + PCS1G_MODE_CFG);
 231
 232         /*
 233          * Clear sw_resolve_ena(bit 0) and set adv_ability to
 234          * something meaningful just in case
 235          */
 236         writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
 237
 238         /* Set MAC IFG Gaps */
 239         writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
 240                DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
 241
 242         /* Set link speed and release all resets */
 243         writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
 244
 245         /* Make VLAN aware for CPU traffic */
 246         writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 247                MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
 248
 249         /* Enable the port in the core */
 250         setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
 251                      QSYS_SWITCH_PORT_MODE_PORT_ENA);
 252 }
 253
 254 static void serdes_write(void __iomem *base, u32 addr)
 255 {
 256         u32 data;
 257
 258         writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
 259                HSIO_MCB_SERDES1G_CFG_ADDR(addr),
 260                base + HSIO_MCB_SERDES1G_CFG);
 261
 262         do {
 263                 data = readl(base + HSIO_MCB_SERDES1G_CFG);
 264         } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
 265 }
 266
 267 static void serdes1g_setup(void __iomem *base, uint32_t addr,
 268                            phy_interface_t interface)
 269 {
 270         writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
 271         writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
 272         writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
 273                HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
 274                HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
 275                HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
 276                HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
 277                base + HSIO_ANA_SERDES1G_IB_CFG);
 278         writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
 279                HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
 280                HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
 281                HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
 282                base + HSIO_ANA_SERDES1G_DES_CFG);
 283         writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
 284                HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
 285                HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
 286                HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
 287                HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
 288                base + HSIO_ANA_SERDES1G_OB_CFG);
 289         writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 290                HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
 291                base + HSIO_ANA_SERDES1G_COMMON_CFG);
 292         writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
 293                HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
 294                HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
 295                base + HSIO_ANA_SERDES1G_PLL_CFG);
 296         writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
 297                base + HSIO_DIG_SERDES1G_MISC_CFG);
 298         serdes_write(base, addr);
 299
 300         writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 301                HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
 302                HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
 303                base + HSIO_ANA_SERDES1G_COMMON_CFG);
 304         serdes_write(base, addr);
 305
 306         writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
 307         serdes_write(base, addr);
 308 }
 309
 310 static void serdes_setup(struct serval_private *priv)
 311 {
 312         size_t mask;
 313         int i = 0;
 314
 315         for (i = 0; i < MAX_PORT; ++i) {
 316                 if (!priv->ports[i].bus)
 317                         continue;
 318
 319                 mask = BIT(priv->ports[i].serdes_index);
 320                 serdes1g_setup(priv->regs[HSIO], mask,
 321                                priv->ports[i].phy_mode);
 322         }
 323 }
 324
 325 static int serval_switch_init(struct serval_private *priv)
 326 {
 327         /* Reset switch & memories */
 328         writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
 329                priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
 330
 331         if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 332                               SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
 333                 pr_err("Timeout in memory reset\n");
 334                 return -EIO;
 335         }
 336
 337         /* Enable switch core */
 338         setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 339                      SYS_SYSTEM_RST_CORE_ENA);
 340
 341         serdes_setup(priv);
 342
 343         return 0;
 344 }
 345
 346 static int serval_initialize(struct serval_private *priv)
 347 {
 348         int ret, i;
 349
 350         /* Initialize switch memories, enable core */
 351         ret = serval_switch_init(priv);
 352         if (ret)
 353                 return ret;
 354
 355         /* Flush queues */
 356         mscc_flush(priv->regs[QS], serval_regs_qs);
 357
 358         /* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
 359         writel(SYS_FRM_AGING_ENA | (20000000 / 65),
 360                priv->regs[SYS] + SYS_FRM_AGING);
 361
 362         for (i = 0; i < MAX_PORT; i++)
 363                 serval_port_init(priv, i);
 364
 365         serval_cpu_capture_setup(priv);
 366
 367         debug("Ports enabled\n");
 368
 369         return 0;
 370 }
 371
 372 static int serval_write_hwaddr(struct udevice *dev)
 373 {
 374         struct serval_private *priv = dev_get_priv(dev);
 375         struct eth_pdata *pdata = dev_get_platdata(dev);
 376
 377         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
 378                            pdata->enetaddr, PGID_UNICAST);
 379
 380         writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 381
 382         return 0;
 383 }
 384
 385 static int serval_start(struct udevice *dev)
 386 {
 387         struct serval_private *priv = dev_get_priv(dev);
 388         struct eth_pdata *pdata = dev_get_platdata(dev);
 389         const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
 390                                               0xff };
 391         int ret;
 392
 393         ret = serval_initialize(priv);
 394         if (ret)
 395                 return ret;
 396
 397         /* Set MAC address tables entries for CPU redirection */
 398         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
 399                            PGID_BROADCAST);
 400
 401         writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
 402                priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
 403
 404         /* It should be setup latter in serval_write_hwaddr */
 405         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
 406                            pdata->enetaddr, PGID_UNICAST);
 407
 408         writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 409         return 0;
 410 }
 411
 412 static void serval_stop(struct udevice *dev)
 413 {
 414         writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
 415         writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
 416 }
 417
 418 static int serval_send(struct udevice *dev, void *packet, int length)
 419 {
 420         struct serval_private *priv = dev_get_priv(dev);
 421         u32 ifh[IFH_LEN];
 422         u32 *buf = packet;
 423
 424         /*
 425          * Generate the IFH for frame injection
 426          *
 427          * The IFH is a 128bit-value
 428          * bit 127: bypass the analyzer processing
 429          * bit 57-67: destination mask
 430          * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
 431          * bit 20-27: cpu extraction queue mask
 432          * bit 16: tag type 0: C-tag, 1: S-tag
 433          * bit 0-11: VID
 434          */
 435         ifh[0] = IFH_INJ_BYPASS;
 436         ifh[1] = (0x07);
 437         ifh[2] = (0x7f) << 25;
 438         ifh[3] = (IFH_TAG_TYPE_C << 16);
 439
 440         return mscc_send(priv->regs[QS], serval_regs_qs,
 441                          ifh, IFH_LEN, buf, length);
 442 }
 443
 444 static int serval_recv(struct udevice *dev, int flags, uchar **packetp)
 445 {
 446         struct serval_private *priv = dev_get_priv(dev);
 447         u32 *rxbuf = (u32 *)net_rx_packets[0];
 448         int byte_cnt = 0;
 449
 450         byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
 451                              false);
 452
 453         *packetp = net_rx_packets[0];
 454
 455         return byte_cnt;
 456 }
 457
 458 static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
 459 {
 460         int i = 0;
 461
 462         for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
 463                 if (miim[i].miim_base == base && miim[i].miim_size == size)
 464                         return miim[i].bus;
 465
 466         return NULL;
 467 }
 468
 469 static void add_port_entry(struct serval_private *priv, size_t index,
 470                            size_t phy_addr, struct mii_dev *bus,
 471                            u8 serdes_index, u8 phy_mode)
 472 {
 473         priv->ports[index].phy_addr = phy_addr;
 474         priv->ports[index].bus = bus;
 475         priv->ports[index].serdes_index = serdes_index;
 476         priv->ports[index].phy_mode = phy_mode;
 477 }
 478
 479 static int serval_probe(struct udevice *dev)
 480 {
 481         struct serval_private *priv = dev_get_priv(dev);
 482         int i, ret;
 483         struct resource res;
 484         fdt32_t faddr;
 485         phys_addr_t addr_base;
 486         unsigned long addr_size;
 487         ofnode eth_node, node, mdio_node;
 488         size_t phy_addr;
 489         struct mii_dev *bus;
 490         struct ofnode_phandle_args phandle;
 491         struct phy_device *phy;
 492
 493         if (!priv)
 494                 return -EINVAL;
 495
 496         /* Get registers and map them to the private structure */
 497         for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
 498                 priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
 499                 if (!priv->regs[i]) {
 500                         debug
 501                             ("Error can't get regs base addresses for %s\n",
 502                              regs_names[i]);
 503                         return -ENOMEM;
 504                 }
 505         }
 506
 507         /* Initialize miim buses */
 508         memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
 509
 510         /* iterate all the ports and find out on which bus they are */
 511         i = 0;
 512         eth_node = dev_read_first_subnode(dev);
 513         for (node = ofnode_first_subnode(eth_node);
 514              ofnode_valid(node);
 515              node = ofnode_next_subnode(node)) {
 516                 if (ofnode_read_resource(node, 0, &res))
 517                         return -ENOMEM;
 518                 i = res.start;
 519
 520                 ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
 521                                                      0, 0, &phandle);
 522                 if (ret)
 523                         continue;
 524
 525                 /* Get phy address on mdio bus */
 526                 if (ofnode_read_resource(phandle.node, 0, &res))
 527                         return -ENOMEM;
 528                 phy_addr = res.start;
 529
 530                 /* Get mdio node */
 531                 mdio_node = ofnode_get_parent(phandle.node);
 532
 533                 if (ofnode_read_resource(mdio_node, 0, &res))
 534                         return -ENOMEM;
 535                 faddr = cpu_to_fdt32(res.start);
 536
 537                 addr_base = ofnode_translate_address(mdio_node, &faddr);
 538                 addr_size = res.end - res.start;
 539
 540                 /* If the bus is new then create a new bus */
 541                 if (!get_mdiobus(addr_base, addr_size))
 542                         priv->bus[miim_count] =
 543                                 mscc_mdiobus_init(miim, &miim_count, addr_base,
 544                                                   addr_size);
 545
 546                 /* Connect mdio bus with the port */
 547                 bus = get_mdiobus(addr_base, addr_size);
 548
 549                 /* Get serdes info */
 550                 ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
 551                                                      3, 0, &phandle);
 552                 if (ret)
 553                         return -ENOMEM;
 554
 555                 add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
 556                                phandle.args[2]);
 557         }
 558
 559         for (i = 0; i < MAX_PORT; i++) {
 560                 if (!priv->ports[i].bus)
 561                         continue;
 562
 563                 phy = phy_connect(priv->ports[i].bus,
 564                                   priv->ports[i].phy_addr, dev,
 565                                   PHY_INTERFACE_MODE_NONE);
 566                 if (phy)
 567                         board_phy_config(phy);
 568         }
 569
 570         return 0;
 571 }
 572
 573 static int serval_remove(struct udevice *dev)
 574 {
 575         struct serval_private *priv = dev_get_priv(dev);
 576         int i;
 577
 578         for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
 579                 mdio_unregister(priv->bus[i]);
 580                 mdio_free(priv->bus[i]);
 581         }
 582
 583         return 0;
 584 }
 585
 586 static const struct eth_ops serval_ops = {
 587         .start        = serval_start,
 588         .stop         = serval_stop,
 589         .send         = serval_send,
 590         .recv         = serval_recv,
 591         .write_hwaddr = serval_write_hwaddr,
 592 };
 593
 594 static const struct udevice_id mscc_serval_ids[] = {
 595         {.compatible = "mscc,vsc7418-switch"},
 596         { /* Sentinel */ }
 597 };
 598
 599 U_BOOT_DRIVER(serval) = {
 600         .name                           = "serval-switch",
 601         .id                             = UCLASS_ETH,
 602         .of_match                       = mscc_serval_ids,
 603         .probe                          = serval_probe,
 604         .remove                         = serval_remove,
 605         .ops                            = &serval_ops,
 606         .priv_auto_alloc_size           = sizeof(struct serval_private),
 607         .platdata_auto_alloc_size       = sizeof(struct eth_pdata),
 608 };