1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Microsemi Corporation
9 #include <dm/of_access.h>
10 #include <dm/of_addr.h>
11 #include <fdt_support.h>
13 #include <linux/ioport.h>
18 #include "mscc_xfer.h"
19 #include "mscc_mac_table.h"
21 #define GCB_MIIM_MII_STATUS 0x0
22 #define GCB_MIIM_STAT_BUSY BIT(3)
23 #define GCB_MIIM_MII_CMD 0x8
24 #define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
25 #define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
26 #define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
27 #define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
28 #define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
29 #define GCB_MIIM_MII_CMD_VLD BIT(31)
30 #define GCB_MIIM_DATA 0xC
31 #define GCB_MIIM_DATA_ERROR (0x2 << 16)
33 #define ANA_PORT_VLAN_CFG(x) (0xc000 + 0x100 * (x))
34 #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
35 #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
36 #define ANA_PORT_PORT_CFG(x) (0xc070 + 0x100 * (x))
37 #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
38 #define ANA_PGID(x) (0x9c00 + 4 * (x))
40 #define HSIO_ANA_SERDES1G_DES_CFG 0x3c
41 #define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
42 #define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
43 #define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
44 #define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
45 #define HSIO_ANA_SERDES1G_IB_CFG 0x40
46 #define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
47 #define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
48 #define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
49 #define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
50 #define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
51 #define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19)
52 #define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
53 #define HSIO_ANA_SERDES1G_OB_CFG 0x44
54 #define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
55 #define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
56 #define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
57 #define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
58 #define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
59 #define HSIO_ANA_SERDES1G_SER_CFG 0x48
60 #define HSIO_ANA_SERDES1G_COMMON_CFG 0x4c
61 #define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
62 #define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
63 #define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
64 #define HSIO_ANA_SERDES1G_PLL_CFG 0x50
65 #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
66 #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
67 #define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
68 #define HSIO_DIG_SERDES1G_DFT_CFG0 0x58
69 #define HSIO_DIG_SERDES1G_MISC_CFG 0x6c
70 #define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
71 #define HSIO_MCB_SERDES1G_CFG 0x74
72 #define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
73 #define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
75 #define SYS_FRM_AGING 0x584
76 #define SYS_FRM_AGING_ENA BIT(20)
77 #define SYS_SYSTEM_RST_CFG 0x518
78 #define SYS_SYSTEM_RST_MEM_INIT BIT(5)
79 #define SYS_SYSTEM_RST_MEM_ENA BIT(6)
80 #define SYS_SYSTEM_RST_CORE_ENA BIT(7)
81 #define SYS_PORT_MODE(x) (0x524 + 0x4 * (x))
82 #define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 4)
83 #define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 2)
84 #define SYS_PAUSE_CFG(x) (0x65c + 0x4 * (x))
85 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
87 #define QSYS_SWITCH_PORT_MODE(x) (0x15a34 + 0x4 * (x))
88 #define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(13)
89 #define QSYS_EGR_NO_SHARING 0x15a9c
90 #define QSYS_QMAP 0x15adc
93 #define DEV_CLOCK_CFG 0x0
94 #define DEV_CLOCK_CFG_LINK_SPEED_1000 1
95 #define DEV_MAC_ENA_CFG 0x10
96 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
97 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
98 #define DEV_MAC_IFG_CFG 0x24
99 #define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
100 #define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
101 #define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
102 #define PCS1G_CFG 0x3c
103 #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
104 #define PCS1G_MODE_CFG 0x40
105 #define PCS1G_SD_CFG 0x44
106 #define PCS1G_ANEG_CFG 0x48
107 #define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
109 #define QS_XTR_GRP_CFG(x) (4 * (x))
110 #define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
111 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
112 #define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
113 #define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
114 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
116 #define IFH_INJ_BYPASS BIT(31)
117 #define IFH_TAG_TYPE_C 0
120 #define INTERNAL_PORT_MSK 0xFF
123 #define PGID_BROADCAST 13
124 #define PGID_UNICAST 14
126 static const char *const regs_names[] = {
127 "port0", "port1", "port2", "port3", "port4", "port5", "port6",
128 "port7", "port8", "port9", "port10",
129 "ana", "qs", "qsys", "rew", "sys", "hsio",
132 #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
135 enum serval_ctrl_regs {
144 #define SERVAL_MIIM_BUS_COUNT 2
146 struct serval_phy_port_t {
153 struct serval_private {
154 void __iomem *regs[REGS_NAMES_COUNT];
155 struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
156 struct serval_phy_port_t ports[MAX_PORT];
159 struct mscc_miim_dev {
161 phys_addr_t miim_base;
162 unsigned long miim_size;
166 static const unsigned long serval_regs_qs[] = {
167 [MSCC_QS_XTR_RD] = 0x8,
168 [MSCC_QS_XTR_FLUSH] = 0x18,
169 [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
170 [MSCC_QS_INJ_WR] = 0x2c,
171 [MSCC_QS_INJ_CTRL] = 0x34,
174 static const unsigned long serval_regs_ana_table[] = {
175 [MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
176 [MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
177 [MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
180 static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
181 static int miim_count = -1;
183 static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
185 return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
186 GCB_MIIM_STAT_BUSY, false, 250, false);
189 static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
191 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
195 ret = mscc_miim_wait_ready(miim);
199 writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
200 GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
201 miim->regs + GCB_MIIM_MII_CMD);
203 ret = mscc_miim_wait_ready(miim);
207 val = readl(miim->regs + GCB_MIIM_DATA);
208 if (val & GCB_MIIM_DATA_ERROR) {
218 static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
221 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
224 ret = mscc_miim_wait_ready(miim);
228 writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
229 GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
230 GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
235 static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base,
236 unsigned long miim_size)
245 sprintf(bus->name, "miim-bus%d", miim_count);
247 miim[miim_count].regs = ioremap(miim_base, miim_size);
248 miim[miim_count].miim_base = miim_base;
249 miim[miim_count].miim_size = miim_size;
250 bus->priv = &miim[miim_count];
251 bus->read = mscc_miim_read;
252 bus->write = mscc_miim_write;
254 if (mdio_register(bus))
257 miim[miim_count].bus = bus;
261 static void serval_cpu_capture_setup(struct serval_private *priv)
265 /* map the 8 CPU extraction queues to CPU port 11 */
266 writel(0, priv->regs[QSYS] + QSYS_QMAP);
268 for (i = 0; i <= 1; i++) {
270 * Do byte-swap and expect status after last data word
271 * Extraction: Mode: manual extraction) | Byte_swap
273 writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
274 priv->regs[QS] + QS_XTR_GRP_CFG(i));
276 * Injection: Mode: manual extraction | Byte_swap
278 writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
279 priv->regs[QS] + QS_INJ_GRP_CFG(i));
282 for (i = 0; i <= 1; i++)
283 /* Enable IFH insertion/parsing on CPU ports */
284 writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
285 SYS_PORT_MODE_INCL_XTR_HDR(1),
286 priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
288 * Setup the CPU port as VLAN aware to support switching frames
291 writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
292 MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
294 /* Disable learning (only RECV_ENA must be set) */
295 writel(ANA_PORT_PORT_CFG_RECV_ENA,
296 priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
298 /* Enable switching to/from cpu port */
299 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
300 QSYS_SWITCH_PORT_MODE_PORT_ENA);
302 /* No pause on CPU port - not needed (off by default) */
303 clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
304 SYS_PAUSE_CFG_PAUSE_ENA);
306 setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
309 static void serval_port_init(struct serval_private *priv, int port)
311 void __iomem *regs = priv->regs[port];
314 writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
316 /* Disable Signal Detect */
317 writel(0, regs + PCS1G_SD_CFG);
319 /* Enable MAC RX and TX */
320 writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
321 regs + DEV_MAC_ENA_CFG);
323 /* Clear sgmii_mode_ena */
324 writel(0, regs + PCS1G_MODE_CFG);
327 * Clear sw_resolve_ena(bit 0) and set adv_ability to
328 * something meaningful just in case
330 writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
332 /* Set MAC IFG Gaps */
333 writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
334 DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
336 /* Set link speed and release all resets */
337 writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
339 /* Make VLAN aware for CPU traffic */
340 writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
341 MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
343 /* Enable the port in the core */
344 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
345 QSYS_SWITCH_PORT_MODE_PORT_ENA);
348 static void serdes_write(void __iomem *base, u32 addr)
352 writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
353 HSIO_MCB_SERDES1G_CFG_ADDR(addr),
354 base + HSIO_MCB_SERDES1G_CFG);
357 data = readl(base + HSIO_MCB_SERDES1G_CFG);
358 } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
363 static void serdes1g_setup(void __iomem *base, uint32_t addr,
364 phy_interface_t interface)
366 writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
367 writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
368 writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
369 HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
370 HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
371 HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
372 HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
373 base + HSIO_ANA_SERDES1G_IB_CFG);
374 writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
375 HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
376 HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
377 HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
378 base + HSIO_ANA_SERDES1G_DES_CFG);
379 writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
380 HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
381 HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
382 HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
383 HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
384 base + HSIO_ANA_SERDES1G_OB_CFG);
385 writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
386 HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
387 base + HSIO_ANA_SERDES1G_COMMON_CFG);
388 writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
389 HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
390 HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
391 base + HSIO_ANA_SERDES1G_PLL_CFG);
392 writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
393 base + HSIO_DIG_SERDES1G_MISC_CFG);
394 serdes_write(base, addr);
396 writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
397 HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
398 HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
399 base + HSIO_ANA_SERDES1G_COMMON_CFG);
400 serdes_write(base, addr);
402 writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
403 serdes_write(base, addr);
406 static void serdes_setup(struct serval_private *priv)
411 for (i = 0; i < MAX_PORT; ++i) {
412 if (!priv->ports[i].bus)
415 mask = BIT(priv->ports[i].serdes_index);
416 serdes1g_setup(priv->regs[HSIO], mask,
417 priv->ports[i].phy_mode);
421 static int serval_switch_init(struct serval_private *priv)
423 /* Reset switch & memories */
424 writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
425 priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
427 if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
428 SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
429 pr_err("Timeout in memory reset\n");
433 /* Enable switch core */
434 setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
435 SYS_SYSTEM_RST_CORE_ENA);
442 static int serval_initialize(struct serval_private *priv)
446 /* Initialize switch memories, enable core */
447 ret = serval_switch_init(priv);
452 mscc_flush(priv->regs[QS], serval_regs_qs);
454 /* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
455 writel(SYS_FRM_AGING_ENA | (20000000 / 65),
456 priv->regs[SYS] + SYS_FRM_AGING);
458 for (i = 0; i < MAX_PORT; i++)
459 serval_port_init(priv, i);
461 serval_cpu_capture_setup(priv);
463 debug("Ports enabled\n");
468 static int serval_write_hwaddr(struct udevice *dev)
470 struct serval_private *priv = dev_get_priv(dev);
471 struct eth_pdata *pdata = dev_get_platdata(dev);
473 mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
474 pdata->enetaddr, PGID_UNICAST);
476 writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
481 static int serval_start(struct udevice *dev)
483 struct serval_private *priv = dev_get_priv(dev);
484 struct eth_pdata *pdata = dev_get_platdata(dev);
485 const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
489 ret = serval_initialize(priv);
493 /* Set MAC address tables entries for CPU redirection */
494 mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
497 writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
498 priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
500 /* It should be setup latter in serval_write_hwaddr */
501 mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
502 pdata->enetaddr, PGID_UNICAST);
504 writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
508 static void serval_stop(struct udevice *dev)
510 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
511 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
514 static int serval_send(struct udevice *dev, void *packet, int length)
516 struct serval_private *priv = dev_get_priv(dev);
521 * Generate the IFH for frame injection
523 * The IFH is a 128bit-value
524 * bit 127: bypass the analyzer processing
525 * bit 57-67: destination mask
526 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
527 * bit 20-27: cpu extraction queue mask
528 * bit 16: tag type 0: C-tag, 1: S-tag
531 ifh[0] = IFH_INJ_BYPASS;
533 ifh[2] = (0x7f) << 25;
534 ifh[3] = (IFH_TAG_TYPE_C << 16);
536 return mscc_send(priv->regs[QS], serval_regs_qs,
537 ifh, IFH_LEN, buf, length);
540 static int serval_recv(struct udevice *dev, int flags, uchar **packetp)
542 struct serval_private *priv = dev_get_priv(dev);
543 u32 *rxbuf = (u32 *)net_rx_packets[0];
546 byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
549 *packetp = net_rx_packets[0];
554 static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
558 for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
559 if (miim[i].miim_base == base && miim[i].miim_size == size)
565 static void add_port_entry(struct serval_private *priv, size_t index,
566 size_t phy_addr, struct mii_dev *bus,
567 u8 serdes_index, u8 phy_mode)
569 priv->ports[index].phy_addr = phy_addr;
570 priv->ports[index].bus = bus;
571 priv->ports[index].serdes_index = serdes_index;
572 priv->ports[index].phy_mode = phy_mode;
575 static int serval_probe(struct udevice *dev)
577 struct serval_private *priv = dev_get_priv(dev);
581 phys_addr_t addr_base;
582 unsigned long addr_size;
583 ofnode eth_node, node, mdio_node;
586 struct ofnode_phandle_args phandle;
587 struct phy_device *phy;
592 /* Get registers and map them to the private structure */
593 for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
594 priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
595 if (!priv->regs[i]) {
597 ("Error can't get regs base addresses for %s\n",
603 /* Initialize miim buses */
604 memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
606 /* iterate all the ports and find out on which bus they are */
608 eth_node = dev_read_first_subnode(dev);
609 for (node = ofnode_first_subnode(eth_node);
611 node = ofnode_next_subnode(node)) {
612 if (ofnode_read_resource(node, 0, &res))
616 ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
621 /* Get phy address on mdio bus */
622 if (ofnode_read_resource(phandle.node, 0, &res))
624 phy_addr = res.start;
627 mdio_node = ofnode_get_parent(phandle.node);
629 if (ofnode_read_resource(mdio_node, 0, &res))
631 faddr = cpu_to_fdt32(res.start);
633 addr_base = ofnode_translate_address(mdio_node, &faddr);
634 addr_size = res.end - res.start;
636 /* If the bus is new then create a new bus */
637 if (!get_mdiobus(addr_base, addr_size))
638 priv->bus[miim_count] =
639 serval_mdiobus_init(addr_base, addr_size);
641 /* Connect mdio bus with the port */
642 bus = get_mdiobus(addr_base, addr_size);
644 /* Get serdes info */
645 ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
650 add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
654 for (i = 0; i < MAX_PORT; i++) {
655 if (!priv->ports[i].bus)
658 phy = phy_connect(priv->ports[i].bus,
659 priv->ports[i].phy_addr, dev,
660 PHY_INTERFACE_MODE_NONE);
662 board_phy_config(phy);
668 static int serval_remove(struct udevice *dev)
670 struct serval_private *priv = dev_get_priv(dev);
673 for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
674 mdio_unregister(priv->bus[i]);
675 mdio_free(priv->bus[i]);
681 static const struct eth_ops serval_ops = {
682 .start = serval_start,
686 .write_hwaddr = serval_write_hwaddr,
689 static const struct udevice_id mscc_serval_ids[] = {
690 {.compatible = "mscc,vsc7418-switch"},
694 U_BOOT_DRIVER(serval) = {
695 .name = "serval-switch",
697 .of_match = mscc_serval_ids,
698 .probe = serval_probe,
699 .remove = serval_remove,
701 .priv_auto_alloc_size = sizeof(struct serval_private),
702 .platdata_auto_alloc_size = sizeof(struct eth_pdata),