1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Microsemi Corporation
10 #include <dm/of_access.h>
11 #include <dm/of_addr.h>
12 #include <fdt_support.h>
14 #include <linux/ioport.h>
19 #include "mscc_xfer.h"
20 #include "mscc_mac_table.h"
21 #include "mscc_miim.h"
23 #define ANA_PORT_VLAN_CFG(x) (0xc000 + 0x100 * (x))
24 #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
25 #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
26 #define ANA_PORT_PORT_CFG(x) (0xc070 + 0x100 * (x))
27 #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
28 #define ANA_PGID(x) (0x9c00 + 4 * (x))
30 #define HSIO_ANA_SERDES1G_DES_CFG 0x3c
31 #define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
32 #define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
33 #define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
34 #define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
35 #define HSIO_ANA_SERDES1G_IB_CFG 0x40
36 #define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
37 #define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
38 #define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
39 #define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
40 #define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
41 #define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19)
42 #define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
43 #define HSIO_ANA_SERDES1G_OB_CFG 0x44
44 #define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
45 #define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
46 #define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
47 #define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
48 #define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
49 #define HSIO_ANA_SERDES1G_SER_CFG 0x48
50 #define HSIO_ANA_SERDES1G_COMMON_CFG 0x4c
51 #define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
52 #define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
53 #define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
54 #define HSIO_ANA_SERDES1G_PLL_CFG 0x50
55 #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
56 #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
57 #define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
58 #define HSIO_DIG_SERDES1G_DFT_CFG0 0x58
59 #define HSIO_DIG_SERDES1G_MISC_CFG 0x6c
60 #define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
61 #define HSIO_MCB_SERDES1G_CFG 0x74
62 #define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
63 #define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
65 #define SYS_FRM_AGING 0x584
66 #define SYS_FRM_AGING_ENA BIT(20)
67 #define SYS_SYSTEM_RST_CFG 0x518
68 #define SYS_SYSTEM_RST_MEM_INIT BIT(5)
69 #define SYS_SYSTEM_RST_MEM_ENA BIT(6)
70 #define SYS_SYSTEM_RST_CORE_ENA BIT(7)
71 #define SYS_PORT_MODE(x) (0x524 + 0x4 * (x))
72 #define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 4)
73 #define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 2)
74 #define SYS_PAUSE_CFG(x) (0x65c + 0x4 * (x))
75 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
77 #define QSYS_SWITCH_PORT_MODE(x) (0x15a34 + 0x4 * (x))
78 #define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(13)
79 #define QSYS_EGR_NO_SHARING 0x15a9c
80 #define QSYS_QMAP 0x15adc
83 #define DEV_CLOCK_CFG 0x0
84 #define DEV_CLOCK_CFG_LINK_SPEED_1000 1
85 #define DEV_MAC_ENA_CFG 0x10
86 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
87 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
88 #define DEV_MAC_IFG_CFG 0x24
89 #define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
90 #define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
91 #define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
92 #define PCS1G_CFG 0x3c
93 #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
94 #define PCS1G_MODE_CFG 0x40
95 #define PCS1G_SD_CFG 0x44
96 #define PCS1G_ANEG_CFG 0x48
97 #define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
99 #define QS_XTR_GRP_CFG(x) (4 * (x))
100 #define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
101 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
102 #define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
103 #define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
104 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
106 #define IFH_INJ_BYPASS BIT(31)
107 #define IFH_TAG_TYPE_C 0
110 #define INTERNAL_PORT_MSK 0xFF
113 #define PGID_BROADCAST 13
114 #define PGID_UNICAST 14
116 static const char *const regs_names[] = {
117 "port0", "port1", "port2", "port3", "port4", "port5", "port6",
118 "port7", "port8", "port9", "port10",
119 "ana", "qs", "qsys", "rew", "sys", "hsio",
122 #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
125 enum serval_ctrl_regs {
134 #define SERVAL_MIIM_BUS_COUNT 2
136 struct serval_phy_port_t {
143 struct serval_private {
144 void __iomem *regs[REGS_NAMES_COUNT];
145 struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
146 struct serval_phy_port_t ports[MAX_PORT];
149 static const unsigned long serval_regs_qs[] = {
150 [MSCC_QS_XTR_RD] = 0x8,
151 [MSCC_QS_XTR_FLUSH] = 0x18,
152 [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
153 [MSCC_QS_INJ_WR] = 0x2c,
154 [MSCC_QS_INJ_CTRL] = 0x34,
157 static const unsigned long serval_regs_ana_table[] = {
158 [MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
159 [MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
160 [MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
163 static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
164 static int miim_count = -1;
166 static void serval_cpu_capture_setup(struct serval_private *priv)
170 /* map the 8 CPU extraction queues to CPU port 11 */
171 writel(0, priv->regs[QSYS] + QSYS_QMAP);
173 for (i = 0; i <= 1; i++) {
175 * Do byte-swap and expect status after last data word
176 * Extraction: Mode: manual extraction) | Byte_swap
178 writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
179 priv->regs[QS] + QS_XTR_GRP_CFG(i));
181 * Injection: Mode: manual extraction | Byte_swap
183 writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
184 priv->regs[QS] + QS_INJ_GRP_CFG(i));
187 for (i = 0; i <= 1; i++)
188 /* Enable IFH insertion/parsing on CPU ports */
189 writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
190 SYS_PORT_MODE_INCL_XTR_HDR(1),
191 priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
193 * Setup the CPU port as VLAN aware to support switching frames
196 writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
197 MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
199 /* Disable learning (only RECV_ENA must be set) */
200 writel(ANA_PORT_PORT_CFG_RECV_ENA,
201 priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
203 /* Enable switching to/from cpu port */
204 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
205 QSYS_SWITCH_PORT_MODE_PORT_ENA);
207 /* No pause on CPU port - not needed (off by default) */
208 clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
209 SYS_PAUSE_CFG_PAUSE_ENA);
211 setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
214 static void serval_port_init(struct serval_private *priv, int port)
216 void __iomem *regs = priv->regs[port];
219 writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
221 /* Disable Signal Detect */
222 writel(0, regs + PCS1G_SD_CFG);
224 /* Enable MAC RX and TX */
225 writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
226 regs + DEV_MAC_ENA_CFG);
228 /* Clear sgmii_mode_ena */
229 writel(0, regs + PCS1G_MODE_CFG);
232 * Clear sw_resolve_ena(bit 0) and set adv_ability to
233 * something meaningful just in case
235 writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
237 /* Set MAC IFG Gaps */
238 writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
239 DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
241 /* Set link speed and release all resets */
242 writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
244 /* Make VLAN aware for CPU traffic */
245 writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
246 MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
248 /* Enable the port in the core */
249 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
250 QSYS_SWITCH_PORT_MODE_PORT_ENA);
253 static void serdes_write(void __iomem *base, u32 addr)
257 writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
258 HSIO_MCB_SERDES1G_CFG_ADDR(addr),
259 base + HSIO_MCB_SERDES1G_CFG);
262 data = readl(base + HSIO_MCB_SERDES1G_CFG);
263 } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
266 static void serdes1g_setup(void __iomem *base, uint32_t addr,
267 phy_interface_t interface)
269 writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
270 writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
271 writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
272 HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
273 HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
274 HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
275 HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
276 base + HSIO_ANA_SERDES1G_IB_CFG);
277 writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
278 HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
279 HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
280 HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
281 base + HSIO_ANA_SERDES1G_DES_CFG);
282 writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
283 HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
284 HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
285 HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
286 HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
287 base + HSIO_ANA_SERDES1G_OB_CFG);
288 writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
289 HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
290 base + HSIO_ANA_SERDES1G_COMMON_CFG);
291 writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
292 HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
293 HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
294 base + HSIO_ANA_SERDES1G_PLL_CFG);
295 writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
296 base + HSIO_DIG_SERDES1G_MISC_CFG);
297 serdes_write(base, addr);
299 writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
300 HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
301 HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
302 base + HSIO_ANA_SERDES1G_COMMON_CFG);
303 serdes_write(base, addr);
305 writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
306 serdes_write(base, addr);
309 static void serdes_setup(struct serval_private *priv)
314 for (i = 0; i < MAX_PORT; ++i) {
315 if (!priv->ports[i].bus)
318 mask = BIT(priv->ports[i].serdes_index);
319 serdes1g_setup(priv->regs[HSIO], mask,
320 priv->ports[i].phy_mode);
324 static int serval_switch_init(struct serval_private *priv)
326 /* Reset switch & memories */
327 writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
328 priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
330 if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
331 SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
332 pr_err("Timeout in memory reset\n");
336 /* Enable switch core */
337 setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
338 SYS_SYSTEM_RST_CORE_ENA);
345 static int serval_initialize(struct serval_private *priv)
349 /* Initialize switch memories, enable core */
350 ret = serval_switch_init(priv);
355 mscc_flush(priv->regs[QS], serval_regs_qs);
357 /* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
358 writel(SYS_FRM_AGING_ENA | (20000000 / 65),
359 priv->regs[SYS] + SYS_FRM_AGING);
361 for (i = 0; i < MAX_PORT; i++)
362 serval_port_init(priv, i);
364 serval_cpu_capture_setup(priv);
366 debug("Ports enabled\n");
371 static int serval_write_hwaddr(struct udevice *dev)
373 struct serval_private *priv = dev_get_priv(dev);
374 struct eth_pdata *pdata = dev_get_platdata(dev);
376 mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
377 pdata->enetaddr, PGID_UNICAST);
379 writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
384 static int serval_start(struct udevice *dev)
386 struct serval_private *priv = dev_get_priv(dev);
387 struct eth_pdata *pdata = dev_get_platdata(dev);
388 const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
392 ret = serval_initialize(priv);
396 /* Set MAC address tables entries for CPU redirection */
397 mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
400 writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
401 priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
403 /* It should be setup latter in serval_write_hwaddr */
404 mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
405 pdata->enetaddr, PGID_UNICAST);
407 writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
411 static void serval_stop(struct udevice *dev)
413 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
414 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
417 static int serval_send(struct udevice *dev, void *packet, int length)
419 struct serval_private *priv = dev_get_priv(dev);
424 * Generate the IFH for frame injection
426 * The IFH is a 128bit-value
427 * bit 127: bypass the analyzer processing
428 * bit 57-67: destination mask
429 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
430 * bit 20-27: cpu extraction queue mask
431 * bit 16: tag type 0: C-tag, 1: S-tag
434 ifh[0] = IFH_INJ_BYPASS;
436 ifh[2] = (0x7f) << 25;
437 ifh[3] = (IFH_TAG_TYPE_C << 16);
439 return mscc_send(priv->regs[QS], serval_regs_qs,
440 ifh, IFH_LEN, buf, length);
443 static int serval_recv(struct udevice *dev, int flags, uchar **packetp)
445 struct serval_private *priv = dev_get_priv(dev);
446 u32 *rxbuf = (u32 *)net_rx_packets[0];
449 byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
452 *packetp = net_rx_packets[0];
457 static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
461 for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
462 if (miim[i].miim_base == base && miim[i].miim_size == size)
468 static void add_port_entry(struct serval_private *priv, size_t index,
469 size_t phy_addr, struct mii_dev *bus,
470 u8 serdes_index, u8 phy_mode)
472 priv->ports[index].phy_addr = phy_addr;
473 priv->ports[index].bus = bus;
474 priv->ports[index].serdes_index = serdes_index;
475 priv->ports[index].phy_mode = phy_mode;
478 static int serval_probe(struct udevice *dev)
480 struct serval_private *priv = dev_get_priv(dev);
484 phys_addr_t addr_base;
485 unsigned long addr_size;
486 ofnode eth_node, node, mdio_node;
489 struct ofnode_phandle_args phandle;
490 struct phy_device *phy;
495 /* Get registers and map them to the private structure */
496 for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
497 priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
498 if (!priv->regs[i]) {
500 ("Error can't get regs base addresses for %s\n",
506 /* Initialize miim buses */
507 memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
509 /* iterate all the ports and find out on which bus they are */
511 eth_node = dev_read_first_subnode(dev);
512 for (node = ofnode_first_subnode(eth_node);
514 node = ofnode_next_subnode(node)) {
515 if (ofnode_read_resource(node, 0, &res))
519 ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
524 /* Get phy address on mdio bus */
525 if (ofnode_read_resource(phandle.node, 0, &res))
527 phy_addr = res.start;
530 mdio_node = ofnode_get_parent(phandle.node);
532 if (ofnode_read_resource(mdio_node, 0, &res))
534 faddr = cpu_to_fdt32(res.start);
536 addr_base = ofnode_translate_address(mdio_node, &faddr);
537 addr_size = res.end - res.start;
539 /* If the bus is new then create a new bus */
540 if (!get_mdiobus(addr_base, addr_size))
541 priv->bus[miim_count] =
542 mscc_mdiobus_init(miim, &miim_count, addr_base,
545 /* Connect mdio bus with the port */
546 bus = get_mdiobus(addr_base, addr_size);
548 /* Get serdes info */
549 ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
554 add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
558 for (i = 0; i < MAX_PORT; i++) {
559 if (!priv->ports[i].bus)
562 phy = phy_connect(priv->ports[i].bus,
563 priv->ports[i].phy_addr, dev,
564 PHY_INTERFACE_MODE_NONE);
566 board_phy_config(phy);
572 static int serval_remove(struct udevice *dev)
574 struct serval_private *priv = dev_get_priv(dev);
577 for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
578 mdio_unregister(priv->bus[i]);
579 mdio_free(priv->bus[i]);
585 static const struct eth_ops serval_ops = {
586 .start = serval_start,
590 .write_hwaddr = serval_write_hwaddr,
593 static const struct udevice_id mscc_serval_ids[] = {
594 {.compatible = "mscc,vsc7418-switch"},
598 U_BOOT_DRIVER(serval) = {
599 .name = "serval-switch",
601 .of_match = mscc_serval_ids,
602 .probe = serval_probe,
603 .remove = serval_remove,
605 .priv_auto_alloc_size = sizeof(struct serval_private),
606 .platdata_auto_alloc_size = sizeof(struct eth_pdata),