drivers/net/mscc_eswitch/serval_switch.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Microsemi Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <config.h>
   8 #include <dm.h>
   9 #include <dm/of_access.h>
  10 #include <dm/of_addr.h>
  11 #include <fdt_support.h>
  12 #include <linux/io.h>
  13 #include <linux/ioport.h>
  14 #include <miiphy.h>
  15 #include <net.h>
  16 #include <wait_bit.h>
  17
  18 #include "mscc_xfer.h"
  19 #include "mscc_mac_table.h"
  20
  21 #define GCB_MIIM_MII_STATUS                     0x0
  22 #define         GCB_MIIM_STAT_BUSY                      BIT(3)
  23 #define GCB_MIIM_MII_CMD                        0x8
  24 #define         GCB_MIIM_MII_CMD_OPR_WRITE              BIT(1)
  25 #define         GCB_MIIM_MII_CMD_OPR_READ               BIT(2)
  26 #define         GCB_MIIM_MII_CMD_WRDATA(x)              ((x) << 4)
  27 #define         GCB_MIIM_MII_CMD_REGAD(x)               ((x) << 20)
  28 #define         GCB_MIIM_MII_CMD_PHYAD(x)               ((x) << 25)
  29 #define         GCB_MIIM_MII_CMD_VLD                    BIT(31)
  30 #define GCB_MIIM_DATA                           0xC
  31 #define         GCB_MIIM_DATA_ERROR                     (0x2 << 16)
  32
  33 #define ANA_PORT_VLAN_CFG(x)                    (0xc000 + 0x100 * (x))
  34 #define         ANA_PORT_VLAN_CFG_AWARE_ENA             BIT(20)
  35 #define         ANA_PORT_VLAN_CFG_POP_CNT(x)            ((x) << 18)
  36 #define ANA_PORT_PORT_CFG(x)                    (0xc070 + 0x100 * (x))
  37 #define         ANA_PORT_PORT_CFG_RECV_ENA              BIT(6)
  38 #define ANA_PGID(x)                             (0x9c00 + 4 * (x))
  39
  40 #define HSIO_ANA_SERDES1G_DES_CFG               0x3c
  41 #define         HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)            ((x) << 1)
  42 #define         HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x)             ((x) << 5)
  43 #define         HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x)          ((x) << 8)
  44 #define         HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x)           ((x) << 13)
  45 #define HSIO_ANA_SERDES1G_IB_CFG                0x40
  46 #define         HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x)       (x)
  47 #define         HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x)             ((x) << 6)
  48 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP        BIT(9)
  49 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV             BIT(11)
  50 #define         HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM           BIT(13)
  51 #define         HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x)             ((x) << 19)
  52 #define         HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x)         ((x) << 24)
  53 #define HSIO_ANA_SERDES1G_OB_CFG                0x44
  54 #define         HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x)       (x)
  55 #define         HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)            ((x) << 4)
  56 #define         HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x)       ((x) << 10)
  57 #define         HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)            ((x) << 13)
  58 #define         HSIO_ANA_SERDES1G_OB_CFG_SLP(x)                 ((x) << 17)
  59 #define HSIO_ANA_SERDES1G_SER_CFG               0x48
  60 #define HSIO_ANA_SERDES1G_COMMON_CFG            0x4c
  61 #define         HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE            BIT(0)
  62 #define         HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE           BIT(18)
  63 #define         HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST            BIT(31)
  64 #define HSIO_ANA_SERDES1G_PLL_CFG               0x50
  65 #define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA               BIT(7)
  66 #define         HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x)      ((x) << 8)
  67 #define         HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2           BIT(21)
  68 #define HSIO_DIG_SERDES1G_DFT_CFG0              0x58
  69 #define HSIO_DIG_SERDES1G_MISC_CFG              0x6c
  70 #define         HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST             BIT(0)
  71 #define HSIO_MCB_SERDES1G_CFG                   0x74
  72 #define         HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT       BIT(31)
  73 #define         HSIO_MCB_SERDES1G_CFG_ADDR(x)           (x)
  74
  75 #define SYS_FRM_AGING                           0x584
  76 #define         SYS_FRM_AGING_ENA                       BIT(20)
  77 #define SYS_SYSTEM_RST_CFG                      0x518
  78 #define         SYS_SYSTEM_RST_MEM_INIT                 BIT(5)
  79 #define         SYS_SYSTEM_RST_MEM_ENA                  BIT(6)
  80 #define         SYS_SYSTEM_RST_CORE_ENA                 BIT(7)
  81 #define SYS_PORT_MODE(x)                        (0x524 + 0x4 * (x))
  82 #define         SYS_PORT_MODE_INCL_INJ_HDR(x)           ((x) << 4)
  83 #define         SYS_PORT_MODE_INCL_XTR_HDR(x)           ((x) << 2)
  84 #define SYS_PAUSE_CFG(x)                        (0x65c + 0x4 * (x))
  85 #define         SYS_PAUSE_CFG_PAUSE_ENA                 BIT(0)
  86
  87 #define QSYS_SWITCH_PORT_MODE(x)                (0x15a34 + 0x4 * (x))
  88 #define         QSYS_SWITCH_PORT_MODE_PORT_ENA          BIT(13)
  89 #define QSYS_EGR_NO_SHARING                     0x15a9c
  90 #define QSYS_QMAP                               0x15adc
  91
  92 /* Port registers */
  93 #define DEV_CLOCK_CFG                           0x0
  94 #define DEV_CLOCK_CFG_LINK_SPEED_1000                   1
  95 #define DEV_MAC_ENA_CFG                         0x10
  96 #define         DEV_MAC_ENA_CFG_RX_ENA                  BIT(4)
  97 #define         DEV_MAC_ENA_CFG_TX_ENA                  BIT(0)
  98 #define DEV_MAC_IFG_CFG                         0x24
  99 #define         DEV_MAC_IFG_CFG_TX_IFG(x)               ((x) << 8)
 100 #define         DEV_MAC_IFG_CFG_RX_IFG2(x)              ((x) << 4)
 101 #define         DEV_MAC_IFG_CFG_RX_IFG1(x)              (x)
 102 #define PCS1G_CFG                               0x3c
 103 #define         PCS1G_MODE_CFG_SGMII_MODE_ENA           BIT(0)
 104 #define PCS1G_MODE_CFG                          0x40
 105 #define PCS1G_SD_CFG                            0x44
 106 #define PCS1G_ANEG_CFG                          0x48
 107 #define         PCS1G_ANEG_CFG_ADV_ABILITY(x)           ((x) << 16)
 108
 109 #define QS_XTR_GRP_CFG(x)                       (4 * (x))
 110 #define         QS_XTR_GRP_CFG_MODE(x)                  ((x) << 2)
 111 #define         QS_XTR_GRP_CFG_BYTE_SWAP                BIT(0)
 112 #define QS_INJ_GRP_CFG(x)                       (0x24 + (x) * 4)
 113 #define         QS_INJ_GRP_CFG_MODE(x)                  ((x) << 2)
 114 #define         QS_INJ_GRP_CFG_BYTE_SWAP                BIT(0)
 115
 116 #define IFH_INJ_BYPASS          BIT(31)
 117 #define IFH_TAG_TYPE_C          0
 118 #define MAC_VID                 1
 119 #define CPU_PORT                11
 120 #define INTERNAL_PORT_MSK       0xFF
 121 #define IFH_LEN                 4
 122 #define ETH_ALEN                6
 123 #define PGID_BROADCAST          13
 124 #define PGID_UNICAST            14
 125
 126 static const char *const regs_names[] = {
 127         "port0", "port1", "port2", "port3", "port4", "port5", "port6",
 128         "port7", "port8", "port9", "port10",
 129         "ana", "qs", "qsys", "rew", "sys", "hsio",
 130 };
 131
 132 #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
 133 #define MAX_PORT 11
 134
 135 enum serval_ctrl_regs {
 136         ANA = MAX_PORT,
 137         QS,
 138         QSYS,
 139         REW,
 140         SYS,
 141         HSIO,
 142 };
 143
 144 #define SERVAL_MIIM_BUS_COUNT 2
 145
 146 struct serval_phy_port_t {
 147         size_t phy_addr;
 148         struct mii_dev *bus;
 149         u8 serdes_index;
 150         u8 phy_mode;
 151 };
 152
 153 struct serval_private {
 154         void __iomem *regs[REGS_NAMES_COUNT];
 155         struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
 156         struct serval_phy_port_t ports[MAX_PORT];
 157 };
 158
 159 struct mscc_miim_dev {
 160         void __iomem *regs;
 161         phys_addr_t miim_base;
 162         unsigned long miim_size;
 163         struct mii_dev *bus;
 164 };
 165
 166 static const unsigned long serval_regs_qs[] = {
 167         [MSCC_QS_XTR_RD] = 0x8,
 168         [MSCC_QS_XTR_FLUSH] = 0x18,
 169         [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
 170         [MSCC_QS_INJ_WR] = 0x2c,
 171         [MSCC_QS_INJ_CTRL] = 0x34,
 172 };
 173
 174 static const unsigned long serval_regs_ana_table[] = {
 175         [MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
 176         [MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
 177         [MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
 178 };
 179
 180 static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
 181 static int miim_count = -1;
 182
 183 static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
 184 {
 185         return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
 186                                  GCB_MIIM_STAT_BUSY, false, 250, false);
 187 }
 188
 189 static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
 190 {
 191         struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
 192         u32 val;
 193         int ret;
 194
 195         ret = mscc_miim_wait_ready(miim);
 196         if (ret)
 197                 goto out;
 198
 199         writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
 200                GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
 201                miim->regs + GCB_MIIM_MII_CMD);
 202
 203         ret = mscc_miim_wait_ready(miim);
 204         if (ret)
 205                 goto out;
 206
 207         val = readl(miim->regs + GCB_MIIM_DATA);
 208         if (val & GCB_MIIM_DATA_ERROR) {
 209                 ret = -EIO;
 210                 goto out;
 211         }
 212
 213         ret = val & 0xFFFF;
 214  out:
 215         return ret;
 216 }
 217
 218 static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
 219                            u16 val)
 220 {
 221         struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
 222         int ret;
 223
 224         ret = mscc_miim_wait_ready(miim);
 225         if (ret < 0)
 226                 goto out;
 227
 228         writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
 229                GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
 230                GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
 231  out:
 232         return ret;
 233 }
 234
 235 static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base,
 236                                            unsigned long miim_size)
 237 {
 238         struct mii_dev *bus;
 239
 240         bus = mdio_alloc();
 241         if (!bus)
 242                 return NULL;
 243
 244         ++miim_count;
 245         sprintf(bus->name, "miim-bus%d", miim_count);
 246
 247         miim[miim_count].regs = ioremap(miim_base, miim_size);
 248         miim[miim_count].miim_base = miim_base;
 249         miim[miim_count].miim_size = miim_size;
 250         bus->priv = &miim[miim_count];
 251         bus->read = mscc_miim_read;
 252         bus->write = mscc_miim_write;
 253
 254         if (mdio_register(bus))
 255                 return NULL;
 256
 257         miim[miim_count].bus = bus;
 258         return bus;
 259 }
 260
 261 static void serval_cpu_capture_setup(struct serval_private *priv)
 262 {
 263         int i;
 264
 265         /* map the 8 CPU extraction queues to CPU port 11 */
 266         writel(0, priv->regs[QSYS] + QSYS_QMAP);
 267
 268         for (i = 0; i <= 1; i++) {
 269                 /*
 270                  * Do byte-swap and expect status after last data word
 271                  * Extraction: Mode: manual extraction) | Byte_swap
 272                  */
 273                 writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
 274                        priv->regs[QS] + QS_XTR_GRP_CFG(i));
 275                 /*
 276                  * Injection: Mode: manual extraction | Byte_swap
 277                  */
 278                 writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
 279                        priv->regs[QS] + QS_INJ_GRP_CFG(i));
 280         }
 281
 282         for (i = 0; i <= 1; i++)
 283                 /* Enable IFH insertion/parsing on CPU ports */
 284                 writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
 285                        SYS_PORT_MODE_INCL_XTR_HDR(1),
 286                        priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
 287         /*
 288          * Setup the CPU port as VLAN aware to support switching frames
 289          * based on tags
 290          */
 291         writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 292                MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
 293
 294         /* Disable learning (only RECV_ENA must be set) */
 295         writel(ANA_PORT_PORT_CFG_RECV_ENA,
 296                priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
 297
 298         /* Enable switching to/from cpu port */
 299         setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
 300                      QSYS_SWITCH_PORT_MODE_PORT_ENA);
 301
 302         /* No pause on CPU port - not needed (off by default) */
 303         clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
 304                      SYS_PAUSE_CFG_PAUSE_ENA);
 305
 306         setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
 307 }
 308
 309 static void serval_port_init(struct serval_private *priv, int port)
 310 {
 311         void __iomem *regs = priv->regs[port];
 312
 313         /* Enable PCS */
 314         writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
 315
 316         /* Disable Signal Detect */
 317         writel(0, regs + PCS1G_SD_CFG);
 318
 319         /* Enable MAC RX and TX */
 320         writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
 321                regs + DEV_MAC_ENA_CFG);
 322
 323         /* Clear sgmii_mode_ena */
 324         writel(0, regs + PCS1G_MODE_CFG);
 325
 326         /*
 327          * Clear sw_resolve_ena(bit 0) and set adv_ability to
 328          * something meaningful just in case
 329          */
 330         writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
 331
 332         /* Set MAC IFG Gaps */
 333         writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
 334                DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
 335
 336         /* Set link speed and release all resets */
 337         writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
 338
 339         /* Make VLAN aware for CPU traffic */
 340         writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
 341                MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
 342
 343         /* Enable the port in the core */
 344         setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
 345                      QSYS_SWITCH_PORT_MODE_PORT_ENA);
 346 }
 347
 348 static void serdes_write(void __iomem *base, u32 addr)
 349 {
 350         u32 data;
 351
 352         writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
 353                HSIO_MCB_SERDES1G_CFG_ADDR(addr),
 354                base + HSIO_MCB_SERDES1G_CFG);
 355
 356         do {
 357                 data = readl(base + HSIO_MCB_SERDES1G_CFG);
 358         } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
 359 }
 360
 361 static void serdes1g_setup(void __iomem *base, uint32_t addr,
 362                            phy_interface_t interface)
 363 {
 364         writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
 365         writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
 366         writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
 367                HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
 368                HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
 369                HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
 370                HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
 371                base + HSIO_ANA_SERDES1G_IB_CFG);
 372         writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
 373                HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
 374                HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
 375                HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
 376                base + HSIO_ANA_SERDES1G_DES_CFG);
 377         writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
 378                HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
 379                HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
 380                HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
 381                HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
 382                base + HSIO_ANA_SERDES1G_OB_CFG);
 383         writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 384                HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
 385                base + HSIO_ANA_SERDES1G_COMMON_CFG);
 386         writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
 387                HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
 388                HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
 389                base + HSIO_ANA_SERDES1G_PLL_CFG);
 390         writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
 391                base + HSIO_DIG_SERDES1G_MISC_CFG);
 392         serdes_write(base, addr);
 393
 394         writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
 395                HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
 396                HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
 397                base + HSIO_ANA_SERDES1G_COMMON_CFG);
 398         serdes_write(base, addr);
 399
 400         writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
 401         serdes_write(base, addr);
 402 }
 403
 404 static void serdes_setup(struct serval_private *priv)
 405 {
 406         size_t mask;
 407         int i = 0;
 408
 409         for (i = 0; i < MAX_PORT; ++i) {
 410                 if (!priv->ports[i].bus)
 411                         continue;
 412
 413                 mask = BIT(priv->ports[i].serdes_index);
 414                 serdes1g_setup(priv->regs[HSIO], mask,
 415                                priv->ports[i].phy_mode);
 416         }
 417 }
 418
 419 static int serval_switch_init(struct serval_private *priv)
 420 {
 421         /* Reset switch & memories */
 422         writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
 423                priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
 424
 425         if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 426                               SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
 427                 pr_err("Timeout in memory reset\n");
 428                 return -EIO;
 429         }
 430
 431         /* Enable switch core */
 432         setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
 433                      SYS_SYSTEM_RST_CORE_ENA);
 434
 435         serdes_setup(priv);
 436
 437         return 0;
 438 }
 439
 440 static int serval_initialize(struct serval_private *priv)
 441 {
 442         int ret, i;
 443
 444         /* Initialize switch memories, enable core */
 445         ret = serval_switch_init(priv);
 446         if (ret)
 447                 return ret;
 448
 449         /* Flush queues */
 450         mscc_flush(priv->regs[QS], serval_regs_qs);
 451
 452         /* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
 453         writel(SYS_FRM_AGING_ENA | (20000000 / 65),
 454                priv->regs[SYS] + SYS_FRM_AGING);
 455
 456         for (i = 0; i < MAX_PORT; i++)
 457                 serval_port_init(priv, i);
 458
 459         serval_cpu_capture_setup(priv);
 460
 461         debug("Ports enabled\n");
 462
 463         return 0;
 464 }
 465
 466 static int serval_write_hwaddr(struct udevice *dev)
 467 {
 468         struct serval_private *priv = dev_get_priv(dev);
 469         struct eth_pdata *pdata = dev_get_platdata(dev);
 470
 471         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
 472                            pdata->enetaddr, PGID_UNICAST);
 473
 474         writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 475
 476         return 0;
 477 }
 478
 479 static int serval_start(struct udevice *dev)
 480 {
 481         struct serval_private *priv = dev_get_priv(dev);
 482         struct eth_pdata *pdata = dev_get_platdata(dev);
 483         const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
 484                                               0xff };
 485         int ret;
 486
 487         ret = serval_initialize(priv);
 488         if (ret)
 489                 return ret;
 490
 491         /* Set MAC address tables entries for CPU redirection */
 492         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
 493                            PGID_BROADCAST);
 494
 495         writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
 496                priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
 497
 498         /* It should be setup latter in serval_write_hwaddr */
 499         mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
 500                            pdata->enetaddr, PGID_UNICAST);
 501
 502         writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
 503         return 0;
 504 }
 505
 506 static void serval_stop(struct udevice *dev)
 507 {
 508         writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
 509         writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
 510 }
 511
 512 static int serval_send(struct udevice *dev, void *packet, int length)
 513 {
 514         struct serval_private *priv = dev_get_priv(dev);
 515         u32 ifh[IFH_LEN];
 516         u32 *buf = packet;
 517
 518         /*
 519          * Generate the IFH for frame injection
 520          *
 521          * The IFH is a 128bit-value
 522          * bit 127: bypass the analyzer processing
 523          * bit 57-67: destination mask
 524          * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
 525          * bit 20-27: cpu extraction queue mask
 526          * bit 16: tag type 0: C-tag, 1: S-tag
 527          * bit 0-11: VID
 528          */
 529         ifh[0] = IFH_INJ_BYPASS;
 530         ifh[1] = (0x07);
 531         ifh[2] = (0x7f) << 25;
 532         ifh[3] = (IFH_TAG_TYPE_C << 16);
 533
 534         return mscc_send(priv->regs[QS], serval_regs_qs,
 535                          ifh, IFH_LEN, buf, length);
 536 }
 537
 538 static int serval_recv(struct udevice *dev, int flags, uchar **packetp)
 539 {
 540         struct serval_private *priv = dev_get_priv(dev);
 541         u32 *rxbuf = (u32 *)net_rx_packets[0];
 542         int byte_cnt = 0;
 543
 544         byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
 545                              false);
 546
 547         *packetp = net_rx_packets[0];
 548
 549         return byte_cnt;
 550 }
 551
 552 static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
 553 {
 554         int i = 0;
 555
 556         for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
 557                 if (miim[i].miim_base == base && miim[i].miim_size == size)
 558                         return miim[i].bus;
 559
 560         return NULL;
 561 }
 562
 563 static void add_port_entry(struct serval_private *priv, size_t index,
 564                            size_t phy_addr, struct mii_dev *bus,
 565                            u8 serdes_index, u8 phy_mode)
 566 {
 567         priv->ports[index].phy_addr = phy_addr;
 568         priv->ports[index].bus = bus;
 569         priv->ports[index].serdes_index = serdes_index;
 570         priv->ports[index].phy_mode = phy_mode;
 571 }
 572
 573 static int serval_probe(struct udevice *dev)
 574 {
 575         struct serval_private *priv = dev_get_priv(dev);
 576         int i, ret;
 577         struct resource res;
 578         fdt32_t faddr;
 579         phys_addr_t addr_base;
 580         unsigned long addr_size;
 581         ofnode eth_node, node, mdio_node;
 582         size_t phy_addr;
 583         struct mii_dev *bus;
 584         struct ofnode_phandle_args phandle;
 585         struct phy_device *phy;
 586
 587         if (!priv)
 588                 return -EINVAL;
 589
 590         /* Get registers and map them to the private structure */
 591         for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
 592                 priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
 593                 if (!priv->regs[i]) {
 594                         debug
 595                             ("Error can't get regs base addresses for %s\n",
 596                              regs_names[i]);
 597                         return -ENOMEM;
 598                 }
 599         }
 600
 601         /* Initialize miim buses */
 602         memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
 603
 604         /* iterate all the ports and find out on which bus they are */
 605         i = 0;
 606         eth_node = dev_read_first_subnode(dev);
 607         for (node = ofnode_first_subnode(eth_node);
 608              ofnode_valid(node);
 609              node = ofnode_next_subnode(node)) {
 610                 if (ofnode_read_resource(node, 0, &res))
 611                         return -ENOMEM;
 612                 i = res.start;
 613
 614                 ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
 615                                                      0, 0, &phandle);
 616                 if (ret)
 617                         continue;
 618
 619                 /* Get phy address on mdio bus */
 620                 if (ofnode_read_resource(phandle.node, 0, &res))
 621                         return -ENOMEM;
 622                 phy_addr = res.start;
 623
 624                 /* Get mdio node */
 625                 mdio_node = ofnode_get_parent(phandle.node);
 626
 627                 if (ofnode_read_resource(mdio_node, 0, &res))
 628                         return -ENOMEM;
 629                 faddr = cpu_to_fdt32(res.start);
 630
 631                 addr_base = ofnode_translate_address(mdio_node, &faddr);
 632                 addr_size = res.end - res.start;
 633
 634                 /* If the bus is new then create a new bus */
 635                 if (!get_mdiobus(addr_base, addr_size))
 636                         priv->bus[miim_count] =
 637                                 serval_mdiobus_init(addr_base, addr_size);
 638
 639                 /* Connect mdio bus with the port */
 640                 bus = get_mdiobus(addr_base, addr_size);
 641
 642                 /* Get serdes info */
 643                 ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
 644                                                      3, 0, &phandle);
 645                 if (ret)
 646                         return -ENOMEM;
 647
 648                 add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
 649                                phandle.args[2]);
 650         }
 651
 652         for (i = 0; i < MAX_PORT; i++) {
 653                 if (!priv->ports[i].bus)
 654                         continue;
 655
 656                 phy = phy_connect(priv->ports[i].bus,
 657                                   priv->ports[i].phy_addr, dev,
 658                                   PHY_INTERFACE_MODE_NONE);
 659                 if (phy)
 660                         board_phy_config(phy);
 661         }
 662
 663         return 0;
 664 }
 665
 666 static int serval_remove(struct udevice *dev)
 667 {
 668         struct serval_private *priv = dev_get_priv(dev);
 669         int i;
 670
 671         for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
 672                 mdio_unregister(priv->bus[i]);
 673                 mdio_free(priv->bus[i]);
 674         }
 675
 676         return 0;
 677 }
 678
 679 static const struct eth_ops serval_ops = {
 680         .start        = serval_start,
 681         .stop         = serval_stop,
 682         .send         = serval_send,
 683         .recv         = serval_recv,
 684         .write_hwaddr = serval_write_hwaddr,
 685 };
 686
 687 static const struct udevice_id mscc_serval_ids[] = {
 688         {.compatible = "mscc,vsc7418-switch"},
 689         { /* Sentinel */ }
 690 };
 691
 692 U_BOOT_DRIVER(serval) = {
 693         .name                           = "serval-switch",
 694         .id                             = UCLASS_ETH,
 695         .of_match                       = mscc_serval_ids,
 696         .probe                          = serval_probe,
 697         .remove                         = serval_remove,
 698         .ops                            = &serval_ops,
 699         .priv_auto_alloc_size           = sizeof(struct serval_private),
 700         .platdata_auto_alloc_size       = sizeof(struct eth_pdata),
 701 };