1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
9 #include <dm/of_access.h>
10 #include <dm/of_addr.h>
11 #include <fdt_support.h>
13 #include <linux/ioport.h>
18 #include "mscc_miim.h"
19 #include "mscc_xfer.h"
20 #include "mscc_mac_table.h"
23 #define PHY_CFG_ENA 0xF
24 #define PHY_CFG_COMMON_RST BIT(4)
25 #define PHY_CFG_RST (0xF << 5)
27 #define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
29 #define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x))
30 #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
31 #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
32 #define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
33 #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
34 #define ANA_PGID(x) (0x8c00 + 4 * (x))
36 #define SYS_FRM_AGING 0x574
37 #define SYS_FRM_AGING_ENA BIT(20)
39 #define SYS_SYSTEM_RST_CFG 0x508
40 #define SYS_SYSTEM_RST_MEM_INIT BIT(0)
41 #define SYS_SYSTEM_RST_MEM_ENA BIT(1)
42 #define SYS_SYSTEM_RST_CORE_ENA BIT(2)
43 #define SYS_PORT_MODE(x) (0x514 + 0x4 * (x))
44 #define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3)
45 #define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
46 #define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1)
47 #define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
48 #define SYS_PAUSE_CFG(x) (0x608 + 0x4 * (x))
49 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
51 #define QSYS_SWITCH_PORT_MODE(x) (0x11234 + 0x4 * (x))
52 #define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
53 #define QSYS_QMAP 0x112d8
54 #define QSYS_EGR_NO_SHARING 0x1129c
57 #define DEV_CLOCK_CFG 0x0
58 #define DEV_CLOCK_CFG_LINK_SPEED_1000 1
59 #define DEV_MAC_ENA_CFG 0x1c
60 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
61 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
63 #define DEV_MAC_IFG_CFG 0x30
64 #define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
65 #define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
66 #define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
68 #define PCS1G_CFG 0x48
69 #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
70 #define PCS1G_MODE_CFG 0x4c
71 #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
72 #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
73 #define PCS1G_SD_CFG 0x50
74 #define PCS1G_ANEG_CFG 0x54
75 #define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
77 #define QS_XTR_GRP_CFG(x) (4 * (x))
78 #define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
79 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
80 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
81 #define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
82 #define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
83 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
85 #define IFH_INJ_BYPASS BIT(31)
86 #define IFH_TAG_TYPE_C 0
89 #define INTERNAL_PORT_MSK 0xF
92 #define PGID_BROADCAST 13
93 #define PGID_UNICAST 14
110 #define MAX_PORT (PORT3 - PORT0)
112 enum ocelot_mdio_target {
124 struct ocelot_private {
125 void __iomem *regs[TARGET_MAX];
126 struct mii_dev *bus[NUM_PHY];
129 static const unsigned long ocelot_regs_qs[] = {
130 [MSCC_QS_XTR_RD] = 0x8,
131 [MSCC_QS_XTR_FLUSH] = 0x18,
132 [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
133 [MSCC_QS_INJ_WR] = 0x2c,
134 [MSCC_QS_INJ_CTRL] = 0x34,
137 static const unsigned long ocelot_regs_ana_table[] = {
138 [MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
139 [MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
140 [MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
143 static struct mscc_miim_dev miim[NUM_PHY];
145 static void mscc_phy_reset(void)
147 writel(0, miim[INTERNAL].phy_regs + PHY_CFG);
148 writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
149 | PHY_CFG_ENA, miim[INTERNAL].phy_regs + PHY_CFG);
150 if (wait_for_bit_le32(miim[INTERNAL].phy_regs + PHY_STAT,
151 PHY_STAT_SUPERVISOR_COMPLETE,
152 true, 2000, false)) {
153 pr_err("Timeout in phy reset\n");
157 /* For now only setup the internal mdio bus */
158 static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
160 unsigned long phy_size[TARGET_MAX];
161 phys_addr_t phy_base[TARGET_MAX];
162 struct ofnode_phandle_args phandle;
163 ofnode eth_node, node, mdio_node;
174 /* gathered only the first mdio bus */
175 eth_node = dev_read_first_subnode(dev);
176 node = ofnode_first_subnode(eth_node);
177 ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
179 mdio_node = ofnode_get_parent(phandle.node);
181 for (i = 0; i < TARGET_MDIO_MAX; i++) {
182 if (ofnode_read_resource(mdio_node, i, &res)) {
183 pr_err("%s: get OF resource failed\n", __func__);
186 faddr = cpu_to_fdt32(res.start);
187 phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
188 phy_size[i] = res.end - res.start;
191 strcpy(bus->name, "miim-internal");
192 miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
193 miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
194 bus->priv = &miim[INTERNAL];
195 bus->read = mscc_miim_read;
196 bus->write = mscc_miim_write;
198 if (mdio_register(bus))
204 __weak void mscc_switch_reset(void)
208 static void ocelot_stop(struct udevice *dev)
214 static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
218 /* map the 8 CPU extraction queues to CPU port 11 */
219 writel(0, priv->regs[QSYS] + QSYS_QMAP);
221 for (i = 0; i <= 1; i++) {
223 * Do byte-swap and expect status after last data word
224 * Extraction: Mode: manual extraction) | Byte_swap
226 writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
227 priv->regs[QS] + QS_XTR_GRP_CFG(i));
229 * Injection: Mode: manual extraction | Byte_swap
231 writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
232 priv->regs[QS] + QS_INJ_GRP_CFG(i));
235 for (i = 0; i <= 1; i++)
236 /* Enable IFH insertion/parsing on CPU ports */
237 writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
238 SYS_PORT_MODE_INCL_XTR_HDR(1),
239 priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
241 * Setup the CPU port as VLAN aware to support switching frames
244 writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
245 MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
247 /* Disable learning (only RECV_ENA must be set) */
248 writel(ANA_PORT_PORT_CFG_RECV_ENA,
249 priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
251 /* Enable switching to/from cpu port */
252 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
253 QSYS_SWITCH_PORT_MODE_PORT_ENA);
255 /* No pause on CPU port - not needed (off by default) */
256 clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
257 SYS_PAUSE_CFG_PAUSE_ENA);
259 setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
262 static void ocelot_port_init(struct ocelot_private *priv, int port)
264 void __iomem *regs = priv->regs[port];
267 writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
269 /* Disable Signal Detect */
270 writel(0, regs + PCS1G_SD_CFG);
272 /* Enable MAC RX and TX */
273 writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
274 regs + DEV_MAC_ENA_CFG);
276 /* Clear sgmii_mode_ena */
277 writel(0, regs + PCS1G_MODE_CFG);
280 * Clear sw_resolve_ena(bit 0) and set adv_ability to
281 * something meaningful just in case
283 writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
285 /* Set MAC IFG Gaps */
286 writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
287 DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
289 /* Set link speed and release all resets */
290 writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
292 /* Make VLAN aware for CPU traffic */
293 writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
294 MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
296 /* Enable the port in the core */
297 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0),
298 QSYS_SWITCH_PORT_MODE_PORT_ENA);
301 static int ocelot_switch_init(struct ocelot_private *priv)
303 /* Reset switch & memories */
304 writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
305 priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
307 /* Wait to complete */
308 if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
309 SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
310 pr_err("Timeout in memory reset\n");
314 /* Enable switch core */
315 setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
316 SYS_SYSTEM_RST_CORE_ENA);
321 static int ocelot_initialize(struct ocelot_private *priv)
325 /* Initialize switch memories, enable core */
326 ret = ocelot_switch_init(priv);
330 * Disable port-to-port by switching
331 * Put fron ports in "port isolation modes" - i.e. they cant send
332 * to other ports - via the PGID sorce masks.
334 for (i = 0; i <= MAX_PORT; i++)
335 writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
338 mscc_flush(priv->regs[QS], ocelot_regs_qs);
340 /* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
341 writel(SYS_FRM_AGING_ENA | (20000000 / 65),
342 priv->regs[SYS] + SYS_FRM_AGING);
344 for (i = PORT0; i <= PORT3; i++)
345 ocelot_port_init(priv, i);
347 ocelot_cpu_capture_setup(priv);
349 debug("Ports enabled\n");
354 static int ocelot_write_hwaddr(struct udevice *dev)
356 struct ocelot_private *priv = dev_get_priv(dev);
357 struct eth_pdata *pdata = dev_get_platdata(dev);
359 mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
360 pdata->enetaddr, PGID_UNICAST);
362 writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
367 static int ocelot_start(struct udevice *dev)
369 struct ocelot_private *priv = dev_get_priv(dev);
370 struct eth_pdata *pdata = dev_get_platdata(dev);
371 const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
375 ret = ocelot_initialize(priv);
379 /* Set MAC address tables entries for CPU redirection */
380 mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
383 writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
384 priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
386 /* It should be setup latter in ocelot_write_hwaddr */
387 mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
388 pdata->enetaddr, PGID_UNICAST);
390 writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
395 static int ocelot_send(struct udevice *dev, void *packet, int length)
397 struct ocelot_private *priv = dev_get_priv(dev);
399 int port = BIT(0); /* use port 0 */
403 * Generate the IFH for frame injection
405 * The IFH is a 128bit-value
406 * bit 127: bypass the analyzer processing
407 * bit 56-67: destination mask
408 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
409 * bit 20-27: cpu extraction queue mask
410 * bit 16: tag type 0: C-tag, 1: S-tag
413 ifh[0] = IFH_INJ_BYPASS;
414 ifh[1] = (0xf00 & port) >> 8;
415 ifh[2] = (0xff & port) << 24;
416 ifh[3] = (IFH_TAG_TYPE_C << 16);
418 return mscc_send(priv->regs[QS], ocelot_regs_qs,
419 ifh, IFH_LEN, buf, length);
422 static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
424 struct ocelot_private *priv = dev_get_priv(dev);
425 u32 *rxbuf = (u32 *)net_rx_packets[0];
428 byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
431 *packetp = net_rx_packets[0];
436 static int ocelot_probe(struct udevice *dev)
438 struct ocelot_private *priv = dev_get_priv(dev);
442 enum ocelot_target id;
457 for (i = 0; i < ARRAY_SIZE(reg); i++) {
458 priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
459 if (!priv->regs[reg[i].id]) {
461 ("Error %d: can't get regs base addresses for %s\n",
467 priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
470 for (i = 0; i < 4; i++) {
471 phy_connect(priv->bus[INTERNAL], i, dev,
472 PHY_INTERFACE_MODE_NONE);
478 static int ocelot_remove(struct udevice *dev)
480 struct ocelot_private *priv = dev_get_priv(dev);
483 for (i = 0; i < NUM_PHY; i++) {
484 mdio_unregister(priv->bus[i]);
485 mdio_free(priv->bus[i]);
491 static const struct eth_ops ocelot_ops = {
492 .start = ocelot_start,
496 .write_hwaddr = ocelot_write_hwaddr,
499 static const struct udevice_id mscc_ocelot_ids[] = {
500 {.compatible = "mscc,vsc7514-switch"},
504 U_BOOT_DRIVER(ocelot) = {
505 .name = "ocelot-switch",
507 .of_match = mscc_ocelot_ids,
508 .probe = ocelot_probe,
509 .remove = ocelot_remove,
511 .priv_auto_alloc_size = sizeof(struct ocelot_private),
512 .platdata_auto_alloc_size = sizeof(struct eth_pdata),