1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #include <asm/cpm_8xx.h>
14 #include <asm/global_data.h>
16 #include <linux/delay.h>
19 #include <linux/mii.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* define WANT_MII when MII support is required */
24 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
33 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
34 #error "CONFIG_MII has to be defined!"
39 #if defined(CONFIG_RMII) && !defined(WANT_MII)
40 #error RMII support is unusable without a working PHY.
43 #ifdef CONFIG_SYS_DISCOVER_PHY
44 static int mii_discover_phy(struct udevice *dev);
47 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
48 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
51 static struct ether_fcc_info_s
60 #if defined(CONFIG_ETHER_ON_FEC1)
63 offsetof(immap_t, im_cpm.cp_fec1),
70 #if defined(CONFIG_ETHER_ON_FEC2)
73 offsetof(immap_t, im_cpm.cp_fec2),
81 /* Ethernet Transmit and Receive Buffers */
82 #define DBUF_LENGTH 1520
88 #define PKT_MAXBUF_SIZE 1518
89 #define PKT_MINBUF_SIZE 64
90 #define PKT_MAXBLR_SIZE 1520
93 static char txbuf[DBUF_LENGTH] __aligned(8);
95 #error txbuf must be aligned.
98 static uint rxIdx; /* index of the current RX buffer */
99 static uint txIdx; /* index of the current TX buffer */
102 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
103 * immr->udata_bd address on Dual-Port RAM
104 * Provide for Double Buffering
107 struct common_buf_desc {
108 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
109 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
112 static struct common_buf_desc __iomem *rtx;
114 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
115 static void __mii_init(void);
118 static int fec_probe(struct udevice *dev)
120 struct ether_fcc_info_s *efis = dev_get_priv(dev);
121 int index = dev_get_driver_data(dev);
124 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
125 if (ether_fcc_info[i].ether_index != index)
128 memcpy(efis, ðer_fcc_info[i], sizeof(*efis));
130 efis->actual_phy_addr = -1;
132 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
134 struct mii_dev *mdiodev = mdio_alloc();
137 strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
138 mdiodev->read = fec8xx_miiphy_read;
139 mdiodev->write = fec8xx_miiphy_write;
141 retval = mdio_register(mdiodev);
149 static int fec_send(struct udevice *dev, void *packet, int length)
152 struct ether_fcc_info_s *efis = dev_get_priv(dev);
153 fec_t __iomem *fecp =
154 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
160 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
166 printf("TX not ready\n");
168 out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
169 out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
170 setbits_be16(&rtx->txbd[txIdx].cbd_sc,
171 BD_ENET_TX_READY | BD_ENET_TX_LAST);
173 /* Activate transmit Buffer Descriptor polling */
174 /* Descriptor polling active */
175 out_be32(&fecp->fec_x_des_active, 0x01000000);
178 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
184 printf("TX timeout\n");
186 /* return only status bits */;
187 rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
189 txIdx = (txIdx + 1) % TX_BUF_CNT;
194 static int fec_recv(struct udevice *dev, int flags, uchar **packetp)
198 /* section 16.9.23.2 */
199 if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY)
202 length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
204 if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
205 uchar *rx = net_rx_packets[rxIdx];
207 #if defined(CONFIG_CMD_CDP)
208 if ((rx[0] & 1) != 0 &&
209 memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
210 !is_cdp_packet((uchar *)rx))
221 static int fec_free_pkt(struct udevice *dev, uchar *packet, int length)
223 struct ether_fcc_info_s *efis = dev_get_priv(dev);
224 fec_t __iomem *fecp =
225 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
227 /* Give the buffer back to the FEC. */
228 out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
230 /* wrap around buffer index when necessary */
231 if ((rxIdx + 1) >= PKTBUFSRX) {
232 out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
233 BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
236 out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
240 /* Try to fill Buffer Descriptors */
241 /* Descriptor polling active */
242 out_be32(&fecp->fec_r_des_active, 0x01000000);
247 /**************************************************************
249 * FEC Ethernet Initialization Routine
251 *************************************************************/
253 #define FEC_ECNTRL_PINMUX 0x00000004
254 #define FEC_ECNTRL_ETHER_EN 0x00000002
255 #define FEC_ECNTRL_RESET 0x00000001
257 #define FEC_RCNTRL_BC_REJ 0x00000010
258 #define FEC_RCNTRL_PROM 0x00000008
259 #define FEC_RCNTRL_MII_MODE 0x00000004
260 #define FEC_RCNTRL_DRT 0x00000002
261 #define FEC_RCNTRL_LOOP 0x00000001
263 #define FEC_TCNTRL_FDEN 0x00000004
264 #define FEC_TCNTRL_HBC 0x00000002
265 #define FEC_TCNTRL_GTS 0x00000001
267 #define FEC_RESET_DELAY 50
269 #if defined(CONFIG_RMII)
271 static inline void fec_10Mbps(struct udevice *dev)
273 struct ether_fcc_info_s *efis = dev_get_priv(dev);
274 int fecidx = efis->ether_index;
275 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
276 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
278 if ((unsigned int)fecidx >= 2)
281 setbits_be32(&immr->im_cpm.cp_cptr, mask);
284 static inline void fec_100Mbps(struct udevice *dev)
286 struct ether_fcc_info_s *efis = dev_get_priv(dev);
287 int fecidx = efis->ether_index;
288 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
289 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
291 if ((unsigned int)fecidx >= 2)
294 clrbits_be32(&immr->im_cpm.cp_cptr, mask);
299 static inline void fec_full_duplex(struct udevice *dev)
301 struct ether_fcc_info_s *efis = dev_get_priv(dev);
302 fec_t __iomem *fecp =
303 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
305 clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
306 setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
309 static inline void fec_half_duplex(struct udevice *dev)
311 struct ether_fcc_info_s *efis = dev_get_priv(dev);
312 fec_t __iomem *fecp =
313 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
315 setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
316 clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
319 static void fec_pin_init(int fecidx)
321 struct bd_info *bd = gd->bd;
322 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
325 * Set MII speed to 2.5 MHz or slightly below.
327 * According to the MPC860T (Rev. D) Fast ethernet controller user
329 * the MII management interface clock must be less than or equal
331 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
332 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
334 * All MII configuration is done via FEC1 registers:
336 out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
337 ((bd->bi_intfreq + 4999999) / 5000000) << 1);
339 #if defined(CONFIG_MPC885) && defined(WANT_MII)
340 /* use MDC for MII */
341 setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
342 clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
346 #if defined(CONFIG_ETHER_ON_FEC1)
348 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
350 #if !defined(CONFIG_RMII)
352 setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
353 setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
354 clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
356 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
357 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
359 setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
360 clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
362 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
363 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
364 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
366 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
370 #if !defined(CONFIG_FEC1_PHY_NORXERR)
371 setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
372 clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
374 setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
375 setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
376 clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
378 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
379 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
381 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
382 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
384 #endif /* !CONFIG_RMII */
388 * Configure all of port D for MII.
390 out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
391 out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
393 #if defined(CONFIG_TARGET_MCR3000)
394 out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
395 out_be16(&immr->im_ioport.iop_padir, 0x04F0);
396 out_be16(&immr->im_ioport.iop_paodr, 0x0000);
398 out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
399 out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
400 out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
402 out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
403 out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
404 out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
405 out_be16(&immr->im_ioport.iop_pcint, 0x0000);
407 out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
408 out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
410 setbits_be32(&immr->im_ioport.utmode, 0x80);
414 #endif /* CONFIG_ETHER_ON_FEC1 */
415 } else if (fecidx == 1) {
416 #if defined(CONFIG_ETHER_ON_FEC2)
418 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
420 #if !defined(CONFIG_RMII)
421 setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
422 setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
423 clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
424 setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
426 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
429 #if !defined(CONFIG_FEC2_PHY_NORXERR)
430 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
431 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
432 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
434 setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
435 setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
436 setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
437 clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
439 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
440 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
441 #endif /* CONFIG_RMII */
443 #endif /* CONFIG_MPC885 */
445 #endif /* CONFIG_ETHER_ON_FEC2 */
449 static int fec_reset(fec_t __iomem *fecp)
454 * A delay is required between a reset of the FEC block and
455 * initialization of other FEC registers because the reset takes
456 * some time to complete. If you don't delay, subsequent writes
457 * to FEC registers might get killed by the reset routine which is
461 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
462 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
463 (i < FEC_RESET_DELAY); ++i)
466 if (i == FEC_RESET_DELAY)
472 static int fec_start(struct udevice *dev)
474 struct eth_pdata *plat = dev_get_plat(dev);
475 struct ether_fcc_info_s *efis = dev_get_priv(dev);
476 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
477 fec_t __iomem *fecp =
478 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
481 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
482 /* the MII interface is connected to FEC1
483 * so for the miiphy_xxx function to work we must
484 * call mii_init since fec_halt messes the thing up
486 if (efis->ether_index != 0)
490 if (fec_reset(fecp) < 0)
491 printf("FEC_RESET_DELAY timeout\n");
493 /* We use strictly polling mode only
495 out_be32(&fecp->fec_imask, 0);
497 /* Clear any pending interrupt
499 out_be32(&fecp->fec_ievent, 0xffc0);
501 /* No need to set the IVEC register */
503 /* Set station address
505 #define ea plat->enetaddr
506 out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
507 (ea[2] << 8) | ea[3]);
508 out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
511 #if defined(CONFIG_CMD_CDP)
513 * Turn on multicast address hash table
515 out_be32(&fecp->fec_hash_table_high, 0xffffffff);
516 out_be32(&fecp->fec_hash_table_low, 0xffffffff);
518 /* Clear multicast address hash table
520 out_be32(&fecp->fec_hash_table_high, 0);
521 out_be32(&fecp->fec_hash_table_low, 0);
524 /* Set maximum receive buffer size.
526 out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
528 /* Set maximum frame length
530 out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
533 * Setup Buffers and Buffer Descriptors
539 rtx = (struct common_buf_desc __iomem *)
540 (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
542 * Setup Receiver Buffer Descriptors (13.14.24.18)
546 for (i = 0; i < PKTBUFSRX; i++) {
547 out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
548 out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
549 out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
551 setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
554 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
558 for (i = 0; i < TX_BUF_CNT; i++) {
559 out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
560 out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
561 out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
563 setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
565 /* Set receive and transmit descriptor base
567 out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
568 out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
572 /* Half duplex mode */
573 out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
574 out_be32(&fecp->fec_x_cntrl, 0);
576 /* Enable big endian and don't care about SDMA FC.
578 out_be32(&fecp->fec_fun_code, 0x78000000);
581 * Setup the pin configuration of the FEC
583 fec_pin_init(efis->ether_index);
589 * Now enable the transmit and receive processing
591 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
593 if (efis->phy_addr == -1) {
594 #ifdef CONFIG_SYS_DISCOVER_PHY
596 * wait for the PHY to wake up after reset
598 efis->actual_phy_addr = mii_discover_phy(dev);
600 if (efis->actual_phy_addr == -1) {
601 printf("Unable to discover phy!\n");
605 efis->actual_phy_addr = -1;
608 efis->actual_phy_addr = efis->phy_addr;
611 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
613 * adapt the RMII speed to the speed of the phy
615 if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
621 #if defined(CONFIG_MII)
623 * adapt to the half/full speed settings
625 if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
626 fec_full_duplex(dev);
628 fec_half_duplex(dev);
631 /* And last, try to fill Rx Buffer Descriptors */
632 /* Descriptor polling active */
633 out_be32(&fecp->fec_r_des_active, 0x01000000);
635 efis->initialized = 1;
641 static void fec_stop(struct udevice *dev)
643 struct ether_fcc_info_s *efis = dev_get_priv(dev);
644 fec_t __iomem *fecp =
645 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
648 /* avoid halt if initialized; mii gets stuck otherwise */
649 if (!efis->initialized)
653 * A delay is required between a reset of the FEC block and
654 * initialization of other FEC registers because the reset takes
655 * some time to complete. If you don't delay, subsequent writes
656 * to FEC registers might get killed by the reset routine which is
660 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
661 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
662 (i < FEC_RESET_DELAY); ++i)
665 if (i == FEC_RESET_DELAY) {
666 printf("FEC_RESET_DELAY timeout\n");
670 efis->initialized = 0;
673 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
675 /* Make MII read/write commands for the FEC.
678 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
681 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
682 (REG & 0x1f) << 18) | \
685 /* Interrupt events/masks.
687 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
688 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
689 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
690 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
691 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
692 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
693 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
694 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
695 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
696 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
698 /* send command to phy using mii, wait for result */
700 mii_send(uint mii_cmd)
705 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
707 ep = &immr->im_cpm.cp_fec;
709 out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
711 /* wait for mii complete */
713 while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
715 printf("mii_send STUCK!\n");
719 mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
720 out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
721 return mii_reply & 0xffff; /* data read from phy */
725 #if defined(CONFIG_SYS_DISCOVER_PHY)
726 static int mii_discover_phy(struct udevice *dev)
728 #define MAX_PHY_PASSES 11
734 phyaddr = -1; /* didn't find a PHY yet */
735 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
737 /* PHY may need more time to recover from reset.
738 * The LXT970 needs 50ms typical, no maximum is
739 * specified, so wait 10ms before try again.
740 * With 11 passes this gives it 100ms to wake up.
742 udelay(10000); /* wait 10ms */
744 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
745 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
746 if (phytype != 0xffff) {
748 phytype |= mii_send(mk_mii_read(phyno,
754 printf("No PHY device found.\n");
758 #endif /* CONFIG_SYS_DISCOVER_PHY */
760 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
762 /****************************************************************************
763 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
764 * This function is a subset of eth_init
765 ****************************************************************************
767 static void __mii_init(void)
769 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
770 fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
772 if (fec_reset(fecp) < 0)
773 printf("FEC_RESET_DELAY timeout\n");
775 /* We use strictly polling mode only
777 out_be32(&fecp->fec_imask, 0);
779 /* Clear any pending interrupt
781 out_be32(&fecp->fec_ievent, 0xffc0);
783 /* Now enable the transmit and receive processing
785 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
794 /* Setup the pin configuration of the FEC(s)
796 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
797 fec_pin_init(ether_fcc_info[i].ether_index);
800 /*****************************************************************************
801 * Read and write a MII PHY register, routines used by MII Utilities
803 * FIXME: These routines are expected to return 0 on success, but mii_send
804 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
805 * no PHY connected...
806 * For now always return 0.
807 * FIXME: These routines only work after calling eth_init() at least once!
808 * Otherwise they hang in mii_send() !!! Sorry!
809 *****************************************************************************/
811 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
813 unsigned short value = 0;
814 short rdreg; /* register working value */
816 rdreg = mii_send(mk_mii_read(addr, reg));
822 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
825 (void)mii_send(mk_mii_write(addr, reg, value));
831 static const struct eth_ops fec_ops = {
836 .free_pkt = fec_free_pkt,
839 static const struct udevice_id fec_ids[] = {
840 #ifdef CONFIG_ETHER_ON_FEC1
842 .compatible = "fsl,pq1-fec1",
846 #ifdef CONFIG_ETHER_ON_FEC2
848 .compatible = "fsl,pq1-fec2",
855 U_BOOT_DRIVER(fec) = {
861 .priv_auto = sizeof(struct ether_fcc_info_s),
862 .plat_auto = sizeof(struct eth_pdata),