2 * (C) Copyright 2003-2009
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from the MPC8xx FEC driver.
6 * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
16 #include "mpc512x_fec.h"
18 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
23 defined(CONFIG_MPC512x_FEC)
25 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
26 #error "CONFIG_MII has to be defined!"
30 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
33 int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
34 int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
35 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
37 static uchar rx_buff[FEC_BUFFER_SIZE];
38 static int rx_buff_idx = 0;
40 /********************************************************************/
42 static void mpc512x_fec_phydump (char *devname)
45 uint8 phyAddr = CONFIG_PHY_ADDR;
47 /* regs to print: 0...8, 21,27,31 */
48 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
49 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
52 for (i = 0; i < 32; i++) {
54 miiphy_read (devname, phyAddr, i, &phyStatus);
55 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
61 /********************************************************************/
62 static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
69 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
70 fec->bdBase->rbd[ix].dataPointer =
71 (uint32)&fec->bdBase->recv_frames[ix];
72 fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
73 fec->bdBase->rbd[ix].dataLength = 0;
77 * have the last RBD to close the ring
79 fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
85 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
86 fec->bdBase->tbd[ix].status = 0;
90 * Have the last TBD to close the ring
92 fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
95 * Initialize some indices
98 fec->usedTbdIndex = 0;
99 fec->cleanTbdNum = FEC_TBD_NUM;
104 /********************************************************************/
105 static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
108 * Reset buffer descriptor as empty
110 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
111 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
113 pRbd->status = FEC_RBD_EMPTY;
115 pRbd->dataLength = 0;
120 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
123 * Now, we have an empty RxBD, notify FEC
124 * Set Descriptor polling active
126 out_be32(&fec->eth->r_des_active, 0x01000000);
129 /********************************************************************/
130 static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
132 volatile FEC_TBD *pUsedTbd;
135 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
136 fec->cleanTbdNum, fec->usedTbdIndex);
140 * process all the consumed TBDs
142 while (fec->cleanTbdNum < FEC_TBD_NUM) {
143 pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
144 if (pUsedTbd->status & FEC_TBD_READY) {
146 printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
152 * clean this buffer descriptor
154 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
155 pUsedTbd->status = FEC_TBD_WRAP;
157 pUsedTbd->status = 0;
160 * update some indeces for a correct handling of the TBD ring
163 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
167 /********************************************************************/
168 static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
170 uint8 currByte; /* byte for which to compute the CRC */
171 int byte; /* loop - counter */
172 int bit; /* loop - counter */
173 uint32 crc = 0xffffffff; /* initial value */
176 * The algorithm used is the following:
177 * we loop on each of the six bytes of the provided address,
178 * and we compute the CRC by left-shifting the previous
179 * value by one position, so that each bit in the current
180 * byte of the address may contribute the calculation. If
181 * the latter and the MSB in the CRC are different, then
182 * the CRC value so computed is also ex-ored with the
183 * "polynomium generator". The current byte of the address
184 * is also shifted right by one bit at each iteration.
185 * This is because the CRC generatore in hardware is implemented
186 * as a shift-register with as many ex-ores as the radixes
187 * in the polynomium. This suggests that we represent the
188 * polynomiumm itself as a 32-bit constant.
190 for (byte = 0; byte < 6; byte++) {
191 currByte = mac[byte];
192 for (bit = 0; bit < 8; bit++) {
193 if ((currByte & 0x01) ^ (crc & 0x01)) {
195 crc = crc ^ 0xedb88320;
206 * Set individual hash table register
209 out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
210 out_be32(&fec->eth->iaddr2, 0);
212 out_be32(&fec->eth->iaddr1, 0);
213 out_be32(&fec->eth->iaddr2, (1 << crc));
217 * Set physical address
219 out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
220 (mac[2] << 8) + mac[3]);
221 out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
225 /********************************************************************/
226 static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
228 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
231 printf ("mpc512x_fec_init... Begin\n");
234 /* Set interrupt mask register */
235 out_be32(&fec->eth->imask, 0x00000000);
237 /* Clear FEC-Lite interrupt event register(IEVENT) */
238 out_be32(&fec->eth->ievent, 0xffffffff);
240 /* Set transmit fifo watermark register(X_WMRK), default = 64 */
241 out_be32(&fec->eth->x_wmrk, 0x0);
243 /* Set Opcode/Pause Duration Register */
244 out_be32(&fec->eth->op_pause, 0x00010020);
246 /* Frame length=1522; MII mode */
247 out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
249 /* Half-duplex, heartbeat disabled */
250 out_be32(&fec->eth->x_cntrl, 0x00000000);
252 /* Enable MIB counters */
253 out_be32(&fec->eth->mib_control, 0x0);
255 /* Setup recv fifo start and buff size */
256 out_be32(&fec->eth->r_fstart, 0x500);
257 out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
259 /* Setup BD base addresses */
260 out_be32(&fec->eth->r_des_start, (uint32)fec->bdBase->rbd);
261 out_be32(&fec->eth->x_des_start, (uint32)fec->bdBase->tbd);
264 out_be32(&fec->eth->dma_control, 0xc0000000);
267 setbits_be32(&fec->eth->ecntrl, 0x00000006);
269 /* Initilize addresses and status words of BDs */
270 mpc512x_fec_bd_init (fec);
272 /* Descriptor polling active */
273 out_be32(&fec->eth->r_des_active, 0x01000000);
276 printf("mpc512x_fec_init... Done \n");
281 /********************************************************************/
282 int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
284 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
285 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
290 printf ("mpc512x_fec_init_phy... Begin\n");
294 * Clear FEC-Lite interrupt event register(IEVENT)
296 out_be32(&fec->eth->ievent, 0xffffffff);
299 * Set interrupt mask register
301 out_be32(&fec->eth->imask, 0x00000000);
303 if (fec->xcv_type != SEVENWIRE) {
305 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
306 * and do not drop the Preamble.
308 out_be32(&fec->eth->mii_speed,
309 (((gd->ips_clk / 1000000) / 5) + 1) << 1);
312 * Reset PHY, then delay 300ns
314 miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
317 if (fec->xcv_type == MII10) {
319 * Force 10Base-T, FDX operation
322 printf ("Forcing 10 Mbps ethernet link... ");
324 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
326 miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
329 do { /* wait for link status to go down */
331 if ((timeout--) == 0) {
333 printf ("hmmm, should not have waited...");
337 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
341 } while ((phyStatus & 0x0004)); /* !link up */
344 do { /* wait for link status to come back up */
346 if ((timeout--) == 0) {
347 printf ("failed. Link is down.\n");
350 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
354 } while (!(phyStatus & 0x0004)); /* !link up */
359 } else { /* MII100 */
361 * Set the auto-negotiation advertisement register bits
363 miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
366 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
368 miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
371 * Wait for AN completion
377 if ((timeout--) == 0) {
379 printf ("PHY auto neg 0 failed...\n");
384 if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
386 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
390 } while (!(phyStatus & 0x0004));
393 printf ("PHY auto neg complete! \n");
399 if (fec->xcv_type != SEVENWIRE)
400 mpc512x_fec_phydump (dev->name);
404 printf ("mpc512x_fec_init_phy... Done \n");
409 /********************************************************************/
410 static void mpc512x_fec_halt (struct eth_device *dev)
412 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
413 int counter = 0xffff;
416 if (fec->xcv_type != SEVENWIRE)
417 mpc512x_fec_phydump (dev->name);
421 * mask FEC chip interrupts
423 out_be32(&fec->eth->imask, 0);
426 * issue graceful stop command to the FEC transmitter if necessary
428 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
431 * wait for graceful stop to register
433 while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
437 * Disable the Ethernet Controller
439 clrbits_be32(&fec->eth->ecntrl, 0x00000002);
442 * Issue a reset command to the FEC chip
444 setbits_be32(&fec->eth->ecntrl, 0x1);
447 * wait at least 16 clock cycles
451 printf ("Ethernet task stopped\n");
455 /********************************************************************/
457 static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
461 * This routine transmits one frame. This routine only accepts
462 * 6-byte Ethernet addresses.
464 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
465 volatile FEC_TBD *pTbd;
468 printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
472 * Clear Tx BD ring at first
474 mpc512x_fec_tbd_scrub (fec);
477 * Check for valid length of data.
479 if ((data_length > 1500) || (data_length <= 0)) {
484 * Check the number of vacant TxBDs.
486 if (fec->cleanTbdNum < 1) {
488 printf ("No available TxBDs ...\n");
494 * Get the first TxBD to send the mac header
496 pTbd = &fec->bdBase->tbd[fec->tbdIndex];
497 pTbd->dataLength = data_length;
498 pTbd->dataPointer = (uint32)eth_data;
499 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
500 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
502 /* Activate transmit Buffer Descriptor polling */
503 out_be32(&fec->eth->x_des_active, 0x01000000);
509 fec->cleanTbdNum -= 1;
512 * wait until frame is sent .
514 while (pTbd->status & FEC_TBD_READY) {
517 printf ("TDB status = %04x\n", pTbd->status);
525 /********************************************************************/
526 static int mpc512x_fec_recv (struct eth_device *dev)
529 * This command pulls one frame from the card
531 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
532 volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
533 unsigned long ievent;
534 int frame_length = 0;
537 printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
544 * Check if any critical events have happened
546 ievent = in_be32(&fec->eth->ievent);
547 out_be32(&fec->eth->ievent, ievent);
548 if (ievent & 0x20060000) {
549 /* BABT, Rx/Tx FIFO errors */
550 mpc512x_fec_halt (dev);
551 mpc512x_fec_init (dev, NULL);
554 if (ievent & 0x80000000) {
555 /* Heartbeat error */
556 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
558 if (ievent & 0x10000000) {
559 /* Graceful stop complete */
560 if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
561 mpc512x_fec_halt (dev);
562 clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
563 mpc512x_fec_init (dev, NULL);
567 if (!(pRbd->status & FEC_RBD_EMPTY)) {
568 if (!(pRbd->status & FEC_RBD_ERR) &&
569 ((pRbd->dataLength - 4) > 14)) {
574 if (pRbd->status & FEC_RBD_LAST)
575 frame_length = pRbd->dataLength - 4;
577 frame_length = pRbd->dataLength;
581 printf ("recv data length 0x%08x data hdr: ",
583 for (i = 0; i < 14; i++)
584 printf ("%x ", *((uint8*)pRbd->dataPointer + i));
589 * Fill the buffer and pass it to upper layers
591 memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
592 frame_length - rx_buff_idx);
593 rx_buff_idx = frame_length;
595 if (pRbd->status & FEC_RBD_LAST) {
596 NetReceive ((uchar*)rx_buff, frame_length);
602 * Reset buffer descriptor as empty
604 mpc512x_fec_rbd_clean (fec, pRbd);
607 /* Try to fill Buffer Descriptors */
608 out_be32(&fec->eth->r_des_active, 0x01000000);
613 /********************************************************************/
614 int mpc512x_fec_initialize (bd_t * bis)
616 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
617 mpc512x_fec_priv *fec;
618 struct eth_device *dev;
620 char *tmp, *end, env_enetaddr[6];
623 fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
624 dev = (struct eth_device *) malloc (sizeof(*dev));
625 memset (dev, 0, sizeof *dev);
629 # ifndef CONFIG_FEC_10MBIT
630 fec->xcv_type = MII100;
632 fec->xcv_type = MII10;
634 dev->priv = (void *)fec;
635 dev->iobase = (int)&im->fec;
636 dev->init = mpc512x_fec_init;
637 dev->halt = mpc512x_fec_halt;
638 dev->send = mpc512x_fec_send;
639 dev->recv = mpc512x_fec_recv;
641 sprintf (dev->name, "FEC ETHERNET");
644 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
645 miiphy_register (dev->name,
646 fec512x_miiphy_read, fec512x_miiphy_write);
649 /* Clean up space FEC's MIB and FIFO RAM ...*/
650 memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
653 * Malloc space for BDs (must be quad word-aligned)
654 * this pointer is lost, so cannot be freed
656 bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
657 fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
658 memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
661 * Set interrupt mask register
663 out_be32(&fec->eth->imask, 0x00000000);
666 * Clear FEC-Lite interrupt event register(IEVENT)
668 out_be32(&fec->eth->ievent, 0xffffffff);
671 * Try to set the mac address now. The fec mac address is
672 * a garbage after reset. When not using fec for booting
673 * the Linux fec driver will try to work with this garbage.
675 tmp = getenv ("ethaddr");
677 for (i=0; i<6; i++) {
678 env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0;
680 tmp = (*end) ? end+1 : end;
682 mpc512x_fec_set_hwaddr (fec, env_enetaddr);
683 out_be32(&fec->eth->gaddr1, 0x00000000);
684 out_be32(&fec->eth->gaddr2, 0x00000000);
687 mpc512x_fec_init_phy (dev, bis);
692 /* MII-interface related functions */
693 /********************************************************************/
694 int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
696 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
697 volatile fec512x_t *eth = &im->fec;
698 uint32 reg; /* convenient holder for the PHY register */
699 uint32 phy; /* convenient holder for the PHY */
700 int timeout = 0xffff;
703 * reading from any PHY's register is done by properly
704 * programming the FEC's MII data register.
706 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
707 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
709 out_be32(ð->mii_data, FEC_MII_DATA_ST |
715 * wait for the related interrupt
717 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
722 printf ("Read MDIO failed...\n");
728 * clear mii interrupt bit
730 out_be32(ð->ievent, 0x00800000);
733 * it's now safe to read the PHY's register
735 *retVal = (uint16) in_be32(ð->mii_data);
740 /********************************************************************/
741 int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
743 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
744 volatile fec512x_t *eth = &im->fec;
745 uint32 reg; /* convenient holder for the PHY register */
746 uint32 phy; /* convenient holder for the PHY */
747 int timeout = 0xffff;
749 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
750 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
752 out_be32(ð->mii_data, FEC_MII_DATA_ST |
758 * wait for the MII interrupt
760 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
765 printf ("Write MDIO failed...\n");
771 * clear MII interrupt bit
773 out_be32(ð->ievent, 0x00800000);
779 static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
783 unsigned int crc, count;
789 * crc = 0xffffffff; * The initialized value should be 0xffffffff
793 for (i = len; --i >= 0;) {
795 for (count = 0; count < 8; count++) {
796 if ((c & 0x01) ^ (crc & 0x01)) {
798 crc = crc ^ 0xedb88320;
807 * In big endian system, do byte swaping for crc value
813 #endif /* CONFIG_MPC512x_FEC */