2 * (C) Copyright 2003-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from the MPC8xx FEC driver.
6 * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
15 #include "mpc512x_fec.h"
17 DECLARE_GLOBAL_DATA_PTR;
21 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
22 defined(CONFIG_MPC512x_FEC)
24 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
25 #error "CONFIG_MII has to be defined!"
28 int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
29 int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data);
30 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
32 static uchar rx_buff[FEC_BUFFER_SIZE];
33 static int rx_buff_idx = 0;
35 /********************************************************************/
37 static void mpc512x_fec_phydump (char *devname)
40 u8 phyAddr = CONFIG_PHY_ADDR;
42 /* regs to print: 0...8, 21,27,31 */
43 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
44 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
47 for (i = 0; i < 32; i++) {
49 miiphy_read (devname, phyAddr, i, &phyStatus);
50 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
56 /********************************************************************/
57 static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
64 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
65 fec->bdBase->rbd[ix].dataPointer =
66 (u32)&fec->bdBase->recv_frames[ix];
67 fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
68 fec->bdBase->rbd[ix].dataLength = 0;
72 * have the last RBD to close the ring
74 fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
80 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
81 fec->bdBase->tbd[ix].status = 0;
85 * Have the last TBD to close the ring
87 fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
90 * Initialize some indices
93 fec->usedTbdIndex = 0;
94 fec->cleanTbdNum = FEC_TBD_NUM;
99 /********************************************************************/
100 static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
103 * Reset buffer descriptor as empty
105 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
106 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
108 pRbd->status = FEC_RBD_EMPTY;
110 pRbd->dataLength = 0;
115 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
118 * Now, we have an empty RxBD, notify FEC
119 * Set Descriptor polling active
121 out_be32(&fec->eth->r_des_active, 0x01000000);
124 /********************************************************************/
125 static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
127 volatile FEC_TBD *pUsedTbd;
130 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
131 fec->cleanTbdNum, fec->usedTbdIndex);
135 * process all the consumed TBDs
137 while (fec->cleanTbdNum < FEC_TBD_NUM) {
138 pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
139 if (pUsedTbd->status & FEC_TBD_READY) {
141 printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
147 * clean this buffer descriptor
149 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
150 pUsedTbd->status = FEC_TBD_WRAP;
152 pUsedTbd->status = 0;
155 * update some indeces for a correct handling of the TBD ring
158 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
162 /********************************************************************/
163 static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
165 u8 currByte; /* byte for which to compute the CRC */
166 int byte; /* loop - counter */
167 int bit; /* loop - counter */
168 u32 crc = 0xffffffff; /* initial value */
171 * The algorithm used is the following:
172 * we loop on each of the six bytes of the provided address,
173 * and we compute the CRC by left-shifting the previous
174 * value by one position, so that each bit in the current
175 * byte of the address may contribute the calculation. If
176 * the latter and the MSB in the CRC are different, then
177 * the CRC value so computed is also ex-ored with the
178 * "polynomium generator". The current byte of the address
179 * is also shifted right by one bit at each iteration.
180 * This is because the CRC generatore in hardware is implemented
181 * as a shift-register with as many ex-ores as the radixes
182 * in the polynomium. This suggests that we represent the
183 * polynomiumm itself as a 32-bit constant.
185 for (byte = 0; byte < 6; byte++) {
186 currByte = mac[byte];
187 for (bit = 0; bit < 8; bit++) {
188 if ((currByte & 0x01) ^ (crc & 0x01)) {
190 crc = crc ^ 0xedb88320;
201 * Set individual hash table register
204 out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
205 out_be32(&fec->eth->iaddr2, 0);
207 out_be32(&fec->eth->iaddr1, 0);
208 out_be32(&fec->eth->iaddr2, (1 << crc));
212 * Set physical address
214 out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
215 (mac[2] << 8) + mac[3]);
216 out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
220 /********************************************************************/
221 static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
223 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
226 printf ("mpc512x_fec_init... Begin\n");
229 /* Set interrupt mask register */
230 out_be32(&fec->eth->imask, 0x00000000);
232 /* Clear FEC-Lite interrupt event register(IEVENT) */
233 out_be32(&fec->eth->ievent, 0xffffffff);
235 /* Set transmit fifo watermark register(X_WMRK), default = 64 */
236 out_be32(&fec->eth->x_wmrk, 0x0);
238 /* Set Opcode/Pause Duration Register */
239 out_be32(&fec->eth->op_pause, 0x00010020);
241 /* Frame length=1522; MII mode */
242 out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
244 /* Half-duplex, heartbeat disabled */
245 out_be32(&fec->eth->x_cntrl, 0x00000000);
247 /* Enable MIB counters */
248 out_be32(&fec->eth->mib_control, 0x0);
250 /* Setup recv fifo start and buff size */
251 out_be32(&fec->eth->r_fstart, 0x500);
252 out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
254 /* Setup BD base addresses */
255 out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
256 out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
259 out_be32(&fec->eth->dma_control, 0xc0000000);
262 setbits_be32(&fec->eth->ecntrl, 0x00000006);
264 /* Initilize addresses and status words of BDs */
265 mpc512x_fec_bd_init (fec);
267 /* Descriptor polling active */
268 out_be32(&fec->eth->r_des_active, 0x01000000);
271 printf("mpc512x_fec_init... Done \n");
276 /********************************************************************/
277 int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
279 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
280 const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
285 printf ("mpc512x_fec_init_phy... Begin\n");
289 * Clear FEC-Lite interrupt event register(IEVENT)
291 out_be32(&fec->eth->ievent, 0xffffffff);
294 * Set interrupt mask register
296 out_be32(&fec->eth->imask, 0x00000000);
298 if (fec->xcv_type != SEVENWIRE) {
300 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
301 * and do not drop the Preamble.
303 out_be32(&fec->eth->mii_speed,
304 (((gd->ips_clk / 1000000) / 5) + 1) << 1);
307 * Reset PHY, then delay 300ns
309 miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
312 if (fec->xcv_type == MII10) {
314 * Force 10Base-T, FDX operation
317 printf ("Forcing 10 Mbps ethernet link... ");
319 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
321 miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
324 do { /* wait for link status to go down */
326 if ((timeout--) == 0) {
328 printf ("hmmm, should not have waited...");
332 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
336 } while ((phyStatus & 0x0004)); /* !link up */
339 do { /* wait for link status to come back up */
341 if ((timeout--) == 0) {
342 printf ("failed. Link is down.\n");
345 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
349 } while (!(phyStatus & 0x0004)); /* !link up */
354 } else { /* MII100 */
356 * Set the auto-negotiation advertisement register bits
358 miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
361 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
363 miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
366 * Wait for AN completion
372 if ((timeout--) == 0) {
374 printf ("PHY auto neg 0 failed...\n");
379 if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
381 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
385 } while (!(phyStatus & 0x0004));
388 printf ("PHY auto neg complete! \n");
394 if (fec->xcv_type != SEVENWIRE)
395 mpc512x_fec_phydump (dev->name);
399 printf ("mpc512x_fec_init_phy... Done \n");
404 /********************************************************************/
405 static void mpc512x_fec_halt (struct eth_device *dev)
407 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
408 int counter = 0xffff;
411 if (fec->xcv_type != SEVENWIRE)
412 mpc512x_fec_phydump (dev->name);
416 * mask FEC chip interrupts
418 out_be32(&fec->eth->imask, 0);
421 * issue graceful stop command to the FEC transmitter if necessary
423 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
426 * wait for graceful stop to register
428 while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
432 * Disable the Ethernet Controller
434 clrbits_be32(&fec->eth->ecntrl, 0x00000002);
437 * Issue a reset command to the FEC chip
439 setbits_be32(&fec->eth->ecntrl, 0x1);
442 * wait at least 16 clock cycles
446 printf ("Ethernet task stopped\n");
450 /********************************************************************/
452 static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
456 * This routine transmits one frame. This routine only accepts
457 * 6-byte Ethernet addresses.
459 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
460 volatile FEC_TBD *pTbd;
463 printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
467 * Clear Tx BD ring at first
469 mpc512x_fec_tbd_scrub (fec);
472 * Check for valid length of data.
474 if ((data_length > 1500) || (data_length <= 0)) {
479 * Check the number of vacant TxBDs.
481 if (fec->cleanTbdNum < 1) {
483 printf ("No available TxBDs ...\n");
489 * Get the first TxBD to send the mac header
491 pTbd = &fec->bdBase->tbd[fec->tbdIndex];
492 pTbd->dataLength = data_length;
493 pTbd->dataPointer = (u32)eth_data;
494 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
495 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
497 /* Activate transmit Buffer Descriptor polling */
498 out_be32(&fec->eth->x_des_active, 0x01000000);
504 fec->cleanTbdNum -= 1;
507 * wait until frame is sent .
509 while (pTbd->status & FEC_TBD_READY) {
512 printf ("TDB status = %04x\n", pTbd->status);
520 /********************************************************************/
521 static int mpc512x_fec_recv (struct eth_device *dev)
524 * This command pulls one frame from the card
526 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
527 volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
528 unsigned long ievent;
529 int frame_length = 0;
532 printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
539 * Check if any critical events have happened
541 ievent = in_be32(&fec->eth->ievent);
542 out_be32(&fec->eth->ievent, ievent);
543 if (ievent & 0x20060000) {
544 /* BABT, Rx/Tx FIFO errors */
545 mpc512x_fec_halt (dev);
546 mpc512x_fec_init (dev, NULL);
549 if (ievent & 0x80000000) {
550 /* Heartbeat error */
551 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
553 if (ievent & 0x10000000) {
554 /* Graceful stop complete */
555 if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
556 mpc512x_fec_halt (dev);
557 clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
558 mpc512x_fec_init (dev, NULL);
562 if (!(pRbd->status & FEC_RBD_EMPTY)) {
563 if (!(pRbd->status & FEC_RBD_ERR) &&
564 ((pRbd->dataLength - 4) > 14)) {
569 if (pRbd->status & FEC_RBD_LAST)
570 frame_length = pRbd->dataLength - 4;
572 frame_length = pRbd->dataLength;
576 printf ("recv data length 0x%08x data hdr: ",
578 for (i = 0; i < 14; i++)
579 printf ("%x ", *((u8*)pRbd->dataPointer + i));
584 * Fill the buffer and pass it to upper layers
586 memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
587 frame_length - rx_buff_idx);
588 rx_buff_idx = frame_length;
590 if (pRbd->status & FEC_RBD_LAST) {
591 NetReceive ((uchar*)rx_buff, frame_length);
597 * Reset buffer descriptor as empty
599 mpc512x_fec_rbd_clean (fec, pRbd);
602 /* Try to fill Buffer Descriptors */
603 out_be32(&fec->eth->r_des_active, 0x01000000);
608 /********************************************************************/
609 int mpc512x_fec_initialize (bd_t * bis)
611 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
612 mpc512x_fec_priv *fec;
613 struct eth_device *dev;
615 char *tmp, *end, env_enetaddr[6];
618 fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
619 dev = (struct eth_device *) malloc (sizeof(*dev));
620 memset (dev, 0, sizeof *dev);
624 # ifndef CONFIG_FEC_10MBIT
625 fec->xcv_type = MII100;
627 fec->xcv_type = MII10;
629 dev->priv = (void *)fec;
630 dev->iobase = (int)&im->fec;
631 dev->init = mpc512x_fec_init;
632 dev->halt = mpc512x_fec_halt;
633 dev->send = mpc512x_fec_send;
634 dev->recv = mpc512x_fec_recv;
636 sprintf (dev->name, "FEC ETHERNET");
639 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
640 miiphy_register (dev->name,
641 fec512x_miiphy_read, fec512x_miiphy_write);
644 /* Clean up space FEC's MIB and FIFO RAM ...*/
645 memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib));
646 memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
649 * Malloc space for BDs (must be quad word-aligned)
650 * this pointer is lost, so cannot be freed
652 bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
653 fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
654 memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
657 * Set interrupt mask register
659 out_be32(&fec->eth->imask, 0x00000000);
662 * Clear FEC-Lite interrupt event register(IEVENT)
664 out_be32(&fec->eth->ievent, 0xffffffff);
667 * Try to set the mac address now. The fec mac address is
668 * a garbage after reset. When not using fec for booting
669 * the Linux fec driver will try to work with this garbage.
671 tmp = getenv ("ethaddr");
673 for (i=0; i<6; i++) {
674 env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0;
676 tmp = (*end) ? end+1 : end;
678 mpc512x_fec_set_hwaddr (fec, env_enetaddr);
679 out_be32(&fec->eth->gaddr1, 0x00000000);
680 out_be32(&fec->eth->gaddr2, 0x00000000);
683 mpc512x_fec_init_phy (dev, bis);
688 /* MII-interface related functions */
689 /********************************************************************/
690 int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
692 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
693 volatile fec512x_t *eth = &im->fec;
694 u32 reg; /* convenient holder for the PHY register */
695 u32 phy; /* convenient holder for the PHY */
696 int timeout = 0xffff;
699 * reading from any PHY's register is done by properly
700 * programming the FEC's MII data register.
702 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
703 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
705 out_be32(ð->mii_data, FEC_MII_DATA_ST |
711 * wait for the related interrupt
713 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
718 printf ("Read MDIO failed...\n");
724 * clear mii interrupt bit
726 out_be32(ð->ievent, 0x00800000);
729 * it's now safe to read the PHY's register
731 *retVal = (u16) in_be32(ð->mii_data);
736 /********************************************************************/
737 int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
739 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
740 volatile fec512x_t *eth = &im->fec;
741 u32 reg; /* convenient holder for the PHY register */
742 u32 phy; /* convenient holder for the PHY */
743 int timeout = 0xffff;
745 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
746 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
748 out_be32(ð->mii_data, FEC_MII_DATA_ST |
754 * wait for the MII interrupt
756 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
761 printf ("Write MDIO failed...\n");
767 * clear MII interrupt bit
769 out_be32(ð->ievent, 0x00800000);
774 #endif /* CONFIG_MPC512x_FEC */