1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Driver for the MDIO interface of Microsemi network switches.
5 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
6 * Copyright (c) 2017 Microsemi Corporation
9 #include <linux/bitops.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mdio/mdio-mscc-miim.h>
14 #include <linux/module.h>
15 #include <linux/of_mdio.h>
16 #include <linux/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
20 #define MSCC_MIIM_REG_STATUS 0x0
21 #define MSCC_MIIM_STATUS_STAT_PENDING BIT(2)
22 #define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
23 #define MSCC_MIIM_REG_CMD 0x8
24 #define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
25 #define MSCC_MIIM_CMD_OPR_READ BIT(2)
26 #define MSCC_MIIM_CMD_WRDATA_SHIFT 4
27 #define MSCC_MIIM_CMD_REGAD_SHIFT 20
28 #define MSCC_MIIM_CMD_PHYAD_SHIFT 25
29 #define MSCC_MIIM_CMD_VLD BIT(31)
30 #define MSCC_MIIM_REG_DATA 0xC
31 #define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
33 #define MSCC_PHY_REG_PHY_CFG 0x0
34 #define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3))
35 #define PHY_CFG_PHY_COMMON_RESET BIT(4)
36 #define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
37 #define MSCC_PHY_REG_PHY_STATUS 0x4
39 struct mscc_miim_dev {
41 int mii_status_offset;
42 struct regmap *phy_regs;
46 /* When high resolution timers aren't built-in: we can't use usleep_range() as
47 * we would sleep way too long. Use udelay() instead.
49 #define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
51 if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \
52 readx_poll_timeout_atomic(op, addr, val, cond, delay_us, \
54 readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us); \
57 static int mscc_miim_status(struct mii_bus *bus)
59 struct mscc_miim_dev *miim = bus->priv;
62 ret = regmap_read(miim->regs,
63 MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
65 WARN_ONCE(1, "mscc miim status read error %d\n", ret);
72 static int mscc_miim_wait_ready(struct mii_bus *bus)
76 return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
77 !(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
81 static int mscc_miim_wait_pending(struct mii_bus *bus)
85 return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
86 !(val & MSCC_MIIM_STATUS_STAT_PENDING),
90 static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
92 struct mscc_miim_dev *miim = bus->priv;
96 ret = mscc_miim_wait_pending(bus);
100 ret = regmap_write(miim->regs,
101 MSCC_MIIM_REG_CMD + miim->mii_status_offset,
103 (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
104 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
105 MSCC_MIIM_CMD_OPR_READ);
108 WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
112 ret = mscc_miim_wait_ready(bus);
116 ret = regmap_read(miim->regs,
117 MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
119 WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
123 if (val & MSCC_MIIM_DATA_ERROR) {
133 static int mscc_miim_write(struct mii_bus *bus, int mii_id,
134 int regnum, u16 value)
136 struct mscc_miim_dev *miim = bus->priv;
139 ret = mscc_miim_wait_pending(bus);
143 ret = regmap_write(miim->regs,
144 MSCC_MIIM_REG_CMD + miim->mii_status_offset,
146 (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
147 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
148 (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
149 MSCC_MIIM_CMD_OPR_WRITE);
152 WARN_ONCE(1, "mscc miim write error %d\n", ret);
157 static int mscc_miim_reset(struct mii_bus *bus)
159 struct mscc_miim_dev *miim = bus->priv;
160 int offset = miim->phy_reset_offset;
163 if (miim->phy_regs) {
164 ret = regmap_write(miim->phy_regs,
165 MSCC_PHY_REG_PHY_CFG + offset, 0);
167 WARN_ONCE(1, "mscc reset set error %d\n", ret);
171 ret = regmap_write(miim->phy_regs,
172 MSCC_PHY_REG_PHY_CFG + offset, 0x1ff);
174 WARN_ONCE(1, "mscc reset clear error %d\n", ret);
184 static const struct regmap_config mscc_miim_regmap_config = {
190 int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
191 struct regmap *mii_regmap, int status_offset)
193 struct mscc_miim_dev *miim;
196 bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
201 bus->read = mscc_miim_read;
202 bus->write = mscc_miim_write;
203 bus->reset = mscc_miim_reset;
204 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
211 miim->regs = mii_regmap;
212 miim->mii_status_offset = status_offset;
218 EXPORT_SYMBOL(mscc_miim_setup);
220 static int mscc_miim_probe(struct platform_device *pdev)
222 struct regmap *mii_regmap, *phy_regmap = NULL;
223 void __iomem *regs, *phy_regs;
224 struct mscc_miim_dev *miim;
225 struct resource *res;
229 regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
231 dev_err(&pdev->dev, "Unable to map MIIM registers\n");
232 return PTR_ERR(regs);
235 mii_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
236 &mscc_miim_regmap_config);
238 if (IS_ERR(mii_regmap)) {
239 dev_err(&pdev->dev, "Unable to create MIIM regmap\n");
240 return PTR_ERR(mii_regmap);
243 /* This resource is optional */
244 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
246 phy_regs = devm_ioremap_resource(&pdev->dev, res);
247 if (IS_ERR(phy_regs)) {
248 dev_err(&pdev->dev, "Unable to map internal phy registers\n");
249 return PTR_ERR(phy_regs);
252 phy_regmap = devm_regmap_init_mmio(&pdev->dev, phy_regs,
253 &mscc_miim_regmap_config);
254 if (IS_ERR(phy_regmap)) {
255 dev_err(&pdev->dev, "Unable to create phy register regmap\n");
256 return PTR_ERR(phy_regmap);
260 ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0);
262 dev_err(&pdev->dev, "Unable to setup the MDIO bus\n");
267 miim->phy_regs = phy_regmap;
268 miim->phy_reset_offset = 0;
270 ret = of_mdiobus_register(bus, pdev->dev.of_node);
272 dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
276 platform_set_drvdata(pdev, bus);
281 static int mscc_miim_remove(struct platform_device *pdev)
283 struct mii_bus *bus = platform_get_drvdata(pdev);
285 mdiobus_unregister(bus);
290 static const struct of_device_id mscc_miim_match[] = {
291 { .compatible = "mscc,ocelot-miim" },
294 MODULE_DEVICE_TABLE(of, mscc_miim_match);
296 static struct platform_driver mscc_miim_driver = {
297 .probe = mscc_miim_probe,
298 .remove = mscc_miim_remove,
301 .of_match_table = mscc_miim_match,
305 module_platform_driver(mscc_miim_driver);
307 MODULE_DESCRIPTION("Microsemi MIIM driver");
308 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
309 MODULE_LICENSE("Dual MIT/GPL");