1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 #include <asm/global_data.h>
11 #include <linux/delay.h>
14 * The u-boot networking stack is a little weird. It seems like the
15 * networking core allocates receive buffers up front without any
16 * regard to the hardware that's supposed to actually receive those
19 * The MACB receives packets into 128-byte receive buffers, so the
20 * buffers allocated by the core isn't very practical to use. We'll
21 * allocate our own, but we need one such buffer in case a packet
22 * wraps around the DMA ring so that we have to copy it.
24 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
25 * configuration header. This way, the core allocates one RX buffer
26 * and one TX buffer, each of which can hold a ethernet packet of
29 * For some reason, the networking core unconditionally specifies a
30 * 32-byte packet "alignment" (which really should be called
31 * "padding"). MACB shouldn't need that, but we'll refrain from any
32 * core modifications here...
42 #include <linux/mii.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/arch/clk.h>
46 #include <linux/errno.h>
50 DECLARE_GLOBAL_DATA_PTR;
53 * These buffer sizes must be power of 2 and divisible
54 * by RX_BUFFER_MULTIPLE
56 #define MACB_RX_BUFFER_SIZE 128
57 #define GEM_RX_BUFFER_SIZE 2048
58 #define RX_BUFFER_MULTIPLE 64
60 #define MACB_RX_RING_SIZE 32
61 #define MACB_TX_RING_SIZE 16
63 #define MACB_TX_TIMEOUT 1000
64 #define MACB_AUTONEG_TIMEOUT 5000000
66 #ifdef CONFIG_MACB_ZYNQ
67 /* INCR4 AHB bursts */
68 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
69 /* Use full configured addressable space (8 Kb) */
70 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
71 /* Use full configured addressable space (4 Kb) */
72 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
73 /* Set RXBUF with use of 128 byte */
74 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
75 #define MACB_ZYNQ_GEM_DMACR_INIT \
76 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
77 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
78 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
79 MACB_ZYNQ_GEM_DMACR_RXBUF)
82 struct macb_dma_desc {
87 struct macb_dma_desc_64 {
92 #define HW_DMA_CAP_32B 0
93 #define HW_DMA_CAP_64B 1
95 #define DMA_DESC_SIZE 16
96 #define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
97 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
98 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
99 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
101 #define RXBUF_FRMLEN_MASK 0x00000fff
102 #define TXBUF_FRMLEN_MASK 0x000007ff
109 const struct macb_config *config;
111 unsigned int rx_tail;
112 unsigned int tx_head;
113 unsigned int tx_tail;
114 unsigned int next_rx_tail;
119 struct macb_dma_desc *rx_ring;
120 struct macb_dma_desc *tx_ring;
121 size_t rx_buffer_size;
123 unsigned long rx_buffer_dma;
124 unsigned long rx_ring_dma;
125 unsigned long tx_ring_dma;
127 struct macb_dma_desc *dummy_desc;
128 unsigned long dummy_desc_dma;
130 const struct device *dev;
131 #ifndef CONFIG_DM_ETH
132 struct eth_device netdev;
134 unsigned short phy_addr;
137 struct phy_device *phydev;
142 unsigned long pclk_rate;
144 phy_interface_t phy_interface;
148 struct macb_usrio_cfg {
156 unsigned int dma_burst_length;
157 unsigned int hw_dma_cap;
160 int (*clk_init)(struct udevice *dev, ulong rate);
161 const struct macb_usrio_cfg *usrio;
164 #ifndef CONFIG_DM_ETH
165 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
168 static int macb_is_gem(struct macb_device *macb)
170 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
173 #ifndef cpu_is_sama5d2
174 #define cpu_is_sama5d2() 0
177 #ifndef cpu_is_sama5d4
178 #define cpu_is_sama5d4() 0
181 static int gem_is_gigabit_capable(struct macb_device *macb)
184 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
185 * configured to support only 10/100.
187 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
190 static void macb_mdio_write(struct macb_device *macb, u8 phy_adr, u8 reg,
193 unsigned long netctl;
194 unsigned long netstat;
197 netctl = macb_readl(macb, NCR);
198 netctl |= MACB_BIT(MPE);
199 macb_writel(macb, NCR, netctl);
201 frame = (MACB_BF(SOF, 1)
203 | MACB_BF(PHYA, phy_adr)
206 | MACB_BF(DATA, value));
207 macb_writel(macb, MAN, frame);
210 netstat = macb_readl(macb, NSR);
211 } while (!(netstat & MACB_BIT(IDLE)));
213 netctl = macb_readl(macb, NCR);
214 netctl &= ~MACB_BIT(MPE);
215 macb_writel(macb, NCR, netctl);
218 static u16 macb_mdio_read(struct macb_device *macb, u8 phy_adr, u8 reg)
220 unsigned long netctl;
221 unsigned long netstat;
224 netctl = macb_readl(macb, NCR);
225 netctl |= MACB_BIT(MPE);
226 macb_writel(macb, NCR, netctl);
228 frame = (MACB_BF(SOF, 1)
230 | MACB_BF(PHYA, phy_adr)
233 macb_writel(macb, MAN, frame);
236 netstat = macb_readl(macb, NSR);
237 } while (!(netstat & MACB_BIT(IDLE)));
239 frame = macb_readl(macb, MAN);
241 netctl = macb_readl(macb, NCR);
242 netctl &= ~MACB_BIT(MPE);
243 macb_writel(macb, NCR, netctl);
245 return MACB_BFEXT(DATA, frame);
248 void __weak arch_get_mdio_control(const char *name)
253 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
255 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
259 struct udevice *dev = eth_get_dev_by_name(bus->name);
260 struct macb_device *macb = dev_get_priv(dev);
262 struct eth_device *dev = eth_get_dev_by_name(bus->name);
263 struct macb_device *macb = to_macb(dev);
266 arch_get_mdio_control(bus->name);
267 value = macb_mdio_read(macb, phy_adr, reg);
272 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
276 struct udevice *dev = eth_get_dev_by_name(bus->name);
277 struct macb_device *macb = dev_get_priv(dev);
279 struct eth_device *dev = eth_get_dev_by_name(bus->name);
280 struct macb_device *macb = to_macb(dev);
283 arch_get_mdio_control(bus->name);
284 macb_mdio_write(macb, phy_adr, reg, value);
292 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
295 invalidate_dcache_range(macb->rx_ring_dma,
296 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
299 invalidate_dcache_range(macb->tx_ring_dma,
300 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
304 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
307 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
308 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
310 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
311 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
314 static inline void macb_flush_rx_buffer(struct macb_device *macb)
316 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
317 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
321 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
323 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
324 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
328 #if defined(CONFIG_CMD_NET)
330 static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
332 return (struct macb_dma_desc_64 *)((void *)desc
333 + sizeof(struct macb_dma_desc));
336 static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
339 struct macb_dma_desc_64 *desc_64;
341 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
342 desc_64 = macb_64b_desc(desc);
343 desc_64->addrh = upper_32_bits(addr);
345 desc->addr = lower_32_bits(addr);
348 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
351 unsigned long paddr, ctrl;
352 unsigned int tx_head = macb->tx_head;
355 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
357 ctrl = length & TXBUF_FRMLEN_MASK;
358 ctrl |= MACB_BIT(TX_LAST);
359 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
360 ctrl |= MACB_BIT(TX_WRAP);
366 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
367 tx_head = tx_head * 2;
369 macb->tx_ring[tx_head].ctrl = ctrl;
370 macb_set_addr(macb, &macb->tx_ring[tx_head], paddr);
373 macb_flush_ring_desc(macb, TX);
374 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
377 * I guess this is necessary because the networking core may
378 * re-use the transmit buffer as soon as we return...
380 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
382 macb_invalidate_ring_desc(macb, TX);
383 ctrl = macb->tx_ring[tx_head].ctrl;
384 if (ctrl & MACB_BIT(TX_USED))
389 dma_unmap_single(paddr, length, DMA_TO_DEVICE);
391 if (i <= MACB_TX_TIMEOUT) {
392 if (ctrl & MACB_BIT(TX_UNDERRUN))
393 printf("%s: TX underrun\n", name);
394 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
395 printf("%s: TX buffers exhausted in mid frame\n", name);
397 printf("%s: TX timeout\n", name);
400 /* No one cares anyway */
404 static void reclaim_rx_buffers(struct macb_device *macb,
405 unsigned int new_tail)
412 macb_invalidate_ring_desc(macb, RX);
413 while (i > new_tail) {
414 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
418 macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
420 if (i > MACB_RX_RING_SIZE)
424 while (i < new_tail) {
425 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
429 macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
434 macb_flush_ring_desc(macb, RX);
435 macb->rx_tail = new_tail;
438 static int _macb_recv(struct macb_device *macb, uchar **packetp)
440 unsigned int next_rx_tail = macb->next_rx_tail;
446 macb->wrapped = false;
448 macb_invalidate_ring_desc(macb, RX);
450 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
451 next_rx_tail = next_rx_tail * 2;
453 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
456 status = macb->rx_ring[next_rx_tail].ctrl;
457 if (status & MACB_BIT(RX_SOF)) {
458 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
459 next_rx_tail = next_rx_tail / 2;
463 if (next_rx_tail != macb->rx_tail)
464 reclaim_rx_buffers(macb, next_rx_tail);
465 macb->wrapped = false;
468 if (status & MACB_BIT(RX_EOF)) {
469 buffer = macb->rx_buffer +
470 macb->rx_buffer_size * macb->rx_tail;
471 length = status & RXBUF_FRMLEN_MASK;
473 macb_invalidate_rx_buffer(macb);
475 unsigned int headlen, taillen;
477 headlen = macb->rx_buffer_size *
478 (MACB_RX_RING_SIZE - macb->rx_tail);
479 taillen = length - headlen;
480 memcpy((void *)net_rx_packets[0],
482 memcpy((void *)net_rx_packets[0] + headlen,
483 macb->rx_buffer, taillen);
484 *packetp = (void *)net_rx_packets[0];
489 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
491 next_rx_tail = next_rx_tail / 2;
494 if (++next_rx_tail >= MACB_RX_RING_SIZE)
496 macb->next_rx_tail = next_rx_tail;
499 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
501 next_rx_tail = next_rx_tail / 2;
505 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
506 macb->wrapped = true;
514 static void macb_phy_reset(struct macb_device *macb, const char *name)
519 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
520 macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv);
521 printf("%s: Starting autonegotiation...\n", name);
522 macb_mdio_write(macb, macb->phy_addr, MII_BMCR, (BMCR_ANENABLE
525 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
526 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
527 if (status & BMSR_ANEGCOMPLETE)
532 if (status & BMSR_ANEGCOMPLETE)
533 printf("%s: Autonegotiation complete\n", name);
535 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
539 static int macb_phy_find(struct macb_device *macb, const char *name)
544 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
545 if (phy_id != 0xffff) {
546 printf("%s: PHY present at %d\n", name, macb->phy_addr);
550 /* Search for PHY... */
551 for (i = 0; i < 32; i++) {
553 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
554 if (phy_id != 0xffff) {
555 printf("%s: PHY present at %d\n", name, i);
560 /* PHY isn't up to snuff */
561 printf("%s: PHY not found\n", name);
567 * macb_linkspd_cb - Linkspeed change callback function
568 * @dev/@regs: MACB udevice (DM version) or
569 * Base Register of MACB devices (non-DM version)
571 * Returns 0 when operation success and negative errno number
572 * when operation failed.
575 static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
579 gemgxl_regs = dev_read_addr_index_ptr(dev, 1);
584 * SiFive GEMGXL TX clock operation mode:
586 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
587 * and output clock on GMII output signal GTX_CLK
588 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
590 writel(rate != 125000000, gemgxl_regs);
594 static int macb_sama7g5_clk_init(struct udevice *dev, ulong rate)
599 ret = clk_get_by_name(dev, "tx_clk", &clk);
604 * This is for using GCK. Clock rate is addressed via assigned-clock
605 * property, so only clock enable is needed here. The switching to
606 * proper clock rate depending on link speed is managed by IP logic.
608 return clk_enable(&clk);
611 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
614 struct macb_device *macb = dev_get_priv(dev);
621 rate = 2500000; /* 2.5 MHz */
624 rate = 25000000; /* 25 MHz */
627 rate = 125000000; /* 125 MHz */
630 /* does not change anything */
634 if (macb->config->clk_init)
635 return macb->config->clk_init(dev, rate);
638 * "tx_clk" is an optional clock source for MACB.
639 * Ignore if it does not exist in DT.
641 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
646 ret = clk_set_rate(&tx_clk, rate);
655 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
662 static int macb_phy_init(struct udevice *dev, const char *name)
664 static int macb_phy_init(struct macb_device *macb, const char *name)
668 struct macb_device *macb = dev_get_priv(dev);
671 u16 phy_id, status, adv, lpa;
672 int media, speed, duplex;
676 arch_get_mdio_control(name);
677 /* Auto-detect phy_addr */
678 ret = macb_phy_find(macb, name);
682 /* Check if the PHY is up to snuff... */
683 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
684 if (phy_id == 0xffff) {
685 printf("%s: No PHY present\n", name);
691 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
692 macb->phy_interface);
694 /* need to consider other phy interface mode */
695 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
696 PHY_INTERFACE_MODE_RGMII);
699 printf("phy_connect failed\n");
703 phy_config(macb->phydev);
706 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
707 if (!(status & BMSR_LSTATUS)) {
708 /* Try to re-negotiate if we don't have link already. */
709 macb_phy_reset(macb, name);
711 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
712 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
713 if (status & BMSR_LSTATUS) {
715 * Delay a bit after the link is established,
716 * so that the next xfer does not fail
725 if (!(status & BMSR_LSTATUS)) {
726 printf("%s: link down (status: 0x%04x)\n",
731 /* First check for GMAC and that it is GiB capable */
732 if (gem_is_gigabit_capable(macb)) {
733 lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000);
735 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
737 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
740 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
742 duplex ? "full" : "half",
745 ncfgr = macb_readl(macb, NCFGR);
746 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
747 ncfgr |= GEM_BIT(GBE);
750 ncfgr |= MACB_BIT(FD);
752 macb_writel(macb, NCFGR, ncfgr);
755 ret = macb_linkspd_cb(dev, _1000BASET);
757 ret = macb_linkspd_cb(macb->regs, _1000BASET);
766 /* fall back for EMAC checking */
767 adv = macb_mdio_read(macb, macb->phy_addr, MII_ADVERTISE);
768 lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA);
769 media = mii_nway_result(lpa & adv);
770 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
772 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
773 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
775 speed ? "100" : "10",
776 duplex ? "full" : "half",
779 ncfgr = macb_readl(macb, NCFGR);
780 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
782 ncfgr |= MACB_BIT(SPD);
784 ret = macb_linkspd_cb(dev, _100BASET);
786 ret = macb_linkspd_cb(macb->regs, _100BASET);
790 ret = macb_linkspd_cb(dev, _10BASET);
792 ret = macb_linkspd_cb(macb->regs, _10BASET);
800 ncfgr |= MACB_BIT(FD);
801 macb_writel(macb, NCFGR, ncfgr);
806 static int gmac_init_multi_queues(struct macb_device *macb)
808 int i, num_queues = 1;
812 /* bit 0 is never set but queue 0 always exists */
813 queue_mask = gem_readl(macb, DCFG6) & 0xff;
816 for (i = 1; i < MACB_MAX_QUEUES; i++)
817 if (queue_mask & (1 << i))
820 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
821 macb->dummy_desc->addr = 0;
822 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
823 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
824 paddr = macb->dummy_desc_dma;
826 for (i = 1; i < num_queues; i++) {
827 gem_writel_queue_TBQP(macb, lower_32_bits(paddr), i - 1);
828 gem_writel_queue_RBQP(macb, lower_32_bits(paddr), i - 1);
829 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
830 gem_writel_queue_TBQPH(macb, upper_32_bits(paddr),
832 gem_writel_queue_RBQPH(macb, upper_32_bits(paddr),
839 static void gmac_configure_dma(struct macb_device *macb)
844 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
845 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
846 dmacfg |= GEM_BF(RXBS, buffer_size);
848 if (macb->config->dma_burst_length)
849 dmacfg = GEM_BFINS(FBLDO,
850 macb->config->dma_burst_length, dmacfg);
852 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
853 dmacfg &= ~GEM_BIT(ENDIA_PKT);
855 if (macb->is_big_endian)
856 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
858 dmacfg &= ~GEM_BIT(ENDIA_DESC);
860 dmacfg &= ~GEM_BIT(ADDR64);
861 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
862 dmacfg |= GEM_BIT(ADDR64);
864 gem_writel(macb, DMACFG, dmacfg);
868 static int _macb_init(struct udevice *dev, const char *name)
870 static int _macb_init(struct macb_device *macb, const char *name)
874 struct macb_device *macb = dev_get_priv(dev);
875 unsigned int val = 0;
883 * macb_halt should have been called at some point before now,
884 * so we'll assume the controller is idle.
887 /* initialize DMA descriptors */
888 paddr = macb->rx_buffer_dma;
889 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
890 if (i == (MACB_RX_RING_SIZE - 1))
891 paddr |= MACB_BIT(RX_WRAP);
892 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
896 macb->rx_ring[count].ctrl = 0;
897 macb_set_addr(macb, &macb->rx_ring[count], paddr);
898 paddr += macb->rx_buffer_size;
900 macb_flush_ring_desc(macb, RX);
901 macb_flush_rx_buffer(macb);
903 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
904 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
908 macb_set_addr(macb, &macb->tx_ring[count], 0);
909 if (i == (MACB_TX_RING_SIZE - 1))
910 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED) |
913 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED);
915 macb_flush_ring_desc(macb, TX);
920 macb->next_rx_tail = 0;
922 #ifdef CONFIG_MACB_ZYNQ
923 gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
926 macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
927 macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
928 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
929 macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
930 macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
933 if (macb_is_gem(macb)) {
934 /* Initialize DMA properties */
935 gmac_configure_dma(macb);
936 /* Check the multi queue and initialize the queue for tx */
937 gmac_init_multi_queues(macb);
940 * When the GMAC IP with GE feature, this bit is used to
941 * select interface between RGMII and GMII.
942 * When the GMAC IP without GE feature, this bit is used
943 * to select interface between RMII and MII.
946 if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII ||
947 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
948 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
949 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
950 val = macb->config->usrio->rgmii;
951 else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
952 val = macb->config->usrio->rmii;
953 else if (macb->phy_interface == PHY_INTERFACE_MODE_MII)
954 val = macb->config->usrio->mii;
956 if (macb->config->caps & MACB_CAPS_USRIO_HAS_CLKEN)
957 val |= macb->config->usrio->clken;
959 gem_writel(macb, USRIO, val);
961 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
962 unsigned int ncfgr = macb_readl(macb, NCFGR);
964 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
965 macb_writel(macb, NCFGR, ncfgr);
968 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
969 gem_writel(macb, USRIO, macb->config->usrio->rgmii);
971 gem_writel(macb, USRIO, 0);
975 /* choose RMII or MII mode. This depends on the board */
977 #ifdef CONFIG_AT91FAMILY
978 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
979 macb_writel(macb, USRIO,
980 macb->config->usrio->rmii |
981 macb->config->usrio->clken);
983 macb_writel(macb, USRIO, macb->config->usrio->clken);
986 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
987 macb_writel(macb, USRIO, 0);
989 macb_writel(macb, USRIO, macb->config->usrio->mii);
993 #ifdef CONFIG_AT91FAMILY
994 macb_writel(macb, USRIO, macb->config->usrio->rmii |
995 macb->config->usrio->clken);
997 macb_writel(macb, USRIO, 0);
1000 #ifdef CONFIG_AT91FAMILY
1001 macb_writel(macb, USRIO, macb->config->usrio->clken);
1003 macb_writel(macb, USRIO, macb->config->usrio->mii);
1005 #endif /* CONFIG_RMII */
1009 #ifdef CONFIG_DM_ETH
1010 ret = macb_phy_init(dev, name);
1012 ret = macb_phy_init(macb, name);
1017 /* Enable TX and RX */
1018 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
1023 static void _macb_halt(struct macb_device *macb)
1027 /* Halt the controller and wait for any ongoing transmission to end. */
1028 ncr = macb_readl(macb, NCR);
1029 ncr |= MACB_BIT(THALT);
1030 macb_writel(macb, NCR, ncr);
1033 tsr = macb_readl(macb, TSR);
1034 } while (tsr & MACB_BIT(TGO));
1036 /* Disable TX and RX, and clear statistics */
1037 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
1040 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
1045 /* set hardware address */
1046 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
1047 enetaddr[2] << 16 | enetaddr[3] << 24;
1048 macb_writel(macb, SA1B, hwaddr_bottom);
1049 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
1050 macb_writel(macb, SA1T, hwaddr_top);
1054 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
1057 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1058 unsigned long macb_hz = macb->pclk_rate;
1060 unsigned long macb_hz = get_macb_pclk_rate(id);
1063 if (macb_hz < 20000000)
1064 config = MACB_BF(CLK, MACB_CLK_DIV8);
1065 else if (macb_hz < 40000000)
1066 config = MACB_BF(CLK, MACB_CLK_DIV16);
1067 else if (macb_hz < 80000000)
1068 config = MACB_BF(CLK, MACB_CLK_DIV32);
1070 config = MACB_BF(CLK, MACB_CLK_DIV64);
1075 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
1079 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1080 unsigned long macb_hz = macb->pclk_rate;
1082 unsigned long macb_hz = get_macb_pclk_rate(id);
1085 if (macb_hz < 20000000)
1086 config = GEM_BF(CLK, GEM_CLK_DIV8);
1087 else if (macb_hz < 40000000)
1088 config = GEM_BF(CLK, GEM_CLK_DIV16);
1089 else if (macb_hz < 80000000)
1090 config = GEM_BF(CLK, GEM_CLK_DIV32);
1091 else if (macb_hz < 120000000)
1092 config = GEM_BF(CLK, GEM_CLK_DIV48);
1093 else if (macb_hz < 160000000)
1094 config = GEM_BF(CLK, GEM_CLK_DIV64);
1095 else if (macb_hz < 240000000)
1096 config = GEM_BF(CLK, GEM_CLK_DIV96);
1097 else if (macb_hz < 320000000)
1098 config = GEM_BF(CLK, GEM_CLK_DIV128);
1100 config = GEM_BF(CLK, GEM_CLK_DIV224);
1106 * Get the DMA bus width field of the network configuration register that we
1107 * should program. We find the width from decoding the design configuration
1108 * register to find the maximum supported data bus width.
1110 static u32 macb_dbw(struct macb_device *macb)
1112 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
1114 return GEM_BF(DBW, GEM_DBW128);
1116 return GEM_BF(DBW, GEM_DBW64);
1119 return GEM_BF(DBW, GEM_DBW32);
1123 static void _macb_eth_initialize(struct macb_device *macb)
1125 int id = 0; /* This is not used by functions we call */
1128 if (macb_is_gem(macb))
1129 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1131 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1133 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
1134 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1136 &macb->rx_buffer_dma);
1137 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
1138 &macb->rx_ring_dma);
1139 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
1140 &macb->tx_ring_dma);
1141 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1142 &macb->dummy_desc_dma);
1145 * Do some basic initialization so that we at least can talk
1148 if (macb_is_gem(macb)) {
1149 ncfgr = gem_mdc_clk_div(id, macb);
1150 ncfgr |= macb_dbw(macb);
1152 ncfgr = macb_mdc_clk_div(id, macb);
1155 macb_writel(macb, NCFGR, ncfgr);
1158 #ifndef CONFIG_DM_ETH
1159 static int macb_send(struct eth_device *netdev, void *packet, int length)
1161 struct macb_device *macb = to_macb(netdev);
1163 return _macb_send(macb, netdev->name, packet, length);
1166 static int macb_recv(struct eth_device *netdev)
1168 struct macb_device *macb = to_macb(netdev);
1172 macb->wrapped = false;
1174 macb->next_rx_tail = macb->rx_tail;
1175 length = _macb_recv(macb, &packet);
1177 net_process_received_packet(packet, length);
1178 reclaim_rx_buffers(macb, macb->next_rx_tail);
1185 static int macb_init(struct eth_device *netdev, struct bd_info *bd)
1187 struct macb_device *macb = to_macb(netdev);
1189 return _macb_init(macb, netdev->name);
1192 static void macb_halt(struct eth_device *netdev)
1194 struct macb_device *macb = to_macb(netdev);
1196 return _macb_halt(macb);
1199 static int macb_write_hwaddr(struct eth_device *netdev)
1201 struct macb_device *macb = to_macb(netdev);
1203 return _macb_write_hwaddr(macb, netdev->enetaddr);
1206 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1208 struct macb_device *macb;
1209 struct eth_device *netdev;
1211 macb = malloc(sizeof(struct macb_device));
1213 printf("Error: Failed to allocate memory for MACB%d\n", id);
1216 memset(macb, 0, sizeof(struct macb_device));
1218 netdev = &macb->netdev;
1221 macb->phy_addr = phy_addr;
1223 if (macb_is_gem(macb))
1224 sprintf(netdev->name, "gmac%d", id);
1226 sprintf(netdev->name, "macb%d", id);
1228 netdev->init = macb_init;
1229 netdev->halt = macb_halt;
1230 netdev->send = macb_send;
1231 netdev->recv = macb_recv;
1232 netdev->write_hwaddr = macb_write_hwaddr;
1234 _macb_eth_initialize(macb);
1236 eth_register(netdev);
1238 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1240 struct mii_dev *mdiodev = mdio_alloc();
1243 strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1244 mdiodev->read = macb_miiphy_read;
1245 mdiodev->write = macb_miiphy_write;
1247 retval = mdio_register(mdiodev);
1250 macb->bus = miiphy_get_dev_by_name(netdev->name);
1254 #endif /* !CONFIG_DM_ETH */
1256 #ifdef CONFIG_DM_ETH
1258 static int macb_start(struct udevice *dev)
1260 return _macb_init(dev, dev->name);
1263 static int macb_send(struct udevice *dev, void *packet, int length)
1265 struct macb_device *macb = dev_get_priv(dev);
1267 return _macb_send(macb, dev->name, packet, length);
1270 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1272 struct macb_device *macb = dev_get_priv(dev);
1274 macb->next_rx_tail = macb->rx_tail;
1275 macb->wrapped = false;
1277 return _macb_recv(macb, packetp);
1280 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1282 struct macb_device *macb = dev_get_priv(dev);
1284 reclaim_rx_buffers(macb, macb->next_rx_tail);
1289 static void macb_stop(struct udevice *dev)
1291 struct macb_device *macb = dev_get_priv(dev);
1296 static int macb_write_hwaddr(struct udevice *dev)
1298 struct eth_pdata *plat = dev_get_plat(dev);
1299 struct macb_device *macb = dev_get_priv(dev);
1301 return _macb_write_hwaddr(macb, plat->enetaddr);
1304 static const struct eth_ops macb_eth_ops = {
1305 .start = macb_start,
1309 .free_pkt = macb_free_pkt,
1310 .write_hwaddr = macb_write_hwaddr,
1314 static int macb_enable_clk(struct udevice *dev)
1316 struct macb_device *macb = dev_get_priv(dev);
1321 ret = clk_get_by_index(dev, 0, &clk);
1326 * If clock driver didn't support enable or disable then
1327 * we get -ENOSYS from clk_enable(). To handle this, we
1328 * don't fail for ret == -ENOSYS.
1330 ret = clk_enable(&clk);
1331 if (ret && ret != -ENOSYS)
1334 clk_rate = clk_get_rate(&clk);
1338 macb->pclk_rate = clk_rate;
1344 static const struct macb_usrio_cfg macb_default_usrio = {
1345 .mii = MACB_BIT(MII),
1346 .rmii = MACB_BIT(RMII),
1347 .rgmii = GEM_BIT(RGMII),
1348 .clken = MACB_BIT(CLKEN),
1351 static struct macb_config default_gem_config = {
1352 .dma_burst_length = 16,
1353 .hw_dma_cap = HW_DMA_CAP_32B,
1355 .usrio = &macb_default_usrio,
1358 static int macb_eth_probe(struct udevice *dev)
1360 struct eth_pdata *pdata = dev_get_plat(dev);
1361 struct macb_device *macb = dev_get_priv(dev);
1362 struct ofnode_phandle_args phandle_args;
1365 macb->phy_interface = dev_read_phy_mode(dev);
1366 if (macb->phy_interface == PHY_INTERFACE_MODE_NA)
1369 /* Read phyaddr from DT */
1370 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1372 macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
1375 macb->regs = (void *)(uintptr_t)pdata->iobase;
1377 macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
1379 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1380 if (!macb->config) {
1381 if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT)) {
1382 if (GEM_BFEXT(DAW64, gem_readl(macb, DCFG6)))
1383 default_gem_config.hw_dma_cap = HW_DMA_CAP_64B;
1385 macb->config = &default_gem_config;
1389 ret = macb_enable_clk(dev);
1394 _macb_eth_initialize(macb);
1396 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1397 macb->bus = mdio_alloc();
1400 strlcpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1401 macb->bus->read = macb_miiphy_read;
1402 macb->bus->write = macb_miiphy_write;
1404 ret = mdio_register(macb->bus);
1407 macb->bus = miiphy_get_dev_by_name(dev->name);
1413 static int macb_eth_remove(struct udevice *dev)
1415 struct macb_device *macb = dev_get_priv(dev);
1417 #ifdef CONFIG_PHYLIB
1420 mdio_unregister(macb->bus);
1421 mdio_free(macb->bus);
1427 * macb_late_eth_of_to_plat
1428 * @dev: udevice struct
1429 * Returns 0 when operation success and negative errno number
1430 * when operation failed.
1432 int __weak macb_late_eth_of_to_plat(struct udevice *dev)
1437 static int macb_eth_of_to_plat(struct udevice *dev)
1439 struct eth_pdata *pdata = dev_get_plat(dev);
1441 pdata->iobase = (uintptr_t)dev_remap_addr(dev);
1445 return macb_late_eth_of_to_plat(dev);
1448 static const struct macb_usrio_cfg sama7g5_usrio = {
1455 static const struct macb_config sama5d4_config = {
1456 .dma_burst_length = 4,
1457 .hw_dma_cap = HW_DMA_CAP_32B,
1459 .usrio = &macb_default_usrio,
1462 static const struct macb_config sifive_config = {
1463 .dma_burst_length = 16,
1464 .hw_dma_cap = HW_DMA_CAP_32B,
1465 .clk_init = macb_sifive_clk_init,
1466 .usrio = &macb_default_usrio,
1469 static const struct macb_config sama7g5_gmac_config = {
1470 .dma_burst_length = 16,
1471 .hw_dma_cap = HW_DMA_CAP_32B,
1472 .clk_init = macb_sama7g5_clk_init,
1473 .usrio = &sama7g5_usrio,
1476 static const struct macb_config sama7g5_emac_config = {
1477 .caps = MACB_CAPS_USRIO_HAS_CLKEN,
1478 .dma_burst_length = 16,
1479 .hw_dma_cap = HW_DMA_CAP_32B,
1480 .usrio = &sama7g5_usrio,
1483 static const struct udevice_id macb_eth_ids[] = {
1484 { .compatible = "cdns,macb" },
1485 { .compatible = "cdns,at91sam9260-macb" },
1486 { .compatible = "cdns,sam9x60-macb" },
1487 { .compatible = "cdns,sama7g5-gem",
1488 .data = (ulong)&sama7g5_gmac_config },
1489 { .compatible = "cdns,sama7g5-emac",
1490 .data = (ulong)&sama7g5_emac_config },
1491 { .compatible = "atmel,sama5d2-gem" },
1492 { .compatible = "atmel,sama5d3-gem" },
1493 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1494 { .compatible = "cdns,zynq-gem" },
1495 { .compatible = "sifive,fu540-c000-gem",
1496 .data = (ulong)&sifive_config },
1500 U_BOOT_DRIVER(eth_macb) = {
1503 .of_match = macb_eth_ids,
1504 .of_to_plat = macb_eth_of_to_plat,
1505 .probe = macb_eth_probe,
1506 .remove = macb_eth_remove,
1507 .ops = &macb_eth_ops,
1508 .priv_auto = sizeof(struct macb_device),
1509 .plat_auto = sizeof(struct eth_pdata),