1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 #include <linux/delay.h>
13 * The u-boot networking stack is a little weird. It seems like the
14 * networking core allocates receive buffers up front without any
15 * regard to the hardware that's supposed to actually receive those
18 * The MACB receives packets into 128-byte receive buffers, so the
19 * buffers allocated by the core isn't very practical to use. We'll
20 * allocate our own, but we need one such buffer in case a packet
21 * wraps around the DMA ring so that we have to copy it.
23 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
24 * configuration header. This way, the core allocates one RX buffer
25 * and one TX buffer, each of which can hold a ethernet packet of
28 * For some reason, the networking core unconditionally specifies a
29 * 32-byte packet "alignment" (which really should be called
30 * "padding"). MACB shouldn't need that, but we'll refrain from any
31 * core modifications here...
41 #include <linux/mii.h>
43 #include <linux/dma-mapping.h>
44 #include <asm/arch/clk.h>
45 #include <linux/errno.h>
49 DECLARE_GLOBAL_DATA_PTR;
52 * These buffer sizes must be power of 2 and divisible
53 * by RX_BUFFER_MULTIPLE
55 #define MACB_RX_BUFFER_SIZE 128
56 #define GEM_RX_BUFFER_SIZE 2048
57 #define RX_BUFFER_MULTIPLE 64
59 #define MACB_RX_RING_SIZE 32
60 #define MACB_TX_RING_SIZE 16
62 #define MACB_TX_TIMEOUT 1000
63 #define MACB_AUTONEG_TIMEOUT 5000000
65 #ifdef CONFIG_MACB_ZYNQ
66 /* INCR4 AHB bursts */
67 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
68 /* Use full configured addressable space (8 Kb) */
69 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
70 /* Use full configured addressable space (4 Kb) */
71 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
72 /* Set RXBUF with use of 128 byte */
73 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
74 #define MACB_ZYNQ_GEM_DMACR_INIT \
75 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
76 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
77 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
78 MACB_ZYNQ_GEM_DMACR_RXBUF)
81 struct macb_dma_desc {
86 struct macb_dma_desc_64 {
91 #define HW_DMA_CAP_32B 0
92 #define HW_DMA_CAP_64B 1
94 #define DMA_DESC_SIZE 16
95 #define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
96 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
97 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
98 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
100 #define RXBUF_FRMLEN_MASK 0x00000fff
101 #define TXBUF_FRMLEN_MASK 0x000007ff
108 const struct macb_config *config;
110 unsigned int rx_tail;
111 unsigned int tx_head;
112 unsigned int tx_tail;
113 unsigned int next_rx_tail;
118 struct macb_dma_desc *rx_ring;
119 struct macb_dma_desc *tx_ring;
120 size_t rx_buffer_size;
122 unsigned long rx_buffer_dma;
123 unsigned long rx_ring_dma;
124 unsigned long tx_ring_dma;
126 struct macb_dma_desc *dummy_desc;
127 unsigned long dummy_desc_dma;
129 const struct device *dev;
130 #ifndef CONFIG_DM_ETH
131 struct eth_device netdev;
133 unsigned short phy_addr;
136 struct phy_device *phydev;
141 unsigned long pclk_rate;
143 phy_interface_t phy_interface;
147 struct macb_usrio_cfg {
155 unsigned int dma_burst_length;
156 unsigned int hw_dma_cap;
159 int (*clk_init)(struct udevice *dev, ulong rate);
160 const struct macb_usrio_cfg *usrio;
163 #ifndef CONFIG_DM_ETH
164 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
167 static int macb_is_gem(struct macb_device *macb)
169 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
172 #ifndef cpu_is_sama5d2
173 #define cpu_is_sama5d2() 0
176 #ifndef cpu_is_sama5d4
177 #define cpu_is_sama5d4() 0
180 static int gem_is_gigabit_capable(struct macb_device *macb)
183 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
184 * configured to support only 10/100.
186 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
189 static void macb_mdio_write(struct macb_device *macb, u8 phy_adr, u8 reg,
192 unsigned long netctl;
193 unsigned long netstat;
196 netctl = macb_readl(macb, NCR);
197 netctl |= MACB_BIT(MPE);
198 macb_writel(macb, NCR, netctl);
200 frame = (MACB_BF(SOF, 1)
202 | MACB_BF(PHYA, phy_adr)
205 | MACB_BF(DATA, value));
206 macb_writel(macb, MAN, frame);
209 netstat = macb_readl(macb, NSR);
210 } while (!(netstat & MACB_BIT(IDLE)));
212 netctl = macb_readl(macb, NCR);
213 netctl &= ~MACB_BIT(MPE);
214 macb_writel(macb, NCR, netctl);
217 static u16 macb_mdio_read(struct macb_device *macb, u8 phy_adr, u8 reg)
219 unsigned long netctl;
220 unsigned long netstat;
223 netctl = macb_readl(macb, NCR);
224 netctl |= MACB_BIT(MPE);
225 macb_writel(macb, NCR, netctl);
227 frame = (MACB_BF(SOF, 1)
229 | MACB_BF(PHYA, phy_adr)
232 macb_writel(macb, MAN, frame);
235 netstat = macb_readl(macb, NSR);
236 } while (!(netstat & MACB_BIT(IDLE)));
238 frame = macb_readl(macb, MAN);
240 netctl = macb_readl(macb, NCR);
241 netctl &= ~MACB_BIT(MPE);
242 macb_writel(macb, NCR, netctl);
244 return MACB_BFEXT(DATA, frame);
247 void __weak arch_get_mdio_control(const char *name)
252 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
254 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
258 struct udevice *dev = eth_get_dev_by_name(bus->name);
259 struct macb_device *macb = dev_get_priv(dev);
261 struct eth_device *dev = eth_get_dev_by_name(bus->name);
262 struct macb_device *macb = to_macb(dev);
265 arch_get_mdio_control(bus->name);
266 value = macb_mdio_read(macb, phy_adr, reg);
271 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
275 struct udevice *dev = eth_get_dev_by_name(bus->name);
276 struct macb_device *macb = dev_get_priv(dev);
278 struct eth_device *dev = eth_get_dev_by_name(bus->name);
279 struct macb_device *macb = to_macb(dev);
282 arch_get_mdio_control(bus->name);
283 macb_mdio_write(macb, phy_adr, reg, value);
291 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
294 invalidate_dcache_range(macb->rx_ring_dma,
295 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
298 invalidate_dcache_range(macb->tx_ring_dma,
299 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
303 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
306 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
307 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
309 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
310 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
313 static inline void macb_flush_rx_buffer(struct macb_device *macb)
315 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
316 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
320 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
322 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
323 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
327 #if defined(CONFIG_CMD_NET)
329 static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
331 return (struct macb_dma_desc_64 *)((void *)desc
332 + sizeof(struct macb_dma_desc));
335 static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
338 struct macb_dma_desc_64 *desc_64;
340 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
341 desc_64 = macb_64b_desc(desc);
342 desc_64->addrh = upper_32_bits(addr);
344 desc->addr = lower_32_bits(addr);
347 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
350 unsigned long paddr, ctrl;
351 unsigned int tx_head = macb->tx_head;
354 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
356 ctrl = length & TXBUF_FRMLEN_MASK;
357 ctrl |= MACB_BIT(TX_LAST);
358 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
359 ctrl |= MACB_BIT(TX_WRAP);
365 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
366 tx_head = tx_head * 2;
368 macb->tx_ring[tx_head].ctrl = ctrl;
369 macb_set_addr(macb, &macb->tx_ring[tx_head], paddr);
372 macb_flush_ring_desc(macb, TX);
373 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
376 * I guess this is necessary because the networking core may
377 * re-use the transmit buffer as soon as we return...
379 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
381 macb_invalidate_ring_desc(macb, TX);
382 ctrl = macb->tx_ring[tx_head].ctrl;
383 if (ctrl & MACB_BIT(TX_USED))
388 dma_unmap_single(paddr, length, DMA_TO_DEVICE);
390 if (i <= MACB_TX_TIMEOUT) {
391 if (ctrl & MACB_BIT(TX_UNDERRUN))
392 printf("%s: TX underrun\n", name);
393 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
394 printf("%s: TX buffers exhausted in mid frame\n", name);
396 printf("%s: TX timeout\n", name);
399 /* No one cares anyway */
403 static void reclaim_rx_buffers(struct macb_device *macb,
404 unsigned int new_tail)
411 macb_invalidate_ring_desc(macb, RX);
412 while (i > new_tail) {
413 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
417 macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
419 if (i > MACB_RX_RING_SIZE)
423 while (i < new_tail) {
424 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
428 macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
433 macb_flush_ring_desc(macb, RX);
434 macb->rx_tail = new_tail;
437 static int _macb_recv(struct macb_device *macb, uchar **packetp)
439 unsigned int next_rx_tail = macb->next_rx_tail;
445 macb->wrapped = false;
447 macb_invalidate_ring_desc(macb, RX);
449 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
450 next_rx_tail = next_rx_tail * 2;
452 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
455 status = macb->rx_ring[next_rx_tail].ctrl;
456 if (status & MACB_BIT(RX_SOF)) {
457 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
458 next_rx_tail = next_rx_tail / 2;
462 if (next_rx_tail != macb->rx_tail)
463 reclaim_rx_buffers(macb, next_rx_tail);
464 macb->wrapped = false;
467 if (status & MACB_BIT(RX_EOF)) {
468 buffer = macb->rx_buffer +
469 macb->rx_buffer_size * macb->rx_tail;
470 length = status & RXBUF_FRMLEN_MASK;
472 macb_invalidate_rx_buffer(macb);
474 unsigned int headlen, taillen;
476 headlen = macb->rx_buffer_size *
477 (MACB_RX_RING_SIZE - macb->rx_tail);
478 taillen = length - headlen;
479 memcpy((void *)net_rx_packets[0],
481 memcpy((void *)net_rx_packets[0] + headlen,
482 macb->rx_buffer, taillen);
483 *packetp = (void *)net_rx_packets[0];
488 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
490 next_rx_tail = next_rx_tail / 2;
493 if (++next_rx_tail >= MACB_RX_RING_SIZE)
495 macb->next_rx_tail = next_rx_tail;
498 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
500 next_rx_tail = next_rx_tail / 2;
504 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
505 macb->wrapped = true;
513 static void macb_phy_reset(struct macb_device *macb, const char *name)
518 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
519 macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv);
520 printf("%s: Starting autonegotiation...\n", name);
521 macb_mdio_write(macb, macb->phy_addr, MII_BMCR, (BMCR_ANENABLE
524 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
525 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
526 if (status & BMSR_ANEGCOMPLETE)
531 if (status & BMSR_ANEGCOMPLETE)
532 printf("%s: Autonegotiation complete\n", name);
534 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
538 static int macb_phy_find(struct macb_device *macb, const char *name)
543 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
544 if (phy_id != 0xffff) {
545 printf("%s: PHY present at %d\n", name, macb->phy_addr);
549 /* Search for PHY... */
550 for (i = 0; i < 32; i++) {
552 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
553 if (phy_id != 0xffff) {
554 printf("%s: PHY present at %d\n", name, i);
559 /* PHY isn't up to snuff */
560 printf("%s: PHY not found\n", name);
566 * macb_linkspd_cb - Linkspeed change callback function
567 * @dev/@regs: MACB udevice (DM version) or
568 * Base Register of MACB devices (non-DM version)
570 * Returns 0 when operation success and negative errno number
571 * when operation failed.
574 static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
579 addr = dev_read_addr_index(dev, 1);
580 if (addr == FDT_ADDR_T_NONE)
583 gemgxl_regs = (void __iomem *)addr;
588 * SiFive GEMGXL TX clock operation mode:
590 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
591 * and output clock on GMII output signal GTX_CLK
592 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
594 writel(rate != 125000000, gemgxl_regs);
598 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
601 struct macb_device *macb = dev_get_priv(dev);
608 rate = 2500000; /* 2.5 MHz */
611 rate = 25000000; /* 25 MHz */
614 rate = 125000000; /* 125 MHz */
617 /* does not change anything */
621 if (macb->config->clk_init)
622 return macb->config->clk_init(dev, rate);
625 * "tx_clk" is an optional clock source for MACB.
626 * Ignore if it does not exist in DT.
628 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
633 ret = clk_set_rate(&tx_clk, rate);
642 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
649 static int macb_phy_init(struct udevice *dev, const char *name)
651 static int macb_phy_init(struct macb_device *macb, const char *name)
655 struct macb_device *macb = dev_get_priv(dev);
658 u16 phy_id, status, adv, lpa;
659 int media, speed, duplex;
663 arch_get_mdio_control(name);
664 /* Auto-detect phy_addr */
665 ret = macb_phy_find(macb, name);
669 /* Check if the PHY is up to snuff... */
670 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
671 if (phy_id == 0xffff) {
672 printf("%s: No PHY present\n", name);
678 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
679 macb->phy_interface);
681 /* need to consider other phy interface mode */
682 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
683 PHY_INTERFACE_MODE_RGMII);
686 printf("phy_connect failed\n");
690 phy_config(macb->phydev);
693 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
694 if (!(status & BMSR_LSTATUS)) {
695 /* Try to re-negotiate if we don't have link already. */
696 macb_phy_reset(macb, name);
698 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
699 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
700 if (status & BMSR_LSTATUS) {
702 * Delay a bit after the link is established,
703 * so that the next xfer does not fail
712 if (!(status & BMSR_LSTATUS)) {
713 printf("%s: link down (status: 0x%04x)\n",
718 /* First check for GMAC and that it is GiB capable */
719 if (gem_is_gigabit_capable(macb)) {
720 lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000);
722 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
724 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
727 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
729 duplex ? "full" : "half",
732 ncfgr = macb_readl(macb, NCFGR);
733 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
734 ncfgr |= GEM_BIT(GBE);
737 ncfgr |= MACB_BIT(FD);
739 macb_writel(macb, NCFGR, ncfgr);
742 ret = macb_linkspd_cb(dev, _1000BASET);
744 ret = macb_linkspd_cb(macb->regs, _1000BASET);
753 /* fall back for EMAC checking */
754 adv = macb_mdio_read(macb, macb->phy_addr, MII_ADVERTISE);
755 lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA);
756 media = mii_nway_result(lpa & adv);
757 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
759 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
760 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
762 speed ? "100" : "10",
763 duplex ? "full" : "half",
766 ncfgr = macb_readl(macb, NCFGR);
767 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
769 ncfgr |= MACB_BIT(SPD);
771 ret = macb_linkspd_cb(dev, _100BASET);
773 ret = macb_linkspd_cb(macb->regs, _100BASET);
777 ret = macb_linkspd_cb(dev, _10BASET);
779 ret = macb_linkspd_cb(macb->regs, _10BASET);
787 ncfgr |= MACB_BIT(FD);
788 macb_writel(macb, NCFGR, ncfgr);
793 static int gmac_init_multi_queues(struct macb_device *macb)
795 int i, num_queues = 1;
799 /* bit 0 is never set but queue 0 always exists */
800 queue_mask = gem_readl(macb, DCFG6) & 0xff;
803 for (i = 1; i < MACB_MAX_QUEUES; i++)
804 if (queue_mask & (1 << i))
807 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
808 macb->dummy_desc->addr = 0;
809 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
810 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
811 paddr = macb->dummy_desc_dma;
813 for (i = 1; i < num_queues; i++) {
814 gem_writel_queue_TBQP(macb, lower_32_bits(paddr), i - 1);
815 gem_writel_queue_RBQP(macb, lower_32_bits(paddr), i - 1);
816 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
817 gem_writel_queue_TBQPH(macb, upper_32_bits(paddr),
819 gem_writel_queue_RBQPH(macb, upper_32_bits(paddr),
826 static void gmac_configure_dma(struct macb_device *macb)
831 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
832 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
833 dmacfg |= GEM_BF(RXBS, buffer_size);
835 if (macb->config->dma_burst_length)
836 dmacfg = GEM_BFINS(FBLDO,
837 macb->config->dma_burst_length, dmacfg);
839 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
840 dmacfg &= ~GEM_BIT(ENDIA_PKT);
842 if (macb->is_big_endian)
843 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
845 dmacfg &= ~GEM_BIT(ENDIA_DESC);
847 dmacfg &= ~GEM_BIT(ADDR64);
848 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
849 dmacfg |= GEM_BIT(ADDR64);
851 gem_writel(macb, DMACFG, dmacfg);
855 static int _macb_init(struct udevice *dev, const char *name)
857 static int _macb_init(struct macb_device *macb, const char *name)
861 struct macb_device *macb = dev_get_priv(dev);
862 unsigned int val = 0;
870 * macb_halt should have been called at some point before now,
871 * so we'll assume the controller is idle.
874 /* initialize DMA descriptors */
875 paddr = macb->rx_buffer_dma;
876 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
877 if (i == (MACB_RX_RING_SIZE - 1))
878 paddr |= MACB_BIT(RX_WRAP);
879 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
883 macb->rx_ring[count].ctrl = 0;
884 macb_set_addr(macb, &macb->rx_ring[count], paddr);
885 paddr += macb->rx_buffer_size;
887 macb_flush_ring_desc(macb, RX);
888 macb_flush_rx_buffer(macb);
890 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
891 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
895 macb_set_addr(macb, &macb->tx_ring[count], 0);
896 if (i == (MACB_TX_RING_SIZE - 1))
897 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED) |
900 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED);
902 macb_flush_ring_desc(macb, TX);
907 macb->next_rx_tail = 0;
909 #ifdef CONFIG_MACB_ZYNQ
910 gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
913 macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
914 macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
915 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
916 macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
917 macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
920 if (macb_is_gem(macb)) {
921 /* Initialize DMA properties */
922 gmac_configure_dma(macb);
923 /* Check the multi queue and initialize the queue for tx */
924 gmac_init_multi_queues(macb);
927 * When the GMAC IP with GE feature, this bit is used to
928 * select interface between RGMII and GMII.
929 * When the GMAC IP without GE feature, this bit is used
930 * to select interface between RMII and MII.
933 if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII)
934 val = macb->config->usrio->rgmii;
935 else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
936 val = macb->config->usrio->rmii;
937 else if (macb->phy_interface == PHY_INTERFACE_MODE_MII)
938 val = macb->config->usrio->mii;
940 if (macb->config->caps & MACB_CAPS_USRIO_HAS_CLKEN)
941 val |= macb->config->usrio->clken;
943 gem_writel(macb, USRIO, val);
945 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
946 unsigned int ncfgr = macb_readl(macb, NCFGR);
948 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
949 macb_writel(macb, NCFGR, ncfgr);
952 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
953 gem_writel(macb, USRIO, macb->config->usrio->rgmii);
955 gem_writel(macb, USRIO, 0);
959 /* choose RMII or MII mode. This depends on the board */
961 #ifdef CONFIG_AT91FAMILY
962 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
963 macb_writel(macb, USRIO,
964 macb->config->usrio->rmii |
965 macb->config->usrio->clken);
967 macb_writel(macb, USRIO, macb->config->usrio->clken);
970 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
971 macb_writel(macb, USRIO, 0);
973 macb_writel(macb, USRIO, macb->config->usrio->mii);
977 #ifdef CONFIG_AT91FAMILY
978 macb_writel(macb, USRIO, macb->config->usrio->rmii |
979 macb->config->usrio->clken);
981 macb_writel(macb, USRIO, 0);
984 #ifdef CONFIG_AT91FAMILY
985 macb_writel(macb, USRIO, macb->config->usrio->clken);
987 macb_writel(macb, USRIO, macb->config->usrio->mii);
989 #endif /* CONFIG_RMII */
994 ret = macb_phy_init(dev, name);
996 ret = macb_phy_init(macb, name);
1001 /* Enable TX and RX */
1002 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
1007 static void _macb_halt(struct macb_device *macb)
1011 /* Halt the controller and wait for any ongoing transmission to end. */
1012 ncr = macb_readl(macb, NCR);
1013 ncr |= MACB_BIT(THALT);
1014 macb_writel(macb, NCR, ncr);
1017 tsr = macb_readl(macb, TSR);
1018 } while (tsr & MACB_BIT(TGO));
1020 /* Disable TX and RX, and clear statistics */
1021 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
1024 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
1029 /* set hardware address */
1030 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
1031 enetaddr[2] << 16 | enetaddr[3] << 24;
1032 macb_writel(macb, SA1B, hwaddr_bottom);
1033 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
1034 macb_writel(macb, SA1T, hwaddr_top);
1038 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
1041 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1042 unsigned long macb_hz = macb->pclk_rate;
1044 unsigned long macb_hz = get_macb_pclk_rate(id);
1047 if (macb_hz < 20000000)
1048 config = MACB_BF(CLK, MACB_CLK_DIV8);
1049 else if (macb_hz < 40000000)
1050 config = MACB_BF(CLK, MACB_CLK_DIV16);
1051 else if (macb_hz < 80000000)
1052 config = MACB_BF(CLK, MACB_CLK_DIV32);
1054 config = MACB_BF(CLK, MACB_CLK_DIV64);
1059 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
1063 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1064 unsigned long macb_hz = macb->pclk_rate;
1066 unsigned long macb_hz = get_macb_pclk_rate(id);
1069 if (macb_hz < 20000000)
1070 config = GEM_BF(CLK, GEM_CLK_DIV8);
1071 else if (macb_hz < 40000000)
1072 config = GEM_BF(CLK, GEM_CLK_DIV16);
1073 else if (macb_hz < 80000000)
1074 config = GEM_BF(CLK, GEM_CLK_DIV32);
1075 else if (macb_hz < 120000000)
1076 config = GEM_BF(CLK, GEM_CLK_DIV48);
1077 else if (macb_hz < 160000000)
1078 config = GEM_BF(CLK, GEM_CLK_DIV64);
1079 else if (macb_hz < 240000000)
1080 config = GEM_BF(CLK, GEM_CLK_DIV96);
1081 else if (macb_hz < 320000000)
1082 config = GEM_BF(CLK, GEM_CLK_DIV128);
1084 config = GEM_BF(CLK, GEM_CLK_DIV224);
1090 * Get the DMA bus width field of the network configuration register that we
1091 * should program. We find the width from decoding the design configuration
1092 * register to find the maximum supported data bus width.
1094 static u32 macb_dbw(struct macb_device *macb)
1096 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
1098 return GEM_BF(DBW, GEM_DBW128);
1100 return GEM_BF(DBW, GEM_DBW64);
1103 return GEM_BF(DBW, GEM_DBW32);
1107 static void _macb_eth_initialize(struct macb_device *macb)
1109 int id = 0; /* This is not used by functions we call */
1112 if (macb_is_gem(macb))
1113 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1115 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1117 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
1118 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1120 &macb->rx_buffer_dma);
1121 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
1122 &macb->rx_ring_dma);
1123 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
1124 &macb->tx_ring_dma);
1125 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1126 &macb->dummy_desc_dma);
1129 * Do some basic initialization so that we at least can talk
1132 if (macb_is_gem(macb)) {
1133 ncfgr = gem_mdc_clk_div(id, macb);
1134 ncfgr |= macb_dbw(macb);
1136 ncfgr = macb_mdc_clk_div(id, macb);
1139 macb_writel(macb, NCFGR, ncfgr);
1142 #ifndef CONFIG_DM_ETH
1143 static int macb_send(struct eth_device *netdev, void *packet, int length)
1145 struct macb_device *macb = to_macb(netdev);
1147 return _macb_send(macb, netdev->name, packet, length);
1150 static int macb_recv(struct eth_device *netdev)
1152 struct macb_device *macb = to_macb(netdev);
1156 macb->wrapped = false;
1158 macb->next_rx_tail = macb->rx_tail;
1159 length = _macb_recv(macb, &packet);
1161 net_process_received_packet(packet, length);
1162 reclaim_rx_buffers(macb, macb->next_rx_tail);
1169 static int macb_init(struct eth_device *netdev, struct bd_info *bd)
1171 struct macb_device *macb = to_macb(netdev);
1173 return _macb_init(macb, netdev->name);
1176 static void macb_halt(struct eth_device *netdev)
1178 struct macb_device *macb = to_macb(netdev);
1180 return _macb_halt(macb);
1183 static int macb_write_hwaddr(struct eth_device *netdev)
1185 struct macb_device *macb = to_macb(netdev);
1187 return _macb_write_hwaddr(macb, netdev->enetaddr);
1190 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1192 struct macb_device *macb;
1193 struct eth_device *netdev;
1195 macb = malloc(sizeof(struct macb_device));
1197 printf("Error: Failed to allocate memory for MACB%d\n", id);
1200 memset(macb, 0, sizeof(struct macb_device));
1202 netdev = &macb->netdev;
1205 macb->phy_addr = phy_addr;
1207 if (macb_is_gem(macb))
1208 sprintf(netdev->name, "gmac%d", id);
1210 sprintf(netdev->name, "macb%d", id);
1212 netdev->init = macb_init;
1213 netdev->halt = macb_halt;
1214 netdev->send = macb_send;
1215 netdev->recv = macb_recv;
1216 netdev->write_hwaddr = macb_write_hwaddr;
1218 _macb_eth_initialize(macb);
1220 eth_register(netdev);
1222 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1224 struct mii_dev *mdiodev = mdio_alloc();
1227 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1228 mdiodev->read = macb_miiphy_read;
1229 mdiodev->write = macb_miiphy_write;
1231 retval = mdio_register(mdiodev);
1234 macb->bus = miiphy_get_dev_by_name(netdev->name);
1238 #endif /* !CONFIG_DM_ETH */
1240 #ifdef CONFIG_DM_ETH
1242 static int macb_start(struct udevice *dev)
1244 return _macb_init(dev, dev->name);
1247 static int macb_send(struct udevice *dev, void *packet, int length)
1249 struct macb_device *macb = dev_get_priv(dev);
1251 return _macb_send(macb, dev->name, packet, length);
1254 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1256 struct macb_device *macb = dev_get_priv(dev);
1258 macb->next_rx_tail = macb->rx_tail;
1259 macb->wrapped = false;
1261 return _macb_recv(macb, packetp);
1264 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1266 struct macb_device *macb = dev_get_priv(dev);
1268 reclaim_rx_buffers(macb, macb->next_rx_tail);
1273 static void macb_stop(struct udevice *dev)
1275 struct macb_device *macb = dev_get_priv(dev);
1280 static int macb_write_hwaddr(struct udevice *dev)
1282 struct eth_pdata *plat = dev_get_plat(dev);
1283 struct macb_device *macb = dev_get_priv(dev);
1285 return _macb_write_hwaddr(macb, plat->enetaddr);
1288 static const struct eth_ops macb_eth_ops = {
1289 .start = macb_start,
1293 .free_pkt = macb_free_pkt,
1294 .write_hwaddr = macb_write_hwaddr,
1298 static int macb_enable_clk(struct udevice *dev)
1300 struct macb_device *macb = dev_get_priv(dev);
1305 ret = clk_get_by_index(dev, 0, &clk);
1310 * If clock driver didn't support enable or disable then
1311 * we get -ENOSYS from clk_enable(). To handle this, we
1312 * don't fail for ret == -ENOSYS.
1314 ret = clk_enable(&clk);
1315 if (ret && ret != -ENOSYS)
1318 clk_rate = clk_get_rate(&clk);
1322 macb->pclk_rate = clk_rate;
1328 static const struct macb_usrio_cfg macb_default_usrio = {
1329 .mii = MACB_BIT(MII),
1330 .rmii = MACB_BIT(RMII),
1331 .rgmii = GEM_BIT(RGMII),
1332 .clken = MACB_BIT(CLKEN),
1335 static const struct macb_config default_gem_config = {
1336 .dma_burst_length = 16,
1337 .hw_dma_cap = HW_DMA_CAP_32B,
1339 .usrio = &macb_default_usrio,
1342 static int macb_eth_probe(struct udevice *dev)
1344 struct eth_pdata *pdata = dev_get_plat(dev);
1345 struct macb_device *macb = dev_get_priv(dev);
1346 struct ofnode_phandle_args phandle_args;
1347 const char *phy_mode;
1350 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
1353 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1354 if (macb->phy_interface == -1) {
1355 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1359 /* Read phyaddr from DT */
1360 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1362 macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
1365 macb->regs = (void *)pdata->iobase;
1367 macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
1369 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1371 macb->config = &default_gem_config;
1374 ret = macb_enable_clk(dev);
1379 _macb_eth_initialize(macb);
1381 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1382 macb->bus = mdio_alloc();
1385 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1386 macb->bus->read = macb_miiphy_read;
1387 macb->bus->write = macb_miiphy_write;
1389 ret = mdio_register(macb->bus);
1392 macb->bus = miiphy_get_dev_by_name(dev->name);
1398 static int macb_eth_remove(struct udevice *dev)
1400 struct macb_device *macb = dev_get_priv(dev);
1402 #ifdef CONFIG_PHYLIB
1405 mdio_unregister(macb->bus);
1406 mdio_free(macb->bus);
1412 * macb_late_eth_of_to_plat
1413 * @dev: udevice struct
1414 * Returns 0 when operation success and negative errno number
1415 * when operation failed.
1417 int __weak macb_late_eth_of_to_plat(struct udevice *dev)
1422 static int macb_eth_of_to_plat(struct udevice *dev)
1424 struct eth_pdata *pdata = dev_get_plat(dev);
1426 pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
1430 return macb_late_eth_of_to_plat(dev);
1433 static const struct macb_config microchip_config = {
1434 .dma_burst_length = 16,
1435 .hw_dma_cap = HW_DMA_CAP_64B,
1437 .usrio = &macb_default_usrio,
1440 static const struct macb_config sama5d4_config = {
1441 .dma_burst_length = 4,
1442 .hw_dma_cap = HW_DMA_CAP_32B,
1444 .usrio = &macb_default_usrio,
1447 static const struct macb_config sifive_config = {
1448 .dma_burst_length = 16,
1449 .hw_dma_cap = HW_DMA_CAP_32B,
1450 .clk_init = macb_sifive_clk_init,
1451 .usrio = &macb_default_usrio,
1454 static const struct udevice_id macb_eth_ids[] = {
1455 { .compatible = "cdns,macb" },
1456 { .compatible = "cdns,at91sam9260-macb" },
1457 { .compatible = "cdns,sam9x60-macb" },
1458 { .compatible = "atmel,sama5d2-gem" },
1459 { .compatible = "atmel,sama5d3-gem" },
1460 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1461 { .compatible = "cdns,zynq-gem" },
1462 { .compatible = "sifive,fu540-c000-gem",
1463 .data = (ulong)&sifive_config },
1464 { .compatible = "microchip,mpfs-mss-gem",
1465 .data = (ulong)µchip_config },
1469 U_BOOT_DRIVER(eth_macb) = {
1472 .of_match = macb_eth_ids,
1473 .of_to_plat = macb_eth_of_to_plat,
1474 .probe = macb_eth_probe,
1475 .remove = macb_eth_remove,
1476 .ops = &macb_eth_ops,
1477 .priv_auto = sizeof(struct macb_device),
1478 .plat_auto = sizeof(struct eth_pdata),