1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2005-2006 Atmel Corporation
10 #include <asm/global_data.h>
11 #include <linux/delay.h>
14 * The u-boot networking stack is a little weird. It seems like the
15 * networking core allocates receive buffers up front without any
16 * regard to the hardware that's supposed to actually receive those
19 * The MACB receives packets into 128-byte receive buffers, so the
20 * buffers allocated by the core isn't very practical to use. We'll
21 * allocate our own, but we need one such buffer in case a packet
22 * wraps around the DMA ring so that we have to copy it.
24 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
25 * configuration header. This way, the core allocates one RX buffer
26 * and one TX buffer, each of which can hold a ethernet packet of
29 * For some reason, the networking core unconditionally specifies a
30 * 32-byte packet "alignment" (which really should be called
31 * "padding"). MACB shouldn't need that, but we'll refrain from any
32 * core modifications here...
42 #include <linux/mii.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/arch/clk.h>
46 #include <linux/errno.h>
50 DECLARE_GLOBAL_DATA_PTR;
53 * These buffer sizes must be power of 2 and divisible
54 * by RX_BUFFER_MULTIPLE
56 #define MACB_RX_BUFFER_SIZE 128
57 #define GEM_RX_BUFFER_SIZE 2048
58 #define RX_BUFFER_MULTIPLE 64
60 #define MACB_RX_RING_SIZE 32
61 #define MACB_TX_RING_SIZE 16
63 #define MACB_TX_TIMEOUT 1000
64 #define MACB_AUTONEG_TIMEOUT 5000000
66 #ifdef CONFIG_MACB_ZYNQ
67 /* INCR4 AHB bursts */
68 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
69 /* Use full configured addressable space (8 Kb) */
70 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
71 /* Use full configured addressable space (4 Kb) */
72 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
73 /* Set RXBUF with use of 128 byte */
74 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
75 #define MACB_ZYNQ_GEM_DMACR_INIT \
76 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
77 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
78 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
79 MACB_ZYNQ_GEM_DMACR_RXBUF)
82 struct macb_dma_desc {
87 struct macb_dma_desc_64 {
92 #define HW_DMA_CAP_32B 0
93 #define HW_DMA_CAP_64B 1
95 #define DMA_DESC_SIZE 16
96 #define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
97 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
98 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
99 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
101 #define DESC_PER_CACHELINE_32 (ARCH_DMA_MINALIGN/sizeof(struct macb_dma_desc))
102 #define DESC_PER_CACHELINE_64 (ARCH_DMA_MINALIGN/DMA_DESC_SIZE)
104 #define RXBUF_FRMLEN_MASK 0x00000fff
105 #define TXBUF_FRMLEN_MASK 0x000007ff
112 const struct macb_config *config;
114 unsigned int rx_tail;
115 unsigned int tx_head;
116 unsigned int tx_tail;
117 unsigned int next_rx_tail;
122 struct macb_dma_desc *rx_ring;
123 struct macb_dma_desc *tx_ring;
124 size_t rx_buffer_size;
126 unsigned long rx_buffer_dma;
127 unsigned long rx_ring_dma;
128 unsigned long tx_ring_dma;
130 struct macb_dma_desc *dummy_desc;
131 unsigned long dummy_desc_dma;
133 const struct device *dev;
134 #ifndef CONFIG_DM_ETH
135 struct eth_device netdev;
137 unsigned short phy_addr;
140 struct phy_device *phydev;
145 unsigned long pclk_rate;
147 phy_interface_t phy_interface;
151 struct macb_usrio_cfg {
159 unsigned int dma_burst_length;
160 unsigned int hw_dma_cap;
163 int (*clk_init)(struct udevice *dev, ulong rate);
164 const struct macb_usrio_cfg *usrio;
167 #ifndef CONFIG_DM_ETH
168 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
171 static int macb_is_gem(struct macb_device *macb)
173 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
176 #ifndef cpu_is_sama5d2
177 #define cpu_is_sama5d2() 0
180 #ifndef cpu_is_sama5d4
181 #define cpu_is_sama5d4() 0
184 static int gem_is_gigabit_capable(struct macb_device *macb)
187 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
188 * configured to support only 10/100.
190 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
193 static void macb_mdio_write(struct macb_device *macb, u8 phy_adr, u8 reg,
196 unsigned long netctl;
197 unsigned long netstat;
200 netctl = macb_readl(macb, NCR);
201 netctl |= MACB_BIT(MPE);
202 macb_writel(macb, NCR, netctl);
204 frame = (MACB_BF(SOF, 1)
206 | MACB_BF(PHYA, phy_adr)
209 | MACB_BF(DATA, value));
210 macb_writel(macb, MAN, frame);
213 netstat = macb_readl(macb, NSR);
214 } while (!(netstat & MACB_BIT(IDLE)));
216 netctl = macb_readl(macb, NCR);
217 netctl &= ~MACB_BIT(MPE);
218 macb_writel(macb, NCR, netctl);
221 static u16 macb_mdio_read(struct macb_device *macb, u8 phy_adr, u8 reg)
223 unsigned long netctl;
224 unsigned long netstat;
227 netctl = macb_readl(macb, NCR);
228 netctl |= MACB_BIT(MPE);
229 macb_writel(macb, NCR, netctl);
231 frame = (MACB_BF(SOF, 1)
233 | MACB_BF(PHYA, phy_adr)
236 macb_writel(macb, MAN, frame);
239 netstat = macb_readl(macb, NSR);
240 } while (!(netstat & MACB_BIT(IDLE)));
242 frame = macb_readl(macb, MAN);
244 netctl = macb_readl(macb, NCR);
245 netctl &= ~MACB_BIT(MPE);
246 macb_writel(macb, NCR, netctl);
248 return MACB_BFEXT(DATA, frame);
251 void __weak arch_get_mdio_control(const char *name)
256 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
258 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
262 struct udevice *dev = eth_get_dev_by_name(bus->name);
263 struct macb_device *macb = dev_get_priv(dev);
265 struct eth_device *dev = eth_get_dev_by_name(bus->name);
266 struct macb_device *macb = to_macb(dev);
269 arch_get_mdio_control(bus->name);
270 value = macb_mdio_read(macb, phy_adr, reg);
275 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
279 struct udevice *dev = eth_get_dev_by_name(bus->name);
280 struct macb_device *macb = dev_get_priv(dev);
282 struct eth_device *dev = eth_get_dev_by_name(bus->name);
283 struct macb_device *macb = to_macb(dev);
286 arch_get_mdio_control(bus->name);
287 macb_mdio_write(macb, phy_adr, reg, value);
295 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
298 invalidate_dcache_range(macb->rx_ring_dma,
299 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
302 invalidate_dcache_range(macb->tx_ring_dma,
303 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
307 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
310 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
311 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
313 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
314 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
317 static inline void macb_flush_rx_buffer(struct macb_device *macb)
319 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
320 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
324 static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
326 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
327 ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
331 #if defined(CONFIG_CMD_NET)
333 static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
335 return (struct macb_dma_desc_64 *)((void *)desc
336 + sizeof(struct macb_dma_desc));
339 static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
342 struct macb_dma_desc_64 *desc_64;
344 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
345 desc_64 = macb_64b_desc(desc);
346 desc_64->addrh = upper_32_bits(addr);
348 desc->addr = lower_32_bits(addr);
351 static int _macb_send(struct macb_device *macb, const char *name, void *packet,
354 unsigned long paddr, ctrl;
355 unsigned int tx_head = macb->tx_head;
358 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
360 ctrl = length & TXBUF_FRMLEN_MASK;
361 ctrl |= MACB_BIT(TX_LAST);
362 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
363 ctrl |= MACB_BIT(TX_WRAP);
369 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
370 tx_head = tx_head * 2;
372 macb->tx_ring[tx_head].ctrl = ctrl;
373 macb_set_addr(macb, &macb->tx_ring[tx_head], paddr);
376 macb_flush_ring_desc(macb, TX);
377 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
380 * I guess this is necessary because the networking core may
381 * re-use the transmit buffer as soon as we return...
383 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
385 macb_invalidate_ring_desc(macb, TX);
386 ctrl = macb->tx_ring[tx_head].ctrl;
387 if (ctrl & MACB_BIT(TX_USED))
392 dma_unmap_single(paddr, length, DMA_TO_DEVICE);
394 if (i <= MACB_TX_TIMEOUT) {
395 if (ctrl & MACB_BIT(TX_UNDERRUN))
396 printf("%s: TX underrun\n", name);
397 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
398 printf("%s: TX buffers exhausted in mid frame\n", name);
400 printf("%s: TX timeout\n", name);
403 /* No one cares anyway */
407 static void reclaim_rx_buffer(struct macb_device *macb,
415 * There may be multiple descriptors per CPU cacheline,
416 * so a cache flush would flush the whole line, meaning the content of other descriptors
417 * in the cacheline would also flush. If one of the other descriptors had been
418 * written to by the controller, the flush would cause those changes to be lost.
420 * To circumvent this issue, we do the actual freeing only when we need to free
421 * the last descriptor in the current cacheline. When the current descriptor is the
422 * last in the cacheline, we free all the descriptors that belong to that cacheline.
424 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
425 mask = DESC_PER_CACHELINE_64 - 1;
428 mask = DESC_PER_CACHELINE_32 - 1;
432 /* we exit without freeing if idx is not the last descriptor in the cacheline */
433 if ((idx & mask) != mask)
436 for (i = idx & (~mask); i <= idx; i++)
437 macb->rx_ring[i << shift].addr &= ~MACB_BIT(RX_USED);
440 static void reclaim_rx_buffers(struct macb_device *macb,
441 unsigned int new_tail)
447 macb_invalidate_ring_desc(macb, RX);
448 while (i > new_tail) {
449 reclaim_rx_buffer(macb, i);
451 if (i >= MACB_RX_RING_SIZE)
455 while (i < new_tail) {
456 reclaim_rx_buffer(macb, i);
461 macb_flush_ring_desc(macb, RX);
462 macb->rx_tail = new_tail;
465 static int _macb_recv(struct macb_device *macb, uchar **packetp)
467 unsigned int next_rx_tail = macb->next_rx_tail;
473 macb->wrapped = false;
475 macb_invalidate_ring_desc(macb, RX);
477 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
478 next_rx_tail = next_rx_tail * 2;
480 if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
483 status = macb->rx_ring[next_rx_tail].ctrl;
484 if (status & MACB_BIT(RX_SOF)) {
485 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
486 next_rx_tail = next_rx_tail / 2;
490 if (next_rx_tail != macb->rx_tail)
491 reclaim_rx_buffers(macb, next_rx_tail);
492 macb->wrapped = false;
495 if (status & MACB_BIT(RX_EOF)) {
496 buffer = macb->rx_buffer +
497 macb->rx_buffer_size * macb->rx_tail;
498 length = status & RXBUF_FRMLEN_MASK;
500 macb_invalidate_rx_buffer(macb);
502 unsigned int headlen, taillen;
504 headlen = macb->rx_buffer_size *
505 (MACB_RX_RING_SIZE - macb->rx_tail);
506 taillen = length - headlen;
507 memcpy((void *)net_rx_packets[0],
509 memcpy((void *)net_rx_packets[0] + headlen,
510 macb->rx_buffer, taillen);
511 *packetp = (void *)net_rx_packets[0];
516 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
518 next_rx_tail = next_rx_tail / 2;
521 if (++next_rx_tail >= MACB_RX_RING_SIZE)
523 macb->next_rx_tail = next_rx_tail;
526 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
528 next_rx_tail = next_rx_tail / 2;
532 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
533 macb->wrapped = true;
541 static void macb_phy_reset(struct macb_device *macb, const char *name)
546 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
547 macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv);
548 printf("%s: Starting autonegotiation...\n", name);
549 macb_mdio_write(macb, macb->phy_addr, MII_BMCR, (BMCR_ANENABLE
552 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
553 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
554 if (status & BMSR_ANEGCOMPLETE)
559 if (status & BMSR_ANEGCOMPLETE)
560 printf("%s: Autonegotiation complete\n", name);
562 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
566 static int macb_phy_find(struct macb_device *macb, const char *name)
571 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
572 if (phy_id != 0xffff) {
573 printf("%s: PHY present at %d\n", name, macb->phy_addr);
577 /* Search for PHY... */
578 for (i = 0; i < 32; i++) {
580 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
581 if (phy_id != 0xffff) {
582 printf("%s: PHY present at %d\n", name, i);
587 /* PHY isn't up to snuff */
588 printf("%s: PHY not found\n", name);
594 * macb_linkspd_cb - Linkspeed change callback function
595 * @dev/@regs: MACB udevice (DM version) or
596 * Base Register of MACB devices (non-DM version)
598 * Returns 0 when operation success and negative errno number
599 * when operation failed.
602 static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
606 gemgxl_regs = dev_read_addr_index_ptr(dev, 1);
611 * SiFive GEMGXL TX clock operation mode:
613 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
614 * and output clock on GMII output signal GTX_CLK
615 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
617 writel(rate != 125000000, gemgxl_regs);
621 static int macb_sama7g5_clk_init(struct udevice *dev, ulong rate)
626 ret = clk_get_by_name(dev, "tx_clk", &clk);
631 * This is for using GCK. Clock rate is addressed via assigned-clock
632 * property, so only clock enable is needed here. The switching to
633 * proper clock rate depending on link speed is managed by IP logic.
635 return clk_enable(&clk);
638 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
641 struct macb_device *macb = dev_get_priv(dev);
648 rate = 2500000; /* 2.5 MHz */
651 rate = 25000000; /* 25 MHz */
654 rate = 125000000; /* 125 MHz */
657 /* does not change anything */
661 if (macb->config->clk_init)
662 return macb->config->clk_init(dev, rate);
665 * "tx_clk" is an optional clock source for MACB.
666 * Ignore if it does not exist in DT.
668 ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
673 ret = clk_set_rate(&tx_clk, rate);
682 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
689 static int macb_phy_init(struct udevice *dev, const char *name)
691 static int macb_phy_init(struct macb_device *macb, const char *name)
695 struct macb_device *macb = dev_get_priv(dev);
698 u16 phy_id, status, adv, lpa;
699 int media, speed, duplex;
703 arch_get_mdio_control(name);
704 /* Auto-detect phy_addr */
705 ret = macb_phy_find(macb, name);
709 /* Check if the PHY is up to snuff... */
710 phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
711 if (phy_id == 0xffff) {
712 printf("%s: No PHY present\n", name);
718 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
719 macb->phy_interface);
721 /* need to consider other phy interface mode */
722 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
723 PHY_INTERFACE_MODE_RGMII);
726 printf("phy_connect failed\n");
730 phy_config(macb->phydev);
733 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
734 if (!(status & BMSR_LSTATUS)) {
735 /* Try to re-negotiate if we don't have link already. */
736 macb_phy_reset(macb, name);
738 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
739 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR);
740 if (status & BMSR_LSTATUS) {
742 * Delay a bit after the link is established,
743 * so that the next xfer does not fail
752 if (!(status & BMSR_LSTATUS)) {
753 printf("%s: link down (status: 0x%04x)\n",
758 /* First check for GMAC and that it is GiB capable */
759 if (gem_is_gigabit_capable(macb)) {
760 lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000);
762 if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
764 duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
767 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
769 duplex ? "full" : "half",
772 ncfgr = macb_readl(macb, NCFGR);
773 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
774 ncfgr |= GEM_BIT(GBE);
777 ncfgr |= MACB_BIT(FD);
779 macb_writel(macb, NCFGR, ncfgr);
782 ret = macb_linkspd_cb(dev, _1000BASET);
784 ret = macb_linkspd_cb(macb->regs, _1000BASET);
793 /* fall back for EMAC checking */
794 adv = macb_mdio_read(macb, macb->phy_addr, MII_ADVERTISE);
795 lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA);
796 media = mii_nway_result(lpa & adv);
797 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
799 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
800 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
802 speed ? "100" : "10",
803 duplex ? "full" : "half",
806 ncfgr = macb_readl(macb, NCFGR);
807 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
809 ncfgr |= MACB_BIT(SPD);
811 ret = macb_linkspd_cb(dev, _100BASET);
813 ret = macb_linkspd_cb(macb->regs, _100BASET);
817 ret = macb_linkspd_cb(dev, _10BASET);
819 ret = macb_linkspd_cb(macb->regs, _10BASET);
827 ncfgr |= MACB_BIT(FD);
828 macb_writel(macb, NCFGR, ncfgr);
833 static int gmac_init_multi_queues(struct macb_device *macb)
835 int i, num_queues = 1;
839 /* bit 0 is never set but queue 0 always exists */
840 queue_mask = gem_readl(macb, DCFG6) & 0xff;
843 for (i = 1; i < MACB_MAX_QUEUES; i++)
844 if (queue_mask & (1 << i))
847 macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
848 macb->dummy_desc->addr = 0;
849 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
850 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
851 paddr = macb->dummy_desc_dma;
853 for (i = 1; i < num_queues; i++) {
854 gem_writel_queue_TBQP(macb, lower_32_bits(paddr), i - 1);
855 gem_writel_queue_RBQP(macb, lower_32_bits(paddr), i - 1);
856 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
857 gem_writel_queue_TBQPH(macb, upper_32_bits(paddr),
859 gem_writel_queue_RBQPH(macb, upper_32_bits(paddr),
866 static void gmac_configure_dma(struct macb_device *macb)
871 buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
872 dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
873 dmacfg |= GEM_BF(RXBS, buffer_size);
875 if (macb->config->dma_burst_length)
876 dmacfg = GEM_BFINS(FBLDO,
877 macb->config->dma_burst_length, dmacfg);
879 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
880 dmacfg &= ~GEM_BIT(ENDIA_PKT);
882 if (macb->is_big_endian)
883 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
885 dmacfg &= ~GEM_BIT(ENDIA_DESC);
887 dmacfg &= ~GEM_BIT(ADDR64);
888 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
889 dmacfg |= GEM_BIT(ADDR64);
891 gem_writel(macb, DMACFG, dmacfg);
895 static int _macb_init(struct udevice *dev, const char *name)
897 static int _macb_init(struct macb_device *macb, const char *name)
901 struct macb_device *macb = dev_get_priv(dev);
902 unsigned int val = 0;
910 * macb_halt should have been called at some point before now,
911 * so we'll assume the controller is idle.
914 /* initialize DMA descriptors */
915 paddr = macb->rx_buffer_dma;
916 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
917 if (i == (MACB_RX_RING_SIZE - 1))
918 paddr |= MACB_BIT(RX_WRAP);
919 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
923 macb->rx_ring[count].ctrl = 0;
924 macb_set_addr(macb, &macb->rx_ring[count], paddr);
925 paddr += macb->rx_buffer_size;
927 macb_flush_ring_desc(macb, RX);
928 macb_flush_rx_buffer(macb);
930 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
931 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
935 macb_set_addr(macb, &macb->tx_ring[count], 0);
936 if (i == (MACB_TX_RING_SIZE - 1))
937 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED) |
940 macb->tx_ring[count].ctrl = MACB_BIT(TX_USED);
942 macb_flush_ring_desc(macb, TX);
947 macb->next_rx_tail = 0;
949 #ifdef CONFIG_MACB_ZYNQ
950 gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
953 macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
954 macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
955 if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
956 macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
957 macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
960 if (macb_is_gem(macb)) {
961 /* Initialize DMA properties */
962 gmac_configure_dma(macb);
963 /* Check the multi queue and initialize the queue for tx */
964 gmac_init_multi_queues(macb);
967 * When the GMAC IP with GE feature, this bit is used to
968 * select interface between RGMII and GMII.
969 * When the GMAC IP without GE feature, this bit is used
970 * to select interface between RMII and MII.
973 if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII ||
974 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
975 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
976 macb->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
977 val = macb->config->usrio->rgmii;
978 else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
979 val = macb->config->usrio->rmii;
980 else if (macb->phy_interface == PHY_INTERFACE_MODE_MII)
981 val = macb->config->usrio->mii;
983 if (macb->config->caps & MACB_CAPS_USRIO_HAS_CLKEN)
984 val |= macb->config->usrio->clken;
986 gem_writel(macb, USRIO, val);
988 if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
989 unsigned int ncfgr = macb_readl(macb, NCFGR);
991 ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
992 macb_writel(macb, NCFGR, ncfgr);
995 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
996 gem_writel(macb, USRIO, macb->config->usrio->rgmii);
998 gem_writel(macb, USRIO, 0);
1002 /* choose RMII or MII mode. This depends on the board */
1003 #ifdef CONFIG_DM_ETH
1004 #ifdef CONFIG_AT91FAMILY
1005 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
1006 macb_writel(macb, USRIO,
1007 macb->config->usrio->rmii |
1008 macb->config->usrio->clken);
1010 macb_writel(macb, USRIO, macb->config->usrio->clken);
1013 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
1014 macb_writel(macb, USRIO, 0);
1016 macb_writel(macb, USRIO, macb->config->usrio->mii);
1020 #ifdef CONFIG_AT91FAMILY
1021 macb_writel(macb, USRIO, macb->config->usrio->rmii |
1022 macb->config->usrio->clken);
1024 macb_writel(macb, USRIO, 0);
1027 #ifdef CONFIG_AT91FAMILY
1028 macb_writel(macb, USRIO, macb->config->usrio->clken);
1030 macb_writel(macb, USRIO, macb->config->usrio->mii);
1032 #endif /* CONFIG_RMII */
1036 #ifdef CONFIG_DM_ETH
1037 ret = macb_phy_init(dev, name);
1039 ret = macb_phy_init(macb, name);
1044 /* Enable TX and RX */
1045 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
1050 static void _macb_halt(struct macb_device *macb)
1054 /* Halt the controller and wait for any ongoing transmission to end. */
1055 ncr = macb_readl(macb, NCR);
1056 ncr |= MACB_BIT(THALT);
1057 macb_writel(macb, NCR, ncr);
1060 tsr = macb_readl(macb, TSR);
1061 } while (tsr & MACB_BIT(TGO));
1063 /* Disable TX and RX, and clear statistics */
1064 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
1067 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
1072 /* set hardware address */
1073 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
1074 enetaddr[2] << 16 | enetaddr[3] << 24;
1075 macb_writel(macb, SA1B, hwaddr_bottom);
1076 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
1077 macb_writel(macb, SA1T, hwaddr_top);
1081 static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
1084 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1085 unsigned long macb_hz = macb->pclk_rate;
1087 unsigned long macb_hz = get_macb_pclk_rate(id);
1090 if (macb_hz < 20000000)
1091 config = MACB_BF(CLK, MACB_CLK_DIV8);
1092 else if (macb_hz < 40000000)
1093 config = MACB_BF(CLK, MACB_CLK_DIV16);
1094 else if (macb_hz < 80000000)
1095 config = MACB_BF(CLK, MACB_CLK_DIV32);
1097 config = MACB_BF(CLK, MACB_CLK_DIV64);
1102 static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
1106 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
1107 unsigned long macb_hz = macb->pclk_rate;
1109 unsigned long macb_hz = get_macb_pclk_rate(id);
1112 if (macb_hz < 20000000)
1113 config = GEM_BF(CLK, GEM_CLK_DIV8);
1114 else if (macb_hz < 40000000)
1115 config = GEM_BF(CLK, GEM_CLK_DIV16);
1116 else if (macb_hz < 80000000)
1117 config = GEM_BF(CLK, GEM_CLK_DIV32);
1118 else if (macb_hz < 120000000)
1119 config = GEM_BF(CLK, GEM_CLK_DIV48);
1120 else if (macb_hz < 160000000)
1121 config = GEM_BF(CLK, GEM_CLK_DIV64);
1122 else if (macb_hz < 240000000)
1123 config = GEM_BF(CLK, GEM_CLK_DIV96);
1124 else if (macb_hz < 320000000)
1125 config = GEM_BF(CLK, GEM_CLK_DIV128);
1127 config = GEM_BF(CLK, GEM_CLK_DIV224);
1133 * Get the DMA bus width field of the network configuration register that we
1134 * should program. We find the width from decoding the design configuration
1135 * register to find the maximum supported data bus width.
1137 static u32 macb_dbw(struct macb_device *macb)
1139 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
1141 return GEM_BF(DBW, GEM_DBW128);
1143 return GEM_BF(DBW, GEM_DBW64);
1146 return GEM_BF(DBW, GEM_DBW32);
1150 static void _macb_eth_initialize(struct macb_device *macb)
1152 int id = 0; /* This is not used by functions we call */
1155 if (macb_is_gem(macb))
1156 macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
1158 macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1160 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
1161 macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
1163 &macb->rx_buffer_dma);
1164 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
1165 &macb->rx_ring_dma);
1166 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
1167 &macb->tx_ring_dma);
1168 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
1169 &macb->dummy_desc_dma);
1172 * Do some basic initialization so that we at least can talk
1175 if (macb_is_gem(macb)) {
1176 ncfgr = gem_mdc_clk_div(id, macb);
1177 ncfgr |= macb_dbw(macb);
1179 ncfgr = macb_mdc_clk_div(id, macb);
1182 macb_writel(macb, NCFGR, ncfgr);
1185 #ifndef CONFIG_DM_ETH
1186 static int macb_send(struct eth_device *netdev, void *packet, int length)
1188 struct macb_device *macb = to_macb(netdev);
1190 return _macb_send(macb, netdev->name, packet, length);
1193 static int macb_recv(struct eth_device *netdev)
1195 struct macb_device *macb = to_macb(netdev);
1199 macb->wrapped = false;
1201 macb->next_rx_tail = macb->rx_tail;
1202 length = _macb_recv(macb, &packet);
1204 net_process_received_packet(packet, length);
1205 reclaim_rx_buffers(macb, macb->next_rx_tail);
1212 static int macb_init(struct eth_device *netdev, struct bd_info *bd)
1214 struct macb_device *macb = to_macb(netdev);
1216 return _macb_init(macb, netdev->name);
1219 static void macb_halt(struct eth_device *netdev)
1221 struct macb_device *macb = to_macb(netdev);
1223 return _macb_halt(macb);
1226 static int macb_write_hwaddr(struct eth_device *netdev)
1228 struct macb_device *macb = to_macb(netdev);
1230 return _macb_write_hwaddr(macb, netdev->enetaddr);
1233 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
1235 struct macb_device *macb;
1236 struct eth_device *netdev;
1238 macb = malloc(sizeof(struct macb_device));
1240 printf("Error: Failed to allocate memory for MACB%d\n", id);
1243 memset(macb, 0, sizeof(struct macb_device));
1245 netdev = &macb->netdev;
1248 macb->phy_addr = phy_addr;
1250 if (macb_is_gem(macb))
1251 sprintf(netdev->name, "gmac%d", id);
1253 sprintf(netdev->name, "macb%d", id);
1255 netdev->init = macb_init;
1256 netdev->halt = macb_halt;
1257 netdev->send = macb_send;
1258 netdev->recv = macb_recv;
1259 netdev->write_hwaddr = macb_write_hwaddr;
1261 _macb_eth_initialize(macb);
1263 eth_register(netdev);
1265 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1267 struct mii_dev *mdiodev = mdio_alloc();
1270 strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
1271 mdiodev->read = macb_miiphy_read;
1272 mdiodev->write = macb_miiphy_write;
1274 retval = mdio_register(mdiodev);
1277 macb->bus = miiphy_get_dev_by_name(netdev->name);
1281 #endif /* !CONFIG_DM_ETH */
1283 #ifdef CONFIG_DM_ETH
1285 static int macb_start(struct udevice *dev)
1287 return _macb_init(dev, dev->name);
1290 static int macb_send(struct udevice *dev, void *packet, int length)
1292 struct macb_device *macb = dev_get_priv(dev);
1294 return _macb_send(macb, dev->name, packet, length);
1297 static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1299 struct macb_device *macb = dev_get_priv(dev);
1301 macb->next_rx_tail = macb->rx_tail;
1302 macb->wrapped = false;
1304 return _macb_recv(macb, packetp);
1307 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1309 struct macb_device *macb = dev_get_priv(dev);
1311 reclaim_rx_buffers(macb, macb->next_rx_tail);
1316 static void macb_stop(struct udevice *dev)
1318 struct macb_device *macb = dev_get_priv(dev);
1323 static int macb_write_hwaddr(struct udevice *dev)
1325 struct eth_pdata *plat = dev_get_plat(dev);
1326 struct macb_device *macb = dev_get_priv(dev);
1328 return _macb_write_hwaddr(macb, plat->enetaddr);
1331 static const struct eth_ops macb_eth_ops = {
1332 .start = macb_start,
1336 .free_pkt = macb_free_pkt,
1337 .write_hwaddr = macb_write_hwaddr,
1341 static int macb_enable_clk(struct udevice *dev)
1343 struct macb_device *macb = dev_get_priv(dev);
1348 ret = clk_get_by_index(dev, 0, &clk);
1353 * If clock driver didn't support enable or disable then
1354 * we get -ENOSYS from clk_enable(). To handle this, we
1355 * don't fail for ret == -ENOSYS.
1357 ret = clk_enable(&clk);
1358 if (ret && ret != -ENOSYS)
1361 clk_rate = clk_get_rate(&clk);
1365 macb->pclk_rate = clk_rate;
1371 static const struct macb_usrio_cfg macb_default_usrio = {
1372 .mii = MACB_BIT(MII),
1373 .rmii = MACB_BIT(RMII),
1374 .rgmii = GEM_BIT(RGMII),
1375 .clken = MACB_BIT(CLKEN),
1378 static struct macb_config default_gem_config = {
1379 .dma_burst_length = 16,
1380 .hw_dma_cap = HW_DMA_CAP_32B,
1382 .usrio = &macb_default_usrio,
1385 static int macb_eth_probe(struct udevice *dev)
1387 struct eth_pdata *pdata = dev_get_plat(dev);
1388 struct macb_device *macb = dev_get_priv(dev);
1389 struct ofnode_phandle_args phandle_args;
1392 macb->phy_interface = dev_read_phy_mode(dev);
1393 if (macb->phy_interface == PHY_INTERFACE_MODE_NA)
1396 /* Read phyaddr from DT */
1397 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1399 macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
1402 macb->regs = (void *)(uintptr_t)pdata->iobase;
1404 macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
1406 macb->config = (struct macb_config *)dev_get_driver_data(dev);
1407 if (!macb->config) {
1408 if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT)) {
1409 if (GEM_BFEXT(DAW64, gem_readl(macb, DCFG6)))
1410 default_gem_config.hw_dma_cap = HW_DMA_CAP_64B;
1412 macb->config = &default_gem_config;
1416 ret = macb_enable_clk(dev);
1421 _macb_eth_initialize(macb);
1423 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
1424 macb->bus = mdio_alloc();
1427 strlcpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1428 macb->bus->read = macb_miiphy_read;
1429 macb->bus->write = macb_miiphy_write;
1431 ret = mdio_register(macb->bus);
1434 macb->bus = miiphy_get_dev_by_name(dev->name);
1440 static int macb_eth_remove(struct udevice *dev)
1442 struct macb_device *macb = dev_get_priv(dev);
1444 #ifdef CONFIG_PHYLIB
1447 mdio_unregister(macb->bus);
1448 mdio_free(macb->bus);
1454 * macb_late_eth_of_to_plat
1455 * @dev: udevice struct
1456 * Returns 0 when operation success and negative errno number
1457 * when operation failed.
1459 int __weak macb_late_eth_of_to_plat(struct udevice *dev)
1464 static int macb_eth_of_to_plat(struct udevice *dev)
1466 struct eth_pdata *pdata = dev_get_plat(dev);
1468 pdata->iobase = (uintptr_t)dev_remap_addr(dev);
1472 return macb_late_eth_of_to_plat(dev);
1475 static const struct macb_usrio_cfg sama7g5_usrio = {
1482 static const struct macb_config sama5d4_config = {
1483 .dma_burst_length = 4,
1484 .hw_dma_cap = HW_DMA_CAP_32B,
1486 .usrio = &macb_default_usrio,
1489 static const struct macb_config sifive_config = {
1490 .dma_burst_length = 16,
1491 .hw_dma_cap = HW_DMA_CAP_32B,
1492 .clk_init = macb_sifive_clk_init,
1493 .usrio = &macb_default_usrio,
1496 static const struct macb_config sama7g5_gmac_config = {
1497 .dma_burst_length = 16,
1498 .hw_dma_cap = HW_DMA_CAP_32B,
1499 .clk_init = macb_sama7g5_clk_init,
1500 .usrio = &sama7g5_usrio,
1503 static const struct macb_config sama7g5_emac_config = {
1504 .caps = MACB_CAPS_USRIO_HAS_CLKEN,
1505 .dma_burst_length = 16,
1506 .hw_dma_cap = HW_DMA_CAP_32B,
1507 .usrio = &sama7g5_usrio,
1510 static const struct udevice_id macb_eth_ids[] = {
1511 { .compatible = "cdns,macb" },
1512 { .compatible = "cdns,at91sam9260-macb" },
1513 { .compatible = "cdns,sam9x60-macb" },
1514 { .compatible = "cdns,sama7g5-gem",
1515 .data = (ulong)&sama7g5_gmac_config },
1516 { .compatible = "cdns,sama7g5-emac",
1517 .data = (ulong)&sama7g5_emac_config },
1518 { .compatible = "atmel,sama5d2-gem" },
1519 { .compatible = "atmel,sama5d3-gem" },
1520 { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
1521 { .compatible = "cdns,zynq-gem" },
1522 { .compatible = "sifive,fu540-c000-gem",
1523 .data = (ulong)&sifive_config },
1527 U_BOOT_DRIVER(eth_macb) = {
1530 .of_match = macb_eth_ids,
1531 .of_to_plat = macb_eth_of_to_plat,
1532 .probe = macb_eth_probe,
1533 .remove = macb_eth_remove,
1534 .ops = &macb_eth_ops,
1535 .priv_auto = sizeof(struct macb_device),
1536 .plat_auto = sizeof(struct eth_pdata),