1 // SPDX-License-Identifier: GPL-2.0+
7 #include <fsl-mc/ldpaa_wriop.h>
9 #include <asm/arch/fsl_serdes.h>
10 #include <asm/arch/soc.h>
11 #include <linux/mii.h>
13 u32 dpmac_to_devdisr[] = {
14 [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
15 [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
16 [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
17 [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
18 [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
19 [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
20 [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
21 [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
22 [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
23 [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
24 [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
25 [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
26 [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
27 [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
28 [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
29 [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
30 [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
31 [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
34 static int is_device_disabled(int dpmac_id)
36 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
37 u32 devdisr2 = in_le32(&gur->devdisr2);
39 return dpmac_to_devdisr[dpmac_id] & devdisr2;
42 void wriop_dpmac_disable(int dpmac_id)
44 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
46 setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
49 void wriop_dpmac_enable(int dpmac_id)
51 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
53 clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
56 phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
60 if (is_device_disabled(dpmac_id + 1))
61 return PHY_INTERFACE_MODE_NONE;
63 if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
64 return PHY_INTERFACE_MODE_SGMII;
66 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
67 return PHY_INTERFACE_MODE_XGMII;
69 if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
70 return PHY_INTERFACE_MODE_25G_AUI;
72 if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
73 return PHY_INTERFACE_MODE_XLAUI;
75 if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
76 return PHY_INTERFACE_MODE_CAUI2;
78 if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
79 return PHY_INTERFACE_MODE_CAUI4;
81 return PHY_INTERFACE_MODE_NONE;
84 #ifdef CONFIG_SYS_FSL_HAS_RGMII
85 void fsl_rgmii_init(void)
87 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
90 #ifdef CONFIG_SYS_FSL_EC1
91 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
92 & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
93 ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
95 if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV))
96 wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
99 #ifdef CONFIG_SYS_FSL_EC2
100 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
101 & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
102 ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
104 if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV))
105 wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);