2 * Micrel KS8851_MLL 16bit Network driver
3 * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include "ks8851_mll.h"
29 #define DRIVERNAME "ks8851_mll"
31 #define MAX_RECV_FRAMES 32
32 #define MAX_BUF_SIZE 2048
33 #define TX_BUF_SIZE 2000
34 #define RX_BUF_SIZE 2000
36 static const struct chip_id chip_ids[] = {
37 {CIDER_ID, "KSZ8851"},
42 * union ks_tx_hdr - tx header data
43 * @txb: The header as bytes
44 * @txw: The header as 16bit, little-endian words
46 * A dual representation of the tx header data to allow
47 * access to individual bytes, and to allow 16bit accesses
48 * with 16bit alignment.
56 * struct ks_net - KS8851 driver private data
57 * @net_device : The network device we're bound to
58 * @txh : temporaly buffer to save status/length.
59 * @frame_head_info : frame header information for multi-pkt rx.
60 * @statelock : Lock on this structure for tx list.
61 * @msg_enable : The message flags controlling driver output (see ethtool).
62 * @frame_cnt : number of frames received.
63 * @bus_width : i/o bus width.
64 * @irq : irq number assigned to this device.
65 * @rc_rxqcr : Cached copy of KS_RXQCR.
66 * @rc_txcr : Cached copy of KS_TXCR.
67 * @rc_ier : Cached copy of KS_IER.
68 * @sharedbus : Multipex(addr and data bus) mode indicator.
69 * @cmd_reg_cache : command register cached.
70 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
71 * @promiscuous : promiscuous mode indicator.
72 * @all_mcast : mutlicast indicator.
73 * @mcast_lst_size : size of multicast list.
74 * @mcast_lst : multicast list.
75 * @mcast_bits : multicast enabed.
76 * @mac_addr : MAC address assigned to this device.
78 * @extra_byte : number of extra byte prepended rx pkt.
79 * @enabled : indicator this device works.
82 /* Receive multiplex framer header info */
83 struct type_frame_head {
84 u16 sts; /* Frame status */
85 u16 len; /* Byte count */
86 } fr_h_i[MAX_RECV_FRAMES];
89 struct net_device *netdev;
91 struct type_frame_head *frame_head_info;
101 u16 cmd_reg_cache_int;
105 u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
106 u8 mcast_bits[HW_MCAST_SIZE];
113 #define BE3 0x8000 /* Byte Enable 3 */
114 #define BE2 0x4000 /* Byte Enable 2 */
115 #define BE1 0x2000 /* Byte Enable 1 */
116 #define BE0 0x1000 /* Byte Enable 0 */
118 static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
120 u8 shift_bit = offset & 0x03;
121 u8 shift_data = (offset & 1) << 3;
123 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
125 return (u8)(readw(dev->iobase) >> shift_data);
128 static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
130 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
132 return readw(dev->iobase);
135 static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val)
137 u8 shift_bit = (offset & 0x03);
138 u16 value_write = (u16)(val << ((offset & 1) << 3));
140 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
141 writew(value_write, dev->iobase);
144 static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
146 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
147 writew(val, dev->iobase);
151 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
153 * @ks: The chip state
154 * @wptr: buffer address to save data
155 * @len: length in byte to read
157 static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
162 *wptr++ = readw(dev->iobase);
166 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
167 * @ks: The chip information
168 * @wptr: buffer address
169 * @len: length in byte to write
171 static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
176 writew(*wptr++, dev->iobase);
179 static void ks_enable_int(struct eth_device *dev)
181 ks_wrreg16(dev, KS_IER, ks->rc_ier);
184 static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
188 ks_rdreg16(dev, KS_GRR);
189 pmecr = ks_rdreg16(dev, KS_PMECR);
190 pmecr &= ~PMECR_PM_MASK;
193 ks_wrreg16(dev, KS_PMECR, pmecr);
197 * ks_read_config - read chip configuration of bus width.
198 * @ks: The chip information
200 static void ks_read_config(struct eth_device *dev)
204 /* Regardless of bus width, 8 bit read should always work. */
205 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
206 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
208 /* addr/data bus are multiplexed */
209 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
212 * There are garbage data when reading data from QMU,
213 * depending on bus-width.
215 if (reg_data & CCR_8BIT) {
216 ks->bus_width = ENUM_BUS_8BIT;
218 } else if (reg_data & CCR_16BIT) {
219 ks->bus_width = ENUM_BUS_16BIT;
222 ks->bus_width = ENUM_BUS_32BIT;
228 * ks_soft_reset - issue one of the soft reset to the device
229 * @ks: The device state.
230 * @op: The bit(s) to set in the GRR
232 * Issue the relevant soft-reset command to the device's GRR register
235 * Note, the delays are in there as a caution to ensure that the reset
236 * has time to take effect and then complete. Since the datasheet does
237 * not currently specify the exact sequence, we have chosen something
238 * that seems to work with our device.
240 static void ks_soft_reset(struct eth_device *dev, unsigned op)
242 /* Disable interrupt first */
243 ks_wrreg16(dev, KS_IER, 0x0000);
244 ks_wrreg16(dev, KS_GRR, op);
245 mdelay(10); /* wait a short time to effect reset */
246 ks_wrreg16(dev, KS_GRR, 0);
247 mdelay(1); /* wait for condition to clear */
250 void ks_enable_qmu(struct eth_device *dev)
254 w = ks_rdreg16(dev, KS_TXCR);
256 /* Enables QMU Transmit (TXCR). */
257 ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
259 /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
260 w = ks_rdreg16(dev, KS_RXQCR);
261 ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
263 /* Enables QMU Receive (RXCR1). */
264 w = ks_rdreg16(dev, KS_RXCR1);
265 ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
268 static void ks_disable_qmu(struct eth_device *dev)
272 w = ks_rdreg16(dev, KS_TXCR);
274 /* Disables QMU Transmit (TXCR). */
276 ks_wrreg16(dev, KS_TXCR, w);
278 /* Disables QMU Receive (RXCR1). */
279 w = ks_rdreg16(dev, KS_RXCR1);
281 ks_wrreg16(dev, KS_RXCR1, w);
284 static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
286 u32 r = ks->extra_byte & 0x1;
287 u32 w = ks->extra_byte - r;
289 /* 1. set sudo DMA mode */
290 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
291 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
294 * 2. read prepend data
296 * read 4 + extra bytes and discard them.
297 * extra bytes for dummy, 2 for status, 2 for len
303 ks_inblk(dev, buf, w + 2 + 2);
305 /* 3. read pkt data */
306 ks_inblk(dev, buf, ALIGN(len, 4));
308 /* 4. reset sudo DMA Mode */
309 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
312 static void ks_rcv(struct eth_device *dev, uchar **pv_data)
314 struct type_frame_head *frame_hdr = ks->frame_head_info;
317 ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
319 /* read all header information */
320 for (i = 0; i < ks->frame_cnt; i++) {
321 /* Checking Received packet status */
322 frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
323 /* Get packet len from hardware */
324 frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR);
328 frame_hdr = ks->frame_head_info;
329 while (ks->frame_cnt--) {
330 if ((frame_hdr->sts & RXFSHR_RXFV) &&
331 (frame_hdr->len < RX_BUF_SIZE) &&
333 /* read data block including CRC 4 bytes */
334 ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len);
336 /* NetRxPackets buffer size is ok (*pv_data pointer) */
337 NetReceive(*pv_data, frame_hdr->len);
340 ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
341 printf(DRIVERNAME ": bad packet\n");
348 * ks_read_selftest - read the selftest memory info.
349 * @ks: The device state
351 * Read and check the TX/RX memory selftest information.
353 static int ks_read_selftest(struct eth_device *dev)
355 u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
359 mbir = ks_rdreg16(dev, KS_MBIR);
361 if ((mbir & both_done) != both_done) {
362 printf(DRIVERNAME ": Memory selftest not finished\n");
366 if (mbir & MBIR_TXMBFA) {
367 printf(DRIVERNAME ": TX memory selftest fails\n");
371 if (mbir & MBIR_RXMBFA) {
372 printf(DRIVERNAME ": RX memory selftest fails\n");
376 debug(DRIVERNAME ": the selftest passes\n");
381 static void ks_setup(struct eth_device *dev)
385 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
386 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
388 /* Setup Receive Frame Data Pointer Auto-Increment */
389 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
391 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
392 ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
394 /* Setup RxQ Command Control (RXQCR) */
395 ks->rc_rxqcr = RXQCR_CMD_CNTL;
396 ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);
399 * set the force mode to half duplex, default is full duplex
400 * because if the auto-negotiation fails, most switch uses
403 w = ks_rdreg16(dev, KS_P1MBCR);
404 w &= ~P1MBCR_FORCE_FDX;
405 ks_wrreg16(dev, KS_P1MBCR, w);
407 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
408 ks_wrreg16(dev, KS_TXCR, w);
410 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
415 ks_wrreg16(dev, KS_RXCR1, w);
418 static void ks_setup_int(struct eth_device *dev)
422 /* Clear the interrupts status of the hardware. */
423 ks_wrreg16(dev, KS_ISR, 0xffff);
425 /* Enables the interrupts of the hardware. */
426 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
429 static int ks8851_mll_detect_chip(struct eth_device *dev)
431 unsigned short val, i;
435 val = ks_rdreg16(dev, KS_CIDER);
438 /* Special case -- no chip present */
439 printf(DRIVERNAME ": is chip mounted ?\n");
441 } else if ((val & 0xfff0) != CIDER_ID) {
442 printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
446 debug("Read back KS8851 id 0x%x\n", val);
448 /* only one entry in the table */
450 for (i = 0; chip_ids[i].id != 0; i++) {
451 if (chip_ids[i].id == val)
454 if (!chip_ids[i].id) {
455 printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
459 dev->priv = (void *)&chip_ids[i];
464 static void ks8851_mll_reset(struct eth_device *dev)
466 /* wake up powermode to normal mode */
467 ks_set_powermode(dev, PMECR_PM_NORMAL);
468 mdelay(1); /* wait for normal mode to take effect */
470 /* Disable interrupt and reset */
471 ks_soft_reset(dev, GRR_GSR);
473 /* turn off the IRQs and ack any outstanding */
474 ks_wrreg16(dev, KS_IER, 0x0000);
475 ks_wrreg16(dev, KS_ISR, 0xffff);
477 /* shutdown RX/TX QMU */
481 static void ks8851_mll_phy_configure(struct eth_device *dev)
488 /* Probing the phy */
489 data = ks_rdreg16(dev, KS_OBCR);
490 ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
492 debug(DRIVERNAME ": phy initialized\n");
495 static void ks8851_mll_enable(struct eth_device *dev)
497 ks_wrreg16(dev, KS_ISR, 0xffff);
502 static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
504 struct chip_id *id = dev->priv;
506 debug(DRIVERNAME ": detected %s controller\n", id->name);
508 if (ks_read_selftest(dev)) {
509 printf(DRIVERNAME ": Selftest failed\n");
513 ks8851_mll_reset(dev);
515 /* Configure the PHY, initialize the link state */
516 ks8851_mll_phy_configure(dev);
518 /* static allocation of private informations */
519 ks->frame_head_info = fr_h_i;
521 /* Turn on Tx + Rx */
522 ks8851_mll_enable(dev);
527 static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
529 /* start header at txb[0] to align txw entries */
531 ks->txh.txw[1] = cpu_to_le16(len);
533 /* 1. set sudo-DMA mode */
534 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
535 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
536 /* 2. write status/lenth info */
537 ks_outblk(dev, ks->txh.txw, 4);
538 /* 3. write pkt data */
539 ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
540 /* 4. reset sudo-DMA mode */
541 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
542 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
543 ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
544 /* 6. wait until TXQCR_METFE is auto-cleared */
545 do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
548 static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
550 u8 *data = (u8 *)packet;
551 u16 tmplen = (u16)length;
555 * Extra space are required:
556 * 4 byte for alignment, 4 for status/length, 4 for CRC
558 retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
559 if (retv >= tmplen + 12) {
560 ks_write_qmu(dev, data, tmplen);
563 printf(DRIVERNAME ": failed to send packet: No buffer\n");
568 static void ks8851_mll_halt(struct eth_device *dev)
570 ks8851_mll_reset(dev);
574 * Maximum receive ring size; that is, the number of packets
575 * we can buffer before overflow happens. Basically, this just
576 * needs to be enough to prevent a packet being discarded while
577 * we are processing the previous one.
579 static int ks8851_mll_recv(struct eth_device *dev)
583 status = ks_rdreg16(dev, KS_ISR);
585 ks_wrreg16(dev, KS_ISR, status);
587 if ((status & IRQ_RXI))
588 ks_rcv(dev, (uchar **)NetRxPackets);
590 if ((status & IRQ_LDI)) {
591 u16 pmecr = ks_rdreg16(dev, KS_PMECR);
592 pmecr &= ~PMECR_WKEVT_MASK;
593 ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
599 static int ks8851_mll_write_hwaddr(struct eth_device *dev)
601 u16 addrl, addrm, addrh;
603 addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
604 addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
605 addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
607 ks_wrreg16(dev, KS_MARH, addrh);
608 ks_wrreg16(dev, KS_MARM, addrm);
609 ks_wrreg16(dev, KS_MARL, addrl);
614 int ks8851_mll_initialize(u8 dev_num, int base_addr)
616 struct eth_device *dev;
618 dev = malloc(sizeof(*dev));
620 printf("Error: Failed to allocate memory\n");
623 memset(dev, 0, sizeof(*dev));
625 dev->iobase = base_addr;
629 /* Try to detect chip. Will fail if not present. */
630 if (ks8851_mll_detect_chip(dev)) {
635 dev->init = ks8851_mll_init;
636 dev->halt = ks8851_mll_halt;
637 dev->send = ks8851_mll_send;
638 dev->recv = ks8851_mll_recv;
639 dev->write_hwaddr = ks8851_mll_write_hwaddr;
640 sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);