3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * based on - Driver for MV64360X ethernet ports
7 * Copyright (C) 2002 rabeeh@galileo.co.il
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
31 #define MAX_KWGBE_DEVS 2 /*controller has two ports */
33 /* PHY_BASE_ADR is board specific and can be configured */
34 #if defined (CONFIG_PHY_BASE_ADR)
35 #define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
37 #define PHY_BASE_ADR 0x08 /* default phy base addr */
41 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
42 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
43 #define MRU_MASK 0xfff1ffff
44 #define PHYADR_MASK 0x0000001f
45 #define PHYREG_MASK 0x0000001f
46 #define QTKNBKT_DEF_VAL 0x3fffffff
47 #define QMTBS_DEF_VAL 0x000003ff
48 #define QTKNRT_DEF_VAL 0x0000fcff
49 #define RXUQ 0 /* Used Rx queue */
50 #define TXUQ 0 /* Used Rx queue */
52 #define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
53 #define KWGBEREG_WR(adr, val) writel(val, &adr)
54 #define KWGBEREG_RD(adr) readl(&adr)
55 #define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
56 #define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
58 /* Default port configuration value */
59 #define PRT_CFG_VAL ( \
60 KWGBE_UCAST_MOD_NRML | \
61 KWGBE_DFLT_RXQ(RXUQ) | \
62 KWGBE_DFLT_RX_ARPQ(RXUQ) | \
63 KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
65 KWGBE_RX_BC_IF_ARP | \
66 KWGBE_CPTR_TCP_FRMS_DIS | \
67 KWGBE_CPTR_UDP_FRMS_DIS | \
68 KWGBE_DFLT_RX_TCPQ(RXUQ) | \
69 KWGBE_DFLT_RX_UDPQ(RXUQ) | \
70 KWGBE_DFLT_RX_BPDUQ(RXUQ))
72 /* Default port extend configuration value */
73 #define PORT_CFG_EXTEND_VALUE \
74 KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
75 KWGBE_PARTITION_DIS | \
76 KWGBE_TX_CRC_GENERATION_EN
78 #define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
80 /* Default sdma control value */
81 #define PORT_SDMA_CFG_VALUE ( \
82 KWGBE_RX_BURST_SIZE_16_64BIT | \
83 KWGBE_BLM_RX_NO_SWAP | \
84 KWGBE_BLM_TX_NO_SWAP | \
85 GT_KWGBE_IPG_INT_RX(RXUQ) | \
86 KWGBE_TX_BURST_SIZE_16_64BIT)
88 /* Default port serial control value */
89 #define PORT_SERIAL_CONTROL_VALUE ( \
90 KWGBE_FORCE_LINK_PASS | \
91 KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
92 KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
93 KWGBE_ADV_NO_FLOW_CTRL | \
94 KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
95 KWGBE_FORCE_BP_MODE_NO_JAM | \
96 (1 << 9) /* Reserved bit has to be 1 */ | \
97 KWGBE_DO_NOT_FORCE_LINK_FAIL | \
98 KWGBE_EN_AUTO_NEG_SPEED_GMII | \
100 KWGBE_MIIPHY_MAC_MODE | \
101 KWGBE_AUTO_NEG_NO_CHANGE | \
102 KWGBE_MAX_RX_PACKET_1552BYTE | \
103 KWGBE_CLR_EXT_LOOPBACK | \
104 KWGBE_SET_FULL_DUPLEX_MODE | \
105 KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
107 /* Tx WRR confoguration macros */
108 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
109 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
110 #define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
111 /* MAC accepet/reject macros */
112 #define ACCEPT_MAC_ADDR 0
113 #define REJECT_MAC_ADDR 1
114 /* Size of a Tx/Rx descriptor used in chain list data structure */
115 #define KW_RXQ_DESC_ALIGNED_SIZE \
116 (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
117 /* Buffer offset from buffer pointer */
118 #define RX_BUF_OFFSET 0x2
120 /* Port serial status reg (PSR) */
121 #define KWGBE_INTERFACE_GMII_MII 0
122 #define KWGBE_INTERFACE_PCM 1
123 #define KWGBE_LINK_IS_DOWN 0
124 #define KWGBE_LINK_IS_UP (1 << 1)
125 #define KWGBE_PORT_AT_HALF_DUPLEX 0
126 #define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
127 #define KWGBE_RX_FLOW_CTRL_DISD 0
128 #define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
129 #define KWGBE_GMII_SPEED_100_10 0
130 #define KWGBE_GMII_SPEED_1000 (1 << 4)
131 #define KWGBE_MII_SPEED_10 0
132 #define KWGBE_MII_SPEED_100 (1 << 5)
133 #define KWGBE_NO_TX 0
134 #define KWGBE_TX_IN_PROGRESS (1 << 7)
135 #define KWGBE_BYPASS_NO_ACTIVE 0
136 #define KWGBE_BYPASS_ACTIVE (1 << 8)
137 #define KWGBE_PORT_NOT_AT_PARTN_STT 0
138 #define KWGBE_PORT_AT_PARTN_STT (1 << 9)
139 #define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
140 #define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
142 /* These macros describes the Port configuration reg (Px_cR) bits */
143 #define KWGBE_UCAST_MOD_NRML 0
144 #define KWGBE_UNICAST_PROMISCUOUS_MODE 1
145 #define KWGBE_DFLT_RXQ(_x) (_x << 1)
146 #define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
147 #define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
148 #define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
149 #define KWGBE_RX_BC_IF_IP 0
150 #define KWGBE_REJECT_BC_IF_IP (1 << 8)
151 #define KWGBE_RX_BC_IF_ARP 0
152 #define KWGBE_REJECT_BC_IF_ARP (1 << 9)
153 #define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
154 #define KWGBE_CPTR_TCP_FRMS_DIS 0
155 #define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
156 #define KWGBE_CPTR_UDP_FRMS_DIS 0
157 #define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
158 #define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
159 #define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
160 #define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
161 #define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
163 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
164 #define KWGBE_CLASSIFY_EN 1
165 #define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
166 #define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
167 #define KWGBE_PARTITION_DIS 0
168 #define KWGBE_PARTITION_EN (1 << 2)
169 #define KWGBE_TX_CRC_GENERATION_EN 0
170 #define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
172 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
174 #define KWGBE_RX_BURST_SIZE_1_64BIT 0
175 #define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
176 #define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
177 #define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
178 #define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
179 #define KWGBE_BLM_RX_NO_SWAP (1 << 4)
180 #define KWGBE_BLM_RX_BYTE_SWAP 0
181 #define KWGBE_BLM_TX_NO_SWAP (1 << 5)
182 #define KWGBE_BLM_TX_BYTE_SWAP 0
183 #define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
184 #define KWGBE_DESCRIPTORS_NO_SWAP 0
185 #define KWGBE_TX_BURST_SIZE_1_64BIT 0
186 #define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
187 #define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
188 #define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
189 #define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
191 /* These macros describes the Port serial control reg (PSCR) bits */
192 #define KWGBE_SERIAL_PORT_DIS 0
193 #define KWGBE_SERIAL_PORT_EN 1
194 #define KWGBE_FORCE_LINK_PASS (1 << 1)
195 #define KWGBE_DO_NOT_FORCE_LINK_PASS 0
196 #define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
197 #define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
198 #define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
199 #define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
200 #define KWGBE_ADV_NO_FLOW_CTRL 0
201 #define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
202 #define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
203 #define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
204 #define KWGBE_FORCE_BP_MODE_NO_JAM 0
205 #define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
206 #define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
207 #define KWGBE_FORCE_LINK_FAIL 0
208 #define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
209 #define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
210 #define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
211 #define KWGBE_DTE_ADV_0 0
212 #define KWGBE_DTE_ADV_1 (1 << 14)
213 #define KWGBE_MIIPHY_MAC_MODE 0
214 #define KWGBE_MIIPHY_PHY_MODE (1 << 15)
215 #define KWGBE_AUTO_NEG_NO_CHANGE 0
216 #define KWGBE_RESTART_AUTO_NEG (1 << 16)
217 #define KWGBE_MAX_RX_PACKET_1518BYTE 0
218 #define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
219 #define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
220 #define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
221 #define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
222 #define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
223 #define KWGBE_SET_EXT_LOOPBACK (1 << 20)
224 #define KWGBE_CLR_EXT_LOOPBACK 0
225 #define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
226 #define KWGBE_SET_HALF_DUPLEX_MODE 0
227 #define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
228 #define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
229 #define KWGBE_SET_GMII_SPEED_TO_10_100 0
230 #define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
231 #define KWGBE_SET_MII_SPEED_TO_10 0
232 #define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
234 /* SMI register fields */
235 #define KWGBE_PHY_SMI_TIMEOUT 10000
236 #define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
237 #define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
238 #define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
239 #define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
240 #define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
241 #define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
242 #define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
243 #define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
244 #define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
245 #define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
246 #define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
247 #define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
249 /* SDMA command status fields macros */
250 /* Tx & Rx descriptors status */
251 #define KWGBE_ERROR_SUMMARY 1
252 /* Tx & Rx descriptors command */
253 #define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
254 /* Tx descriptors status */
255 #define KWGBE_LC_ERROR 0
256 #define KWGBE_UR_ERROR (1 << 1)
257 #define KWGBE_RL_ERROR (1 << 2)
258 #define KWGBE_LLC_SNAP_FORMAT (1 << 9)
259 #define KWGBE_TX_LAST_FRAME (1 << 20)
261 /* Rx descriptors status */
262 #define KWGBE_CRC_ERROR 0
263 #define KWGBE_OVERRUN_ERROR (1 << 1)
264 #define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
265 #define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
266 #define KWGBE_VLAN_TAGGED (1 << 19)
267 #define KWGBE_BPDU_FRAME (1 << 20)
268 #define KWGBE_TCP_FRAME_OVER_IP_V_4 0
269 #define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
270 #define KWGBE_OTHER_FRAME_TYPE (1 << 22)
271 #define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
272 #define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
273 #define KWGBE_FRAME_HEADER_OK (1 << 25)
274 #define KWGBE_RX_LAST_DESC (1 << 26)
275 #define KWGBE_RX_FIRST_DESC (1 << 27)
276 #define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
277 #define KWGBE_RX_EN_INTERRUPT (1 << 29)
278 #define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
280 /* Rx descriptors byte count */
281 #define KWGBE_FRAME_FRAGMENTED (1 << 2)
283 /* Tx descriptors command */
284 #define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
285 #define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
286 #define KWGBE_TCP_FRAME 0
287 #define KWGBE_UDP_FRAME (1 << 16)
288 #define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
289 #define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
290 #define KWGBE_ZERO_PADDING (1 << 19)
291 #define KWGBE_TX_LAST_DESC (1 << 20)
292 #define KWGBE_TX_FIRST_DESC (1 << 21)
293 #define KWGBE_GEN_CRC (1 << 22)
294 #define KWGBE_TX_EN_INTERRUPT (1 << 23)
295 #define KWGBE_AUTO_MODE (1 << 30)
297 /* Address decode parameters */
298 /* Ethernet Base Address Register bits */
299 #define EBAR_TARGET_DRAM 0x00000000
300 #define EBAR_TARGET_DEVICE 0x00000001
301 #define EBAR_TARGET_CBS 0x00000002
302 #define EBAR_TARGET_PCI0 0x00000003
303 #define EBAR_TARGET_PCI1 0x00000004
304 #define EBAR_TARGET_CUNIT 0x00000005
305 #define EBAR_TARGET_AUNIT 0x00000006
306 #define EBAR_TARGET_GUNIT 0x00000007
309 #define EBAR_DRAM_CS0 0x00000E00
310 #define EBAR_DRAM_CS1 0x00000D00
311 #define EBAR_DRAM_CS2 0x00000B00
312 #define EBAR_DRAM_CS3 0x00000700
314 /* DRAM Target interface */
315 #define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
316 #define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
317 #define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
319 /* Device Bus Target interface */
320 #define EBAR_DEVICE_DEVCS0 0x00001E00
321 #define EBAR_DEVICE_DEVCS1 0x00001D00
322 #define EBAR_DEVICE_DEVCS2 0x00001B00
323 #define EBAR_DEVICE_DEVCS3 0x00001700
324 #define EBAR_DEVICE_BOOTCS3 0x00000F00
326 /* PCI Target interface */
327 #define EBAR_PCI_BYTE_SWAP 0x00000000
328 #define EBAR_PCI_NO_SWAP 0x00000100
329 #define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
330 #define EBAR_PCI_WORD_SWAP 0x00000300
331 #define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
332 #define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
333 #define EBAR_PCI_IO_SPACE 0x00000000
334 #define EBAR_PCI_MEMORY_SPACE 0x00000800
335 #define EBAR_PCI_REQ64_FORCE 0x00000000
336 #define EBAR_PCI_REQ64_SIZE 0x00001000
338 /* Window access control */
339 #define EWIN_ACCESS_NOT_ALLOWED 0
340 #define EWIN_ACCESS_READ_ONLY 1
341 #define EWIN_ACCESS_FULL ((1 << 1) | 1)
343 /* structures represents Controller registers */
350 struct kwgbe_rxdesc *rxcdp;
361 struct kwgbe_registers {
366 u8 pad1[0x080 - 0x00c - 4];
369 u8 pad2[0x094 - 0x084 - 4];
372 u8 pad3[0x0b0 - 0x098 - 4];
374 u8 pad3a[0x200 - 0x0b0 - 4];
375 struct kwgbe_barsz barsz[6];
376 u8 pad4[0x280 - 0x22c - 4];
380 u8 pad5[0x400 - 0x294 - 4];
384 u8 pad6[0x410 - 0x408 - 4];
397 u8 pad7[0x460 - 0x454 - 4];
402 u8 pad8[0x474 - 0x46c - 4];
409 u8 pad11[0x494 - 0x488 - 4];
411 u8 pad12[0x4bc - 0x494 - 4];
413 u8 pad13[0x4dc - 0x4bc - 4];
419 u8 pad14[0x60c - 0x4ec - 4];
420 struct kwgbe_rxcdp rxcdp[7];
421 struct kwgbe_rxdesc *rxcdp7;
423 struct kwgbe_txdesc *tcsdp;
424 u8 pad15[0x6c0 - 0x684 - 4];
425 struct kwgbe_txdesc *tcqdp[8];
426 u8 pad16[0x700 - 0x6dc - 4];
427 struct kwgbe_tqx tqx[8];
429 u8 pad17[0x7a8 - 0x780 - 4];
433 u8 pad19[0x7c0 - 0x7b8 - 4];
439 u8 pad21[0x3000 - 0x27d0 - 4];
440 u32 pad20_1[32]; /* mib counter registes */
441 u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
445 u8 pad23[0xe20c0 - 0x7360c - 4];
446 u32 pmbus_top_arbiter;
449 /* structures/enums needed by driver */
467 struct kwgbe_winparam {
468 enum kwgbe_adrwin win; /* Window number */
469 enum kwgbe_target target; /* System targets */
470 u16 attrib; /* BAR attrib. See above macros */
471 u32 base_addr; /* Window base address in u32 form */
472 u32 high_addr; /* Window high address in u32 form */
473 u32 size; /* Size in MBytes. Must be % 64Kbyte. */
474 int enable; /* Enable/disable access to the window. */
475 u16 access_ctrl; /*Access ctrl register. see above macros */
478 struct kwgbe_rxdesc {
479 u32 cmd_sts; /* Descriptor command status */
480 u16 buf_size; /* Buffer size */
481 u16 byte_cnt; /* Descriptor buffer byte count */
482 u8 *buf_ptr; /* Descriptor buffer pointer */
483 struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
486 struct kwgbe_txdesc {
487 u32 cmd_sts; /* Descriptor command status */
488 u16 l4i_chk; /* CPU provided TCP Checksum */
489 u16 byte_cnt; /* Descriptor buffer byte count */
490 u8 *buf_ptr; /* Descriptor buffer ptr */
491 struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
494 /* port device data struct */
495 struct kwgbe_device {
496 struct eth_device dev;
497 struct kwgbe_registers *regs;
498 struct kwgbe_txdesc *p_txdesc;
499 struct kwgbe_rxdesc *p_rxdesc;
500 struct kwgbe_rxdesc *p_rxdesc_curr;
505 #endif /* __EGIGA_H__ */