3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * Ingo Assmus <ingo.assmus@keymile.com>
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
35 #include <asm/errno.h>
36 #include <asm/types.h>
37 #include <asm/byteorder.h>
38 #include <asm/arch/kirkwood.h>
39 #include "kirkwood_egiga.h"
41 #define KIRKWOOD_PHY_ADR_REQUEST 0xee
42 #define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
45 * smi_reg_read - miiphy_read callback function.
47 * Returns 16bit phy register value, or 0xffff on error
49 static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
51 struct eth_device *dev = eth_get_dev_by_name(devname);
52 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
53 struct kwgbe_registers *regs = dkwgbe->regs;
57 /* Phyadr read request */
58 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
59 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
61 *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
64 /* check parameters */
65 if (phy_adr > PHYADR_MASK) {
66 printf("Err..(%s) Invalid PHY address %d\n",
67 __FUNCTION__, phy_adr);
70 if (reg_ofs > PHYREG_MASK) {
71 printf("Err..(%s) Invalid register offset %d\n",
72 __FUNCTION__, reg_ofs);
76 timeout = KWGBE_PHY_SMI_TIMEOUT;
77 /* wait till the SMI is not busy */
79 /* read smi register */
80 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
82 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
85 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
87 /* fill the phy address and regiser offset and read opcode */
88 smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
89 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
90 | KWGBE_PHY_SMI_OPCODE_READ;
92 /* write the smi register */
93 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
95 /*wait till read value is ready */
96 timeout = KWGBE_PHY_SMI_TIMEOUT;
99 /* read smi register */
100 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
101 if (timeout-- == 0) {
102 printf("Err..(%s) SMI read ready timeout\n",
106 } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
108 /* Wait for the data to update in the SMI register */
109 for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
111 *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
113 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
120 * smi_reg_write - imiiphy_write callback function.
122 * Returns 0 if write succeed, -EINVAL on bad parameters
125 static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
127 struct eth_device *dev = eth_get_dev_by_name(devname);
128 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
129 struct kwgbe_registers *regs = dkwgbe->regs;
133 /* Phyadr write request*/
134 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
135 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
136 KWGBEREG_WR(regs->phyadr, data);
140 /* check parameters */
141 if (phy_adr > PHYADR_MASK) {
142 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
145 if (reg_ofs > PHYREG_MASK) {
146 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
150 /* wait till the SMI is not busy */
151 timeout = KWGBE_PHY_SMI_TIMEOUT;
153 /* read smi register */
154 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
155 if (timeout-- == 0) {
156 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
159 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
161 /* fill the phy addr and reg offset and write opcode and data */
162 smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
163 smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
164 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
165 smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
167 /* write the smi register */
168 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
173 /* Stop and checks all queues */
174 static void stop_queue(u32 * qreg)
178 reg_data = readl(qreg);
180 if (reg_data & 0xFF) {
181 /* Issue stop command for active channels only */
182 writel((reg_data << 8), qreg);
184 /* Wait for all queue activity to terminate. */
187 * Check port cause register that all queues
190 reg_data = readl(qreg);
192 while (reg_data & 0xFF);
197 * set_access_control - Config address decode parameters for Ethernet unit
199 * This function configures the address decode parameters for the Gigabit
200 * Ethernet Controller according the given parameters struct.
202 * @regs Register struct pointer.
203 * @param Address decode parameter struct.
205 static void set_access_control(struct kwgbe_registers *regs,
206 struct kwgbe_winparam *param)
210 /* Set access control register */
211 access_prot_reg = KWGBEREG_RD(regs->epap);
212 /* clear window permission */
213 access_prot_reg &= (~(3 << (param->win * 2)));
214 access_prot_reg |= (param->access_ctrl << (param->win * 2));
215 KWGBEREG_WR(regs->epap, access_prot_reg);
217 /* Set window Size reg (SR) */
218 KWGBEREG_WR(regs->barsz[param->win].size,
219 (((param->size / 0x10000) - 1) << 16));
221 /* Set window Base address reg (BA) */
222 KWGBEREG_WR(regs->barsz[param->win].bar,
223 (param->target | param->attrib | param->base_addr));
224 /* High address remap reg (HARR) */
226 KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
228 /* Base address enable reg (BARER) */
229 if (param->enable == 1)
230 KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
232 KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
235 static void set_dram_access(struct kwgbe_registers *regs)
237 struct kwgbe_winparam win_param;
240 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
241 /* Set access parameters for DRAM bank i */
242 win_param.win = i; /* Use Ethernet window i */
243 /* Window target - DDR */
244 win_param.target = KWGBE_TARGET_DRAM;
245 /* Enable full access */
246 win_param.access_ctrl = EWIN_ACCESS_FULL;
247 win_param.high_addr = 0;
249 win_param.base_addr = kw_sdram_bar(i);
250 win_param.size = kw_sdram_bs(i); /* Get bank size */
251 if (win_param.size == 0)
252 win_param.enable = 0;
254 win_param.enable = 1; /* Enable the access */
256 /* Enable DRAM bank */
259 win_param.attrib = EBAR_DRAM_CS0;
262 win_param.attrib = EBAR_DRAM_CS1;
265 win_param.attrib = EBAR_DRAM_CS2;
268 win_param.attrib = EBAR_DRAM_CS3;
271 /* invalide bank, disable access */
272 win_param.enable = 0;
273 win_param.attrib = 0;
276 /* Set the access control for address window(EPAPR) RD/WR */
277 set_access_control(regs, &win_param);
282 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
284 * Go through all the DA filter tables (Unicast, Special Multicast & Other
285 * Multicast) and set each entry to 0.
287 static void port_init_mac_tables(struct kwgbe_registers *regs)
291 /* Clear DA filter unicast table (Ex_dFUT) */
292 for (table_index = 0; table_index < 4; ++table_index)
293 KWGBEREG_WR(regs->dfut[table_index], 0);
295 for (table_index = 0; table_index < 64; ++table_index) {
296 /* Clear DA filter special multicast table (Ex_dFSMT) */
297 KWGBEREG_WR(regs->dfsmt[table_index], 0);
298 /* Clear DA filter other multicast table (Ex_dFOMT) */
299 KWGBEREG_WR(regs->dfomt[table_index], 0);
304 * port_uc_addr - This function Set the port unicast address table
306 * This function locates the proper entry in the Unicast table for the
307 * specified MAC nibble and sets its properties according to function
309 * This function add/removes MAC addresses from the port unicast address
312 * @uc_nibble Unicast MAC Address last nibble.
313 * @option 0 = Add, 1 = remove address.
315 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
317 static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
324 /* Locate the Unicast table entry */
325 uc_nibble = (0xf & uc_nibble);
326 /* Register offset from unicast table base */
327 tbl_offset = (uc_nibble / 4);
328 /* Entry offset within the above register */
329 reg_offset = uc_nibble % 4;
332 case REJECT_MAC_ADDR:
334 * Clear accepts frame bit at specified unicast
337 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
338 unicast_reg &= (0xFF << (8 * reg_offset));
339 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
341 case ACCEPT_MAC_ADDR:
342 /* Set accepts frame bit at unicast DA filter table entry */
343 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
344 unicast_reg &= (0xFF << (8 * reg_offset));
345 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
346 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
355 * port_uc_addr_set - This function Set the port Unicast address.
357 static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
362 mac_l = (p_addr[4] << 8) | (p_addr[5]);
363 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
366 KWGBEREG_WR(regs->macal, mac_l);
367 KWGBEREG_WR(regs->macah, mac_h);
369 /* Accept frames of this address */
370 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
374 * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
376 static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
378 struct kwgbe_rxdesc *p_rx_desc;
381 /* initialize the Rx descriptors ring */
382 p_rx_desc = dkwgbe->p_rxdesc;
383 for (i = 0; i < RINGSZ; i++) {
385 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
386 p_rx_desc->buf_size = PKTSIZE_ALIGN;
387 p_rx_desc->byte_cnt = 0;
388 p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
389 if (i == (RINGSZ - 1))
390 p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
392 p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
393 ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
394 p_rx_desc = p_rx_desc->nxtdesc_p;
397 dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
400 static int kwgbe_init(struct eth_device *dev)
402 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
403 struct kwgbe_registers *regs = dkwgbe->regs;
404 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
405 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
409 kwgbe_init_rx_desc_ring(dkwgbe);
411 /* Clear the ethernet port interrupts */
412 KWGBEREG_WR(regs->ic, 0);
413 KWGBEREG_WR(regs->ice, 0);
414 /* Unmask RX buffer and TX end interrupt */
415 KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
416 /* Unmask phy and link status changes interrupts */
417 KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
419 set_dram_access(regs);
420 port_init_mac_tables(regs);
421 port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
423 /* Assign port configuration and command. */
424 KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
425 KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
426 KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
428 /* Assign port SDMA configuration */
429 KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
430 KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
431 KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
432 /* Turn off the port/RXUQ bandwidth limitation */
433 KWGBEREG_WR(regs->pmtu, 0);
435 /* Set maximum receive buffer to 9700 bytes */
436 KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
437 | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
439 /* Enable port initially */
440 KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
443 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
444 * disable the leaky bucket mechanism .
446 KWGBEREG_WR(regs->pmtu, 0);
448 /* Assignment of Rx CRDB of given RXUQ */
449 KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
450 /* Enable port Rx. */
451 KWGBEREG_WR(regs->rqc, (1 << RXUQ));
453 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
454 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
455 /* Wait up to 5s for the link status */
456 for (i = 0; i < 5; i++) {
459 miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
460 KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
461 /* Return if we get link up */
462 if (miiphy_link(dev->name, phyadr))
467 printf("No link on %s\n", dev->name);
473 static int kwgbe_halt(struct eth_device *dev)
475 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
476 struct kwgbe_registers *regs = dkwgbe->regs;
478 /* Disable all gigE address decoder */
479 KWGBEREG_WR(regs->bare, 0x3f);
481 stop_queue(®s->tqc);
482 stop_queue(®s->rqc);
485 KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
486 /* Set port is not reset */
487 KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
488 #ifdef CONFIG_SYS_MII_MODE
489 /* Set MMI interface up */
490 KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
492 /* Disable & mask ethernet port interrupts */
493 KWGBEREG_WR(regs->ic, 0);
494 KWGBEREG_WR(regs->ice, 0);
495 KWGBEREG_WR(regs->pim, 0);
496 KWGBEREG_WR(regs->peim, 0);
501 static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
504 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
505 struct kwgbe_registers *regs = dkwgbe->regs;
506 struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
507 void *p = (void *)dataptr;
510 /* Copy buffer if it's misaligned */
511 if ((u32) dataptr & 0x07) {
512 if (datasize > PKTSIZE_ALIGN) {
513 printf("Non-aligned data too large (%d)\n",
518 memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
519 p = dkwgbe->p_aligned_txbuf;
522 p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
523 p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
524 p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
525 p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
526 p_txdesc->buf_ptr = (u8 *) p;
527 p_txdesc->byte_cnt = datasize;
529 /* Apply send command using zeroth TXUQ */
530 KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
531 KWGBEREG_WR(regs->tqc, (1 << TXUQ));
534 * wait for packet xmit completion
536 cmd_sts = readl(&p_txdesc->cmd_sts);
537 while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
538 /* return fail if error is detected */
539 if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
540 (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
541 cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
542 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
545 cmd_sts = readl(&p_txdesc->cmd_sts);
550 static int kwgbe_recv(struct eth_device *dev)
552 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
553 struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
557 /* wait untill rx packet available or timeout */
559 if (timeout < KWGBE_PHY_SMI_TIMEOUT)
562 debug("%s time out...\n", __FUNCTION__);
565 } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
567 if (p_rxdesc_curr->byte_cnt != 0) {
568 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
569 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
570 (u32) p_rxdesc_curr->buf_ptr,
571 (u32) p_rxdesc_curr->cmd_sts);
575 * In case received a packet without first/last bits on
576 * OR the error summary bit is on,
577 * the packets needs to be dropeed.
579 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
582 (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
583 != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
585 printf("Err..(%s) Dropping packet spread on"
586 " multiple descriptors\n", __FUNCTION__);
588 } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
590 printf("Err..(%s) Dropping packet with errors\n",
594 /* !!! call higher layer processing */
595 debug("%s: Sending Received packet to"
596 " upper layer (NetReceive)\n", __FUNCTION__);
598 /* let the upper layer handle the packet */
599 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
600 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
603 * free these descriptors and point next in the ring
605 p_rxdesc_curr->cmd_sts =
606 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
607 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
608 p_rxdesc_curr->byte_cnt = 0;
610 writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
615 int kirkwood_egiga_initialize(bd_t * bis)
617 struct kwgbe_device *dkwgbe;
618 struct eth_device *dev;
621 u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
623 for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
624 /*skip if port is configured not to use */
625 if (used_ports[devnum] == 0)
628 if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
631 memset(dkwgbe, 0, sizeof(struct kwgbe_device));
633 if (!(dkwgbe->p_rxdesc =
634 (struct kwgbe_rxdesc *)memalign(PKTALIGN,
635 KW_RXQ_DESC_ALIGNED_SIZE
639 if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
640 * PKTSIZE_ALIGN + 1)))
643 if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
646 if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
647 memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
648 free(dkwgbe->p_aligned_txbuf);
650 free(dkwgbe->p_rxbuf);
652 free(dkwgbe->p_rxdesc);
656 printf("Err.. %s Failed to allocate memory\n",
663 /* must be less than NAMESIZE (16) */
664 sprintf(dev->name, "egiga%d", devnum);
666 /* Extract the MAC address from the environment */
669 dkwgbe->regs = (void *)KW_EGIGA0_BASE;
673 dkwgbe->regs = (void *)KW_EGIGA1_BASE;
676 default: /* this should never happen */
677 printf("Err..(%s) Invalid device number %d\n",
678 __FUNCTION__, devnum);
682 while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
683 /* Generate Random Private MAC addr if not set */
684 dev->enetaddr[0] = 0x02;
685 dev->enetaddr[1] = 0x50;
686 dev->enetaddr[2] = 0x43;
687 dev->enetaddr[3] = get_random_hex();
688 dev->enetaddr[4] = get_random_hex();
689 dev->enetaddr[5] = get_random_hex();
690 eth_setenv_enetaddr(s, dev->enetaddr);
693 dev->init = (void *)kwgbe_init;
694 dev->halt = (void *)kwgbe_halt;
695 dev->send = (void *)kwgbe_send;
696 dev->recv = (void *)kwgbe_recv;
700 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
701 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
702 /* Set phy address of the port */
703 miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
704 KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);