drivers/net/keystone_net.c

   1 /*
   2  * Ethernet driver for TI K2HK EVM.
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <command.h>
  11
  12 #include <net.h>
  13 #include <phy.h>
  14 #include <miiphy.h>
  15 #include <malloc.h>
  16 #include <asm/ti-common/keystone_nav.h>
  17 #include <asm/ti-common/keystone_net.h>
  18 #include <asm/ti-common/keystone_serdes.h>
  19
  20 unsigned int emac_open;
  21 static struct mii_dev *mdio_bus;
  22 static unsigned int sys_has_mdio = 1;
  23
  24 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
  25 #define emac_gigabit_enable(x)  keystone2_eth_gigabit_enable(x)
  26 #else
  27 #define emac_gigabit_enable(x)  /* no gigabit to enable */
  28 #endif
  29
  30 #define RX_BUFF_NUMS    24
  31 #define RX_BUFF_LEN     1520
  32 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
  33
  34 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
  35
  36 struct rx_buff_desc net_rx_buffs = {
  37         .buff_ptr       = rx_buffs,
  38         .num_buffs      = RX_BUFF_NUMS,
  39         .buff_len       = RX_BUFF_LEN,
  40         .rx_flow        = 22,
  41 };
  42
  43 static void keystone2_net_serdes_setup(void);
  44
  45 int keystone2_eth_read_mac_addr(struct eth_device *dev)
  46 {
  47         struct eth_priv_t *eth_priv;
  48         u32 maca = 0;
  49         u32 macb = 0;
  50
  51         eth_priv = (struct eth_priv_t *)dev->priv;
  52
  53         /* Read the e-fuse mac address */
  54         if (eth_priv->slave_port == 1) {
  55                 maca = __raw_readl(MAC_ID_BASE_ADDR);
  56                 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
  57         }
  58
  59         dev->enetaddr[0] = (macb >>  8) & 0xff;
  60         dev->enetaddr[1] = (macb >>  0) & 0xff;
  61         dev->enetaddr[2] = (maca >> 24) & 0xff;
  62         dev->enetaddr[3] = (maca >> 16) & 0xff;
  63         dev->enetaddr[4] = (maca >>  8) & 0xff;
  64         dev->enetaddr[5] = (maca >>  0) & 0xff;
  65
  66         return 0;
  67 }
  68
  69 /* MDIO */
  70
  71 static int keystone2_mdio_reset(struct mii_dev *bus)
  72 {
  73         u_int32_t clkdiv;
  74         struct mdio_regs *adap_mdio = bus->priv;
  75
  76         clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
  77
  78         writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
  79                MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
  80                &adap_mdio->control);
  81
  82         while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
  83                 ;
  84
  85         return 0;
  86 }
  87
  88 /**
  89  * keystone2_mdio_read - read a PHY register via MDIO interface.
  90  * Blocks until operation is complete.
  91  */
  92 static int keystone2_mdio_read(struct mii_dev *bus,
  93                                int addr, int devad, int reg)
  94 {
  95         int tmp;
  96         struct mdio_regs *adap_mdio = bus->priv;
  97
  98         while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
  99                 ;
 100
 101         writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
 102                ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
 103                &adap_mdio->useraccess0);
 104
 105         /* Wait for command to complete */
 106         while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
 107                 ;
 108
 109         if (tmp & MDIO_USERACCESS0_ACK)
 110                 return tmp & 0xffff;
 111
 112         return -1;
 113 }
 114
 115 /**
 116  * keystone2_mdio_write - write to a PHY register via MDIO interface.
 117  * Blocks until operation is complete.
 118  */
 119 static int keystone2_mdio_write(struct mii_dev *bus,
 120                                 int addr, int devad, int reg, u16 val)
 121 {
 122         struct mdio_regs *adap_mdio = bus->priv;
 123
 124         while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
 125                 ;
 126
 127         writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
 128                ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
 129                (val & 0xffff), &adap_mdio->useraccess0);
 130
 131         /* Wait for command to complete */
 132         while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
 133                 ;
 134
 135         return 0;
 136 }
 137
 138 static void  __attribute__((unused))
 139         keystone2_eth_gigabit_enable(struct eth_device *dev)
 140 {
 141         u_int16_t data;
 142         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 143
 144         if (sys_has_mdio) {
 145                 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
 146                                            MDIO_DEVAD_NONE, 0);
 147                 /* speed selection MSB */
 148                 if (!(data & (1 << 6)))
 149                         return;
 150         }
 151
 152         /*
 153          * Check if link detected is giga-bit
 154          * If Gigabit mode detected, enable gigbit in MAC
 155          */
 156         writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
 157                      CPGMACSL_REG_CTL) |
 158                EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
 159                DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
 160 }
 161
 162 int keystone_sgmii_link_status(int port)
 163 {
 164         u32 status = 0;
 165
 166         status = __raw_readl(SGMII_STATUS_REG(port));
 167
 168         return (status & SGMII_REG_STATUS_LOCK) &&
 169                (status & SGMII_REG_STATUS_LINK);
 170 }
 171
 172 int keystone_sgmii_config(int port, int interface)
 173 {
 174         unsigned int i, status, mask;
 175         unsigned int mr_adv_ability, control;
 176
 177         switch (interface) {
 178         case SGMII_LINK_MAC_MAC_AUTONEG:
 179                 mr_adv_ability  = (SGMII_REG_MR_ADV_ENABLE |
 180                                    SGMII_REG_MR_ADV_LINK |
 181                                    SGMII_REG_MR_ADV_FULL_DUPLEX |
 182                                    SGMII_REG_MR_ADV_GIG_MODE);
 183                 control         = (SGMII_REG_CONTROL_MASTER |
 184                                    SGMII_REG_CONTROL_AUTONEG);
 185
 186                 break;
 187         case SGMII_LINK_MAC_PHY:
 188         case SGMII_LINK_MAC_PHY_FORCED:
 189                 mr_adv_ability  = SGMII_REG_MR_ADV_ENABLE;
 190                 control         = SGMII_REG_CONTROL_AUTONEG;
 191
 192                 break;
 193         case SGMII_LINK_MAC_MAC_FORCED:
 194                 mr_adv_ability  = (SGMII_REG_MR_ADV_ENABLE |
 195                                    SGMII_REG_MR_ADV_LINK |
 196                                    SGMII_REG_MR_ADV_FULL_DUPLEX |
 197                                    SGMII_REG_MR_ADV_GIG_MODE);
 198                 control         = SGMII_REG_CONTROL_MASTER;
 199
 200                 break;
 201         case SGMII_LINK_MAC_FIBER:
 202                 mr_adv_ability  = 0x20;
 203                 control         = SGMII_REG_CONTROL_AUTONEG;
 204
 205                 break;
 206         default:
 207                 mr_adv_ability  = SGMII_REG_MR_ADV_ENABLE;
 208                 control         = SGMII_REG_CONTROL_AUTONEG;
 209         }
 210
 211         __raw_writel(0, SGMII_CTL_REG(port));
 212
 213         /*
 214          * Wait for the SerDes pll to lock,
 215          * but don't trap if lock is never read
 216          */
 217         for (i = 0; i < 1000; i++)  {
 218                 udelay(2000);
 219                 status = __raw_readl(SGMII_STATUS_REG(port));
 220                 if ((status & SGMII_REG_STATUS_LOCK) != 0)
 221                         break;
 222         }
 223
 224         __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
 225         __raw_writel(control, SGMII_CTL_REG(port));
 226
 227
 228         mask = SGMII_REG_STATUS_LINK;
 229
 230         if (control & SGMII_REG_CONTROL_AUTONEG)
 231                 mask |= SGMII_REG_STATUS_AUTONEG;
 232
 233         for (i = 0; i < 1000; i++) {
 234                 status = __raw_readl(SGMII_STATUS_REG(port));
 235                 if ((status & mask) == mask)
 236                         break;
 237         }
 238
 239         return 0;
 240 }
 241
 242 int mac_sl_reset(u32 port)
 243 {
 244         u32 i, v;
 245
 246         if (port >= DEVICE_N_GMACSL_PORTS)
 247                 return GMACSL_RET_INVALID_PORT;
 248
 249         /* Set the soft reset bit */
 250         writel(CPGMAC_REG_RESET_VAL_RESET,
 251                DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 252
 253         /* Wait for the bit to clear */
 254         for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
 255                 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 256                 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
 257                     CPGMAC_REG_RESET_VAL_RESET)
 258                         return GMACSL_RET_OK;
 259         }
 260
 261         /* Timeout on the reset */
 262         return GMACSL_RET_WARN_RESET_INCOMPLETE;
 263 }
 264
 265 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
 266 {
 267         u32 v, i;
 268         int ret = GMACSL_RET_OK;
 269
 270         if (port >= DEVICE_N_GMACSL_PORTS)
 271                 return GMACSL_RET_INVALID_PORT;
 272
 273         if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
 274                 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
 275                 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
 276         }
 277
 278         /* Must wait if the device is undergoing reset */
 279         for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
 280                 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 281                 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
 282                     CPGMAC_REG_RESET_VAL_RESET)
 283                         break;
 284         }
 285
 286         if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
 287                 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
 288
 289         writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
 290         writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
 291
 292 #ifdef CONFIG_K2E_EVM
 293         /* Map RX packet flow priority to 0 */
 294         writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
 295 #endif
 296
 297         return ret;
 298 }
 299
 300 int ethss_config(u32 ctl, u32 max_pkt_size)
 301 {
 302         u32 i;
 303
 304         /* Max length register */
 305         writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
 306
 307         /* Control register */
 308         writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
 309
 310         /* All statistics enabled by default */
 311         writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
 312                DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
 313
 314         /* Reset and enable the ALE */
 315         writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
 316                CPSW_REG_VAL_ALE_CTL_BYPASS,
 317                DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
 318
 319         /* All ports put into forward mode */
 320         for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
 321                 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
 322                        DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
 323
 324         return 0;
 325 }
 326
 327 int ethss_start(void)
 328 {
 329         int i;
 330         struct mac_sl_cfg cfg;
 331
 332         cfg.max_rx_len  = MAX_SIZE_STREAM_BUFFER;
 333         cfg.ctl         = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
 334
 335         for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
 336                 mac_sl_reset(i);
 337                 mac_sl_config(i, &cfg);
 338         }
 339
 340         return 0;
 341 }
 342
 343 int ethss_stop(void)
 344 {
 345         int i;
 346
 347         for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
 348                 mac_sl_reset(i);
 349
 350         return 0;
 351 }
 352
 353 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
 354 {
 355         if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
 356                 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
 357
 358         return ksnav_send(&netcp_pktdma, buffer,
 359                           num_bytes, (slave_port_num) << 16);
 360 }
 361
 362 /* Eth device open */
 363 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 364 {
 365         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 366         struct phy_device *phy_dev = eth_priv->phy_dev;
 367
 368         debug("+ emac_open\n");
 369
 370         net_rx_buffs.rx_flow    = eth_priv->rx_flow;
 371
 372         sys_has_mdio =
 373                 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
 374
 375         keystone2_net_serdes_setup();
 376
 377         keystone_sgmii_config(eth_priv->slave_port - 1,
 378                               eth_priv->sgmii_link_type);
 379
 380         udelay(10000);
 381
 382         /* On chip switch configuration */
 383         ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
 384
 385         /* TODO: add error handling code */
 386         if (qm_init()) {
 387                 printf("ERROR: qm_init()\n");
 388                 return -1;
 389         }
 390         if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
 391                 qm_close();
 392                 printf("ERROR: netcp_init()\n");
 393                 return -1;
 394         }
 395
 396         /*
 397          * Streaming switch configuration. If not present this
 398          * statement is defined to void in target.h.
 399          * If present this is usually defined to a series of register writes
 400          */
 401         hw_config_streaming_switch();
 402
 403         if (sys_has_mdio) {
 404                 keystone2_mdio_reset(mdio_bus);
 405
 406                 phy_startup(phy_dev);
 407                 if (phy_dev->link == 0) {
 408                         ksnav_close(&netcp_pktdma);
 409                         qm_close();
 410                         return -1;
 411                 }
 412         }
 413
 414         emac_gigabit_enable(dev);
 415
 416         ethss_start();
 417
 418         debug("- emac_open\n");
 419
 420         emac_open = 1;
 421
 422         return 0;
 423 }
 424
 425 /* Eth device close */
 426 void keystone2_eth_close(struct eth_device *dev)
 427 {
 428         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 429         struct phy_device *phy_dev = eth_priv->phy_dev;
 430
 431         debug("+ emac_close\n");
 432
 433         if (!emac_open)
 434                 return;
 435
 436         ethss_stop();
 437
 438         ksnav_close(&netcp_pktdma);
 439         qm_close();
 440         phy_shutdown(phy_dev);
 441
 442         emac_open = 0;
 443
 444         debug("- emac_close\n");
 445 }
 446
 447 /*
 448  * This function sends a single packet on the network and returns
 449  * positive number (number of bytes transmitted) or negative for error
 450  */
 451 static int keystone2_eth_send_packet(struct eth_device *dev,
 452                                         void *packet, int length)
 453 {
 454         int ret_status = -1;
 455         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 456         struct phy_device *phy_dev = eth_priv->phy_dev;
 457
 458         genphy_update_link(phy_dev);
 459         if (phy_dev->link == 0)
 460                 return -1;
 461
 462         if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
 463                 return ret_status;
 464
 465         return length;
 466 }
 467
 468 /*
 469  * This function handles receipt of a packet from the network
 470  */
 471 static int keystone2_eth_rcv_packet(struct eth_device *dev)
 472 {
 473         void *hd;
 474         int  pkt_size;
 475         u32  *pkt;
 476
 477         hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
 478         if (hd == NULL)
 479                 return 0;
 480
 481         NetReceive((uchar *)pkt, pkt_size);
 482
 483         ksnav_release_rxhd(&netcp_pktdma, hd);
 484
 485         return pkt_size;
 486 }
 487
 488 /*
 489  * This function initializes the EMAC hardware.
 490  */
 491 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
 492 {
 493         int res;
 494         struct eth_device *dev;
 495         struct phy_device *phy_dev;
 496
 497         dev = malloc(sizeof(struct eth_device));
 498         if (dev == NULL)
 499                 return -1;
 500
 501         memset(dev, 0, sizeof(struct eth_device));
 502
 503         strcpy(dev->name, eth_priv->int_name);
 504         dev->priv = eth_priv;
 505
 506         keystone2_eth_read_mac_addr(dev);
 507
 508         dev->iobase             = 0;
 509         dev->init               = keystone2_eth_open;
 510         dev->halt               = keystone2_eth_close;
 511         dev->send               = keystone2_eth_send_packet;
 512         dev->recv               = keystone2_eth_rcv_packet;
 513
 514         eth_register(dev);
 515
 516         /* Register MDIO bus if it's not registered yet */
 517         if (!mdio_bus) {
 518                 mdio_bus        = mdio_alloc();
 519                 mdio_bus->read  = keystone2_mdio_read;
 520                 mdio_bus->write = keystone2_mdio_write;
 521                 mdio_bus->reset = keystone2_mdio_reset;
 522                 mdio_bus->priv  = (void *)EMAC_MDIO_BASE_ADDR;
 523                 sprintf(mdio_bus->name, "ethernet-mdio");
 524
 525                 res = mdio_register(mdio_bus);
 526                 if (res)
 527                         return res;
 528         }
 529
 530         /* Create phy device and bind it with driver */
 531 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 532         phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
 533                               dev, PHY_INTERFACE_MODE_SGMII);
 534         phy_config(phy_dev);
 535 #else
 536         phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
 537                                    PHY_INTERFACE_MODE_SGMII);
 538         phy_dev->dev = dev;
 539 #endif
 540         eth_priv->phy_dev = phy_dev;
 541
 542         return 0;
 543 }
 544
 545 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
 546         .clk = SERDES_CLOCK_156P25M,
 547         .rate = SERDES_RATE_5G,
 548         .rate_mode = SERDES_QUARTER_RATE,
 549         .intf = SERDES_PHY_SGMII,
 550         .loopback = 0,
 551 };
 552
 553 static void keystone2_net_serdes_setup(void)
 554 {
 555         ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
 556                         &ks2_serdes_sgmii_156p25mhz,
 557                         CONFIG_KSNET_SERDES_LANES_PER_SGMII);
 558
 559 #ifdef CONFIG_SOC_K2E
 560         ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
 561                         &ks2_serdes_sgmii_156p25mhz,
 562                         CONFIG_KSNET_SERDES_LANES_PER_SGMII);
 563 #endif
 564
 565         /* wait till setup */
 566         udelay(5000);
 567 }