drivers/net/keystone_net.c

   1 /*
   2  * Ethernet driver for TI K2HK EVM.
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <command.h>
  11
  12 #include <net.h>
  13 #include <miiphy.h>
  14 #include <malloc.h>
  15 #include <asm/ti-common/keystone_nav.h>
  16 #include <asm/ti-common/keystone_net.h>
  17 #include <asm/ti-common/keystone_serdes.h>
  18
  19 unsigned int emac_open;
  20 static unsigned int sys_has_mdio = 1;
  21
  22 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
  23 #define emac_gigabit_enable(x)  keystone2_eth_gigabit_enable(x)
  24 #else
  25 #define emac_gigabit_enable(x)  /* no gigabit to enable */
  26 #endif
  27
  28 #define RX_BUFF_NUMS    24
  29 #define RX_BUFF_LEN     1520
  30 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
  31
  32 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
  33
  34 struct rx_buff_desc net_rx_buffs = {
  35         .buff_ptr       = rx_buffs,
  36         .num_buffs      = RX_BUFF_NUMS,
  37         .buff_len       = RX_BUFF_LEN,
  38         .rx_flow        = 22,
  39 };
  40
  41 static void keystone2_net_serdes_setup(void);
  42
  43 static int gen_get_link_speed(int phy_addr);
  44
  45 /* EMAC Addresses */
  46 static volatile struct mdio_regs        *adap_mdio =
  47         (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
  48
  49 int keystone2_eth_read_mac_addr(struct eth_device *dev)
  50 {
  51         struct eth_priv_t *eth_priv;
  52         u32 maca = 0;
  53         u32 macb = 0;
  54
  55         eth_priv = (struct eth_priv_t *)dev->priv;
  56
  57         /* Read the e-fuse mac address */
  58         if (eth_priv->slave_port == 1) {
  59                 maca = __raw_readl(MAC_ID_BASE_ADDR);
  60                 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
  61         }
  62
  63         dev->enetaddr[0] = (macb >>  8) & 0xff;
  64         dev->enetaddr[1] = (macb >>  0) & 0xff;
  65         dev->enetaddr[2] = (maca >> 24) & 0xff;
  66         dev->enetaddr[3] = (maca >> 16) & 0xff;
  67         dev->enetaddr[4] = (maca >>  8) & 0xff;
  68         dev->enetaddr[5] = (maca >>  0) & 0xff;
  69
  70         return 0;
  71 }
  72
  73 static void keystone2_mdio_reset(void)
  74 {
  75         u_int32_t       clkdiv;
  76
  77         clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
  78
  79         writel((clkdiv & 0xffff) |
  80                MDIO_CONTROL_ENABLE |
  81                MDIO_CONTROL_FAULT |
  82                MDIO_CONTROL_FAULT_ENABLE,
  83                &adap_mdio->control);
  84
  85         while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
  86                 ;
  87 }
  88
  89 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
  90 int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
  91 {
  92         int     tmp;
  93
  94         while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
  95                 ;
  96
  97         writel(MDIO_USERACCESS0_GO |
  98                MDIO_USERACCESS0_WRITE_READ |
  99                ((reg_num & 0x1f) << 21) |
 100                ((phy_addr & 0x1f) << 16),
 101                &adap_mdio->useraccess0);
 102
 103         /* Wait for command to complete */
 104         while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
 105                 ;
 106
 107         if (tmp & MDIO_USERACCESS0_ACK) {
 108                 *data = tmp & 0xffff;
 109                 return 0;
 110         }
 111
 112         *data = -1;
 113         return -1;
 114 }
 115
 116 /*
 117  * Write to a PHY register via MDIO inteface.
 118  * Blocks until operation is complete.
 119  */
 120 int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
 121 {
 122         while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
 123                 ;
 124
 125         writel(MDIO_USERACCESS0_GO |
 126                MDIO_USERACCESS0_WRITE_WRITE |
 127                ((reg_num & 0x1f) << 21) |
 128                ((phy_addr & 0x1f) << 16) |
 129                (data & 0xffff),
 130                &adap_mdio->useraccess0);
 131
 132         /* Wait for command to complete */
 133         while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
 134                 ;
 135
 136         return 0;
 137 }
 138
 139 /* PHY functions for a generic PHY */
 140 static int gen_get_link_speed(int phy_addr)
 141 {
 142         u_int16_t       tmp;
 143
 144         if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) &&
 145             (tmp & 0x04)) {
 146                 return 0;
 147         }
 148
 149         return -1;
 150 }
 151
 152 static void  __attribute__((unused))
 153         keystone2_eth_gigabit_enable(struct eth_device *dev)
 154 {
 155         u_int16_t data;
 156         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 157
 158         if (sys_has_mdio) {
 159                 if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) ||
 160                     !(data & (1 << 6))) /* speed selection MSB */
 161                         return;
 162         }
 163
 164         /*
 165          * Check if link detected is giga-bit
 166          * If Gigabit mode detected, enable gigbit in MAC
 167          */
 168         writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
 169                      CPGMACSL_REG_CTL) |
 170                EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
 171                DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
 172 }
 173
 174 int keystone_sgmii_link_status(int port)
 175 {
 176         u32 status = 0;
 177
 178         status = __raw_readl(SGMII_STATUS_REG(port));
 179
 180         return status & SGMII_REG_STATUS_LINK;
 181 }
 182
 183
 184 int keystone_get_link_status(struct eth_device *dev)
 185 {
 186         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 187         int sgmii_link;
 188         int link_state = 0;
 189 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
 190         int j;
 191
 192         for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
 193              j++) {
 194 #endif
 195                 sgmii_link =
 196                         keystone_sgmii_link_status(eth_priv->slave_port - 1);
 197
 198                 if (sgmii_link) {
 199                         link_state = 1;
 200
 201                         if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
 202                                 if (gen_get_link_speed(eth_priv->phy_addr))
 203                                         link_state = 0;
 204                 }
 205 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
 206         }
 207 #endif
 208         return link_state;
 209 }
 210
 211 int keystone_sgmii_config(int port, int interface)
 212 {
 213         unsigned int i, status, mask;
 214         unsigned int mr_adv_ability, control;
 215
 216         switch (interface) {
 217         case SGMII_LINK_MAC_MAC_AUTONEG:
 218                 mr_adv_ability  = (SGMII_REG_MR_ADV_ENABLE |
 219                                    SGMII_REG_MR_ADV_LINK |
 220                                    SGMII_REG_MR_ADV_FULL_DUPLEX |
 221                                    SGMII_REG_MR_ADV_GIG_MODE);
 222                 control         = (SGMII_REG_CONTROL_MASTER |
 223                                    SGMII_REG_CONTROL_AUTONEG);
 224
 225                 break;
 226         case SGMII_LINK_MAC_PHY:
 227         case SGMII_LINK_MAC_PHY_FORCED:
 228                 mr_adv_ability  = SGMII_REG_MR_ADV_ENABLE;
 229                 control         = SGMII_REG_CONTROL_AUTONEG;
 230
 231                 break;
 232         case SGMII_LINK_MAC_MAC_FORCED:
 233                 mr_adv_ability  = (SGMII_REG_MR_ADV_ENABLE |
 234                                    SGMII_REG_MR_ADV_LINK |
 235                                    SGMII_REG_MR_ADV_FULL_DUPLEX |
 236                                    SGMII_REG_MR_ADV_GIG_MODE);
 237                 control         = SGMII_REG_CONTROL_MASTER;
 238
 239                 break;
 240         case SGMII_LINK_MAC_FIBER:
 241                 mr_adv_ability  = 0x20;
 242                 control         = SGMII_REG_CONTROL_AUTONEG;
 243
 244                 break;
 245         default:
 246                 mr_adv_ability  = SGMII_REG_MR_ADV_ENABLE;
 247                 control         = SGMII_REG_CONTROL_AUTONEG;
 248         }
 249
 250         __raw_writel(0, SGMII_CTL_REG(port));
 251
 252         /*
 253          * Wait for the SerDes pll to lock,
 254          * but don't trap if lock is never read
 255          */
 256         for (i = 0; i < 1000; i++)  {
 257                 udelay(2000);
 258                 status = __raw_readl(SGMII_STATUS_REG(port));
 259                 if ((status & SGMII_REG_STATUS_LOCK) != 0)
 260                         break;
 261         }
 262
 263         __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
 264         __raw_writel(control, SGMII_CTL_REG(port));
 265
 266
 267         mask = SGMII_REG_STATUS_LINK;
 268
 269         if (control & SGMII_REG_CONTROL_AUTONEG)
 270                 mask |= SGMII_REG_STATUS_AUTONEG;
 271
 272         for (i = 0; i < 1000; i++) {
 273                 status = __raw_readl(SGMII_STATUS_REG(port));
 274                 if ((status & mask) == mask)
 275                         break;
 276         }
 277
 278         return 0;
 279 }
 280
 281 int mac_sl_reset(u32 port)
 282 {
 283         u32 i, v;
 284
 285         if (port >= DEVICE_N_GMACSL_PORTS)
 286                 return GMACSL_RET_INVALID_PORT;
 287
 288         /* Set the soft reset bit */
 289         writel(CPGMAC_REG_RESET_VAL_RESET,
 290                DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 291
 292         /* Wait for the bit to clear */
 293         for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
 294                 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 295                 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
 296                     CPGMAC_REG_RESET_VAL_RESET)
 297                         return GMACSL_RET_OK;
 298         }
 299
 300         /* Timeout on the reset */
 301         return GMACSL_RET_WARN_RESET_INCOMPLETE;
 302 }
 303
 304 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
 305 {
 306         u32 v, i;
 307         int ret = GMACSL_RET_OK;
 308
 309         if (port >= DEVICE_N_GMACSL_PORTS)
 310                 return GMACSL_RET_INVALID_PORT;
 311
 312         if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
 313                 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
 314                 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
 315         }
 316
 317         /* Must wait if the device is undergoing reset */
 318         for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
 319                 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
 320                 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
 321                     CPGMAC_REG_RESET_VAL_RESET)
 322                         break;
 323         }
 324
 325         if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
 326                 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
 327
 328         writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
 329         writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
 330
 331         return ret;
 332 }
 333
 334 int ethss_config(u32 ctl, u32 max_pkt_size)
 335 {
 336         u32 i;
 337
 338         /* Max length register */
 339         writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
 340
 341         /* Control register */
 342         writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
 343
 344         /* All statistics enabled by default */
 345         writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
 346                DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
 347
 348         /* Reset and enable the ALE */
 349         writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
 350                CPSW_REG_VAL_ALE_CTL_BYPASS,
 351                DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
 352
 353         /* All ports put into forward mode */
 354         for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
 355                 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
 356                        DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
 357
 358         return 0;
 359 }
 360
 361 int ethss_start(void)
 362 {
 363         int i;
 364         struct mac_sl_cfg cfg;
 365
 366         cfg.max_rx_len  = MAX_SIZE_STREAM_BUFFER;
 367         cfg.ctl         = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
 368
 369         for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
 370                 mac_sl_reset(i);
 371                 mac_sl_config(i, &cfg);
 372         }
 373
 374         return 0;
 375 }
 376
 377 int ethss_stop(void)
 378 {
 379         int i;
 380
 381         for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
 382                 mac_sl_reset(i);
 383
 384         return 0;
 385 }
 386
 387 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
 388 {
 389         if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
 390                 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
 391
 392         return ksnav_send(&netcp_pktdma, buffer,
 393                           num_bytes, (slave_port_num) << 16);
 394 }
 395
 396 /* Eth device open */
 397 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 398 {
 399         int link;
 400         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 401
 402         debug("+ emac_open\n");
 403
 404         net_rx_buffs.rx_flow    = eth_priv->rx_flow;
 405
 406         sys_has_mdio =
 407                 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
 408
 409         keystone2_net_serdes_setup();
 410
 411         keystone_sgmii_config(eth_priv->slave_port - 1,
 412                               eth_priv->sgmii_link_type);
 413
 414         udelay(10000);
 415
 416         /* On chip switch configuration */
 417         ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
 418
 419         /* TODO: add error handling code */
 420         if (qm_init()) {
 421                 printf("ERROR: qm_init()\n");
 422                 return -1;
 423         }
 424         if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
 425                 qm_close();
 426                 printf("ERROR: netcp_init()\n");
 427                 return -1;
 428         }
 429
 430         /*
 431          * Streaming switch configuration. If not present this
 432          * statement is defined to void in target.h.
 433          * If present this is usually defined to a series of register writes
 434          */
 435         hw_config_streaming_switch();
 436
 437         if (sys_has_mdio) {
 438                 keystone2_mdio_reset();
 439
 440                 link = keystone_get_link_status(dev);
 441                 if (link == 0) {
 442                         ksnav_close(&netcp_pktdma);
 443                         qm_close();
 444                         return -1;
 445                 }
 446         }
 447
 448         emac_gigabit_enable(dev);
 449
 450         ethss_start();
 451
 452         debug("- emac_open\n");
 453
 454         emac_open = 1;
 455
 456         return 0;
 457 }
 458
 459 /* Eth device close */
 460 void keystone2_eth_close(struct eth_device *dev)
 461 {
 462         debug("+ emac_close\n");
 463
 464         if (!emac_open)
 465                 return;
 466
 467         ethss_stop();
 468
 469         ksnav_close(&netcp_pktdma);
 470         qm_close();
 471
 472         emac_open = 0;
 473
 474         debug("- emac_close\n");
 475 }
 476
 477 /*
 478  * This function sends a single packet on the network and returns
 479  * positive number (number of bytes transmitted) or negative for error
 480  */
 481 static int keystone2_eth_send_packet(struct eth_device *dev,
 482                                         void *packet, int length)
 483 {
 484         int ret_status = -1;
 485         struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
 486
 487         if (keystone_get_link_status(dev) == 0)
 488                 return -1;
 489
 490         if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
 491                 return ret_status;
 492
 493         return length;
 494 }
 495
 496 /*
 497  * This function handles receipt of a packet from the network
 498  */
 499 static int keystone2_eth_rcv_packet(struct eth_device *dev)
 500 {
 501         void *hd;
 502         int  pkt_size;
 503         u32  *pkt;
 504
 505         hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
 506         if (hd == NULL)
 507                 return 0;
 508
 509         NetReceive((uchar *)pkt, pkt_size);
 510
 511         ksnav_release_rxhd(&netcp_pktdma, hd);
 512
 513         return pkt_size;
 514 }
 515
 516 /*
 517  * This function initializes the EMAC hardware.
 518  */
 519 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
 520 {
 521         struct eth_device *dev;
 522
 523         dev = malloc(sizeof(struct eth_device));
 524         if (dev == NULL)
 525                 return -1;
 526
 527         memset(dev, 0, sizeof(struct eth_device));
 528
 529         strcpy(dev->name, eth_priv->int_name);
 530         dev->priv = eth_priv;
 531
 532         keystone2_eth_read_mac_addr(dev);
 533
 534         dev->iobase             = 0;
 535         dev->init               = keystone2_eth_open;
 536         dev->halt               = keystone2_eth_close;
 537         dev->send               = keystone2_eth_send_packet;
 538         dev->recv               = keystone2_eth_rcv_packet;
 539
 540         eth_register(dev);
 541
 542         return 0;
 543 }
 544
 545 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
 546         .clk = SERDES_CLOCK_156P25M,
 547         .rate = SERDES_RATE_5G,
 548         .rate_mode = SERDES_QUARTER_RATE,
 549         .intf = SERDES_PHY_SGMII,
 550         .loopback = 0,
 551 };
 552
 553 static void keystone2_net_serdes_setup(void)
 554 {
 555         ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
 556                         &ks2_serdes_sgmii_156p25mhz,
 557                         CONFIG_KSNET_SERDES_LANES_PER_SGMII);
 558
 559         /* wait till setup */
 560         udelay(5000);
 561 }