drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 135                  "per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172         if (adapter->vfinfo)
 173                 kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 printk(KERN_ERR "%-15s ", rname);
 293                 for (j = 0; j < 8; j++)
 294                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 295                 printk(KERN_CONT "\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 printk(KERN_INFO "Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 328                 netdev->name,
 329                 netdev->state,
 330                 netdev->trans_start,
 331                 netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         printk(KERN_INFO " Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 348                 "leng ntw timestamp\n");
 349         for (n = 0; n < adapter->num_tx_queues; n++) {
 350                 tx_ring = adapter->tx_ring[n];
 351                 tx_buffer_info =
 352                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 353                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 354                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 355                            (u64)tx_buffer_info->dma,
 356                            tx_buffer_info->length,
 357                            tx_buffer_info->next_to_watch,
 358                            (u64)tx_buffer_info->time_stamp);
 359         }
 360
 361         /* Print TX Rings */
 362         if (!netif_msg_tx_done(adapter))
 363                 goto rx_ring_summary;
 364
 365         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 366
 367         /* Transmit Descriptor Formats
 368          *
 369          * Advanced Transmit Descriptor
 370          *   +--------------------------------------------------------------+
 371          * 0 |         Buffer Address [63:0]                                |
 372          *   +--------------------------------------------------------------+
 373          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 374          *   +--------------------------------------------------------------+
 375          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 376          */
 377
 378         for (n = 0; n < adapter->num_tx_queues; n++) {
 379                 tx_ring = adapter->tx_ring[n];
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 382                 printk(KERN_INFO "------------------------------------\n");
 383                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 384                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 385                         "leng  ntw timestamp        bi->skb\n");
 386
 387                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 388                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 389                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 390                         u0 = (struct my_u0 *)tx_desc;
 391                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 392                                 " %04X  %3X %016llX %p", i,
 393                                 le64_to_cpu(u0->a),
 394                                 le64_to_cpu(u0->b),
 395                                 (u64)tx_buffer_info->dma,
 396                                 tx_buffer_info->length,
 397                                 tx_buffer_info->next_to_watch,
 398                                 (u64)tx_buffer_info->time_stamp,
 399                                 tx_buffer_info->skb);
 400                         if (i == tx_ring->next_to_use &&
 401                                 i == tx_ring->next_to_clean)
 402                                 printk(KERN_CONT " NTC/U\n");
 403                         else if (i == tx_ring->next_to_use)
 404                                 printk(KERN_CONT " NTU\n");
 405                         else if (i == tx_ring->next_to_clean)
 406                                 printk(KERN_CONT " NTC\n");
 407                         else
 408                                 printk(KERN_CONT "\n");
 409
 410                         if (netif_msg_pktdata(adapter) &&
 411                                 tx_buffer_info->dma != 0)
 412                                 print_hex_dump(KERN_INFO, "",
 413                                         DUMP_PREFIX_ADDRESS, 16, 1,
 414                                         phys_to_virt(tx_buffer_info->dma),
 415                                         tx_buffer_info->length, true);
 416                 }
 417         }
 418
 419         /* Print RX Rings Summary */
 420 rx_ring_summary:
 421         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 422         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 423         for (n = 0; n < adapter->num_rx_queues; n++) {
 424                 rx_ring = adapter->rx_ring[n];
 425                 printk(KERN_INFO "%5d %5X %5X\n", n,
 426                            rx_ring->next_to_use, rx_ring->next_to_clean);
 427         }
 428
 429         /* Print RX Rings */
 430         if (!netif_msg_rx_status(adapter))
 431                 goto exit;
 432
 433         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 434
 435         /* Advanced Receive Descriptor (Read) Format
 436          *    63                                           1        0
 437          *    +-----------------------------------------------------+
 438          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 439          *    +----------------------------------------------+------+
 440          *  8 |       Header Buffer Address [63:1]           |  DD  |
 441          *    +-----------------------------------------------------+
 442          *
 443          *
 444          * Advanced Receive Descriptor (Write-Back) Format
 445          *
 446          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 447          *   +------------------------------------------------------+
 448          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 449          *   | Checksum   Ident  |   |           |    | Type | Type |
 450          *   +------------------------------------------------------+
 451          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 452          *   +------------------------------------------------------+
 453          *   63       48 47    32 31            20 19               0
 454          */
 455         for (n = 0; n < adapter->num_rx_queues; n++) {
 456                 rx_ring = adapter->rx_ring[n];
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 459                 printk(KERN_INFO "------------------------------------\n");
 460                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 461                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 462                         "<-- Adv Rx Read format\n");
 463                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 464                         "[vl er S cks ln] ---------------- [bi->skb] "
 465                         "<-- Adv Rx Write-Back format\n");
 466
 467                 for (i = 0; i < rx_ring->count; i++) {
 468                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 469                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 470                         u0 = (struct my_u0 *)rx_desc;
 471                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 472                         if (staterr & IXGBE_RXD_STAT_DD) {
 473                                 /* Descriptor Done */
 474                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 475                                         "%016llX ---------------- %p", i,
 476                                         le64_to_cpu(u0->a),
 477                                         le64_to_cpu(u0->b),
 478                                         rx_buffer_info->skb);
 479                         } else {
 480                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 481                                         "%016llX %016llX %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         (u64)rx_buffer_info->dma,
 485                                         rx_buffer_info->skb);
 486
 487                                 if (netif_msg_pktdata(adapter)) {
 488                                         print_hex_dump(KERN_INFO, "",
 489                                            DUMP_PREFIX_ADDRESS, 16, 1,
 490                                            phys_to_virt(rx_buffer_info->dma),
 491                                            rx_ring->rx_buf_len, true);
 492
 493                                         if (rx_ring->rx_buf_len
 494                                                 < IXGBE_RXBUFFER_2048)
 495                                                 print_hex_dump(KERN_INFO, "",
 496                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 497                                                   phys_to_virt(
 498                                                     rx_buffer_info->page_dma +
 499                                                     rx_buffer_info->page_offset
 500                                                   ),
 501                                                   PAGE_SIZE/2, true);
 502                                 }
 503                         }
 504
 505                         if (i == rx_ring->next_to_use)
 506                                 printk(KERN_CONT " NTU\n");
 507                         else if (i == rx_ring->next_to_clean)
 508                                 printk(KERN_CONT " NTC\n");
 509                         else
 510                                 printk(KERN_CONT "\n");
 511
 512                 }
 513         }
 514
 515 exit:
 516         return;
 517 }
 518
 519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 520 {
 521         u32 ctrl_ext;
 522
 523         /* Let firmware take over control of h/w */
 524         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 526                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 527 }
 528
 529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 530 {
 531         u32 ctrl_ext;
 532
 533         /* Let firmware know the driver has taken over */
 534         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 536                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 537 }
 538
 539 /*
 540  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 541  * @adapter: pointer to adapter struct
 542  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 543  * @queue: queue to map the corresponding interrupt to
 544  * @msix_vector: the vector to map to the corresponding queue
 545  *
 546  */
 547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 548                            u8 queue, u8 msix_vector)
 549 {
 550         u32 ivar, index;
 551         struct ixgbe_hw *hw = &adapter->hw;
 552         switch (hw->mac.type) {
 553         case ixgbe_mac_82598EB:
 554                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 555                 if (direction == -1)
 556                         direction = 0;
 557                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 558                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 559                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 560                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 561                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 562                 break;
 563         case ixgbe_mac_82599EB:
 564                 if (direction == -1) {
 565                         /* other causes */
 566                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 567                         index = ((queue & 1) * 8);
 568                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 569                         ivar &= ~(0xFF << index);
 570                         ivar |= (msix_vector << index);
 571                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 572                         break;
 573                 } else {
 574                         /* tx or rx causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((16 * (queue & 1)) + (8 * direction));
 577                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 581                         break;
 582                 }
 583         default:
 584                 break;
 585         }
 586 }
 587
 588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 589                                           u64 qmask)
 590 {
 591         u32 mask;
 592
 593         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596         } else {
 597                 mask = (qmask & 0xFFFFFFFF);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 599                 mask = (qmask >> 32);
 600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 601         }
 602 }
 603
 604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 605                                              struct ixgbe_tx_buffer
 606                                              *tx_buffer_info)
 607 {
 608         if (tx_buffer_info->dma) {
 609                 if (tx_buffer_info->mapped_as_page)
 610                         dma_unmap_page(&adapter->pdev->dev,
 611                                        tx_buffer_info->dma,
 612                                        tx_buffer_info->length,
 613                                        DMA_TO_DEVICE);
 614                 else
 615                         dma_unmap_single(&adapter->pdev->dev,
 616                                          tx_buffer_info->dma,
 617                                          tx_buffer_info->length,
 618                                          DMA_TO_DEVICE);
 619                 tx_buffer_info->dma = 0;
 620         }
 621         if (tx_buffer_info->skb) {
 622                 dev_kfree_skb_any(tx_buffer_info->skb);
 623                 tx_buffer_info->skb = NULL;
 624         }
 625         tx_buffer_info->time_stamp = 0;
 626         /* tx_buffer_info must be completely set up in the transmit path */
 627 }
 628
 629 /**
 630  * ixgbe_tx_xon_state - check the tx ring xon state
 631  * @adapter: the ixgbe adapter
 632  * @tx_ring: the corresponding tx_ring
 633  *
 634  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 635  * corresponding TC of this tx_ring when checking TFCS.
 636  *
 637  * Returns : true if in xon state (currently not paused)
 638  */
 639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 640                                       struct ixgbe_ring *tx_ring)
 641 {
 642         u32 txoff = IXGBE_TFCS_TXOFF;
 643
 644 #ifdef CONFIG_IXGBE_DCB
 645         if (adapter->dcb_cfg.pfc_mode_enable) {
 646                 int tc;
 647                 int reg_idx = tx_ring->reg_idx;
 648                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 649
 650                 switch (adapter->hw.mac.type) {
 651                 case ixgbe_mac_82598EB:
 652                         tc = reg_idx >> 2;
 653                         txoff = IXGBE_TFCS_TXOFF0;
 654                         break;
 655                 case ixgbe_mac_82599EB:
 656                         tc = 0;
 657                         txoff = IXGBE_TFCS_TXOFF;
 658                         if (dcb_i == 8) {
 659                                 /* TC0, TC1 */
 660                                 tc = reg_idx >> 5;
 661                                 if (tc == 2) /* TC2, TC3 */
 662                                         tc += (reg_idx - 64) >> 4;
 663                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 664                                         tc += 1 + ((reg_idx - 96) >> 3);
 665                         } else if (dcb_i == 4) {
 666                                 /* TC0, TC1 */
 667                                 tc = reg_idx >> 6;
 668                                 if (tc == 1) {
 669                                         tc += (reg_idx - 64) >> 5;
 670                                         if (tc == 2) /* TC2, TC3 */
 671                                                 tc += (reg_idx - 96) >> 4;
 672                                 }
 673                         }
 674                         break;
 675                 default:
 676                         tc = 0;
 677                 }
 678                 txoff <<= tc;
 679         }
 680 #endif
 681         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 682 }
 683
 684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 685                                        struct ixgbe_ring *tx_ring,
 686                                        unsigned int eop)
 687 {
 688         struct ixgbe_hw *hw = &adapter->hw;
 689
 690         /* Detect a transmit hang in hardware, this serializes the
 691          * check with the clearing of time_stamp and movement of eop */
 692         adapter->detect_tx_hung = false;
 693         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 694             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 695             ixgbe_tx_xon_state(adapter, tx_ring)) {
 696                 /* detected Tx unit hang */
 697                 union ixgbe_adv_tx_desc *tx_desc;
 698                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 699                 e_err(drv, "Detected Tx Unit Hang\n"
 700                       "  Tx Queue             <%d>\n"
 701                       "  TDH, TDT             <%x>, <%x>\n"
 702                       "  next_to_use          <%x>\n"
 703                       "  next_to_clean        <%x>\n"
 704                       "tx_buffer_info[next_to_clean]\n"
 705                       "  time_stamp           <%lx>\n"
 706                       "  jiffies              <%lx>\n",
 707                       tx_ring->queue_index,
 708                       IXGBE_READ_REG(hw, tx_ring->head),
 709                       IXGBE_READ_REG(hw, tx_ring->tail),
 710                       tx_ring->next_to_use, eop,
 711                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 712                 return true;
 713         }
 714
 715         return false;
 716 }
 717
 718 #define IXGBE_MAX_TXD_PWR       14
 719 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 720
 721 /* Tx Descriptors needed, worst case */
 722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 723                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 725         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 726
 727 static void ixgbe_tx_timeout(struct net_device *netdev);
 728
 729 /**
 730  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 731  * @q_vector: structure containing interrupt and ring information
 732  * @tx_ring: tx ring to clean
 733  **/
 734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 735                                struct ixgbe_ring *tx_ring)
 736 {
 737         struct ixgbe_adapter *adapter = q_vector->adapter;
 738         struct net_device *netdev = adapter->netdev;
 739         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 740         struct ixgbe_tx_buffer *tx_buffer_info;
 741         unsigned int i, eop, count = 0;
 742         unsigned int total_bytes = 0, total_packets = 0;
 743
 744         i = tx_ring->next_to_clean;
 745         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 746         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 747
 748         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 749                (count < tx_ring->work_limit)) {
 750                 bool cleaned = false;
 751                 rmb(); /* read buffer_info after eop_desc */
 752                 for ( ; !cleaned; count++) {
 753                         struct sk_buff *skb;
 754                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 755                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 756                         cleaned = (i == eop);
 757                         skb = tx_buffer_info->skb;
 758
 759                         if (cleaned && skb) {
 760                                 unsigned int segs, bytecount;
 761                                 unsigned int hlen = skb_headlen(skb);
 762
 763                                 /* gso_segs is currently only valid for tcp */
 764                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 765 #ifdef IXGBE_FCOE
 766                                 /* adjust for FCoE Sequence Offload */
 767                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 768                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 769                                     skb_is_gso(skb)) {
 770                                         hlen = skb_transport_offset(skb) +
 771                                                 sizeof(struct fc_frame_header) +
 772                                                 sizeof(struct fcoe_crc_eof);
 773                                         segs = DIV_ROUND_UP(skb->len - hlen,
 774                                                 skb_shinfo(skb)->gso_size);
 775                                 }
 776 #endif /* IXGBE_FCOE */
 777                                 /* multiply data chunks by size of headers */
 778                                 bytecount = ((segs - 1) * hlen) + skb->len;
 779                                 total_packets += segs;
 780                                 total_bytes += bytecount;
 781                         }
 782
 783                         ixgbe_unmap_and_free_tx_resource(adapter,
 784                                                          tx_buffer_info);
 785
 786                         tx_desc->wb.status = 0;
 787
 788                         i++;
 789                         if (i == tx_ring->count)
 790                                 i = 0;
 791                 }
 792
 793                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 794                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 795         }
 796
 797         tx_ring->next_to_clean = i;
 798
 799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 800         if (unlikely(count && netif_carrier_ok(netdev) &&
 801                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 802                 /* Make sure that anybody stopping the queue after this
 803                  * sees the new next_to_clean.
 804                  */
 805                 smp_mb();
 806                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 807                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 808                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 809                         ++tx_ring->restart_queue;
 810                 }
 811         }
 812
 813         if (adapter->detect_tx_hung) {
 814                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 815                         /* schedule immediate reset if we believe we hung */
 816                         e_info(probe, "tx hang %d detected, resetting "
 817                                "adapter\n", adapter->tx_timeout_count + 1);
 818                         ixgbe_tx_timeout(adapter->netdev);
 819                 }
 820         }
 821
 822         /* re-arm the interrupt */
 823         if (count >= tx_ring->work_limit)
 824                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 825
 826         tx_ring->total_bytes += total_bytes;
 827         tx_ring->total_packets += total_packets;
 828         tx_ring->stats.packets += total_packets;
 829         tx_ring->stats.bytes += total_bytes;
 830         return (count < tx_ring->work_limit);
 831 }
 832
 833 #ifdef CONFIG_IXGBE_DCA
 834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 835                                 struct ixgbe_ring *rx_ring)
 836 {
 837         u32 rxctrl;
 838         int cpu = get_cpu();
 839         int q = rx_ring->reg_idx;
 840
 841         if (rx_ring->cpu != cpu) {
 842                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 843                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 844                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 845                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 846                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 847                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 848                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 849                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 850                 }
 851                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 852                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 853                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 854                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 855                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 856                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 857                 rx_ring->cpu = cpu;
 858         }
 859         put_cpu();
 860 }
 861
 862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 863                                 struct ixgbe_ring *tx_ring)
 864 {
 865         u32 txctrl;
 866         int cpu = get_cpu();
 867         int q = tx_ring->reg_idx;
 868         struct ixgbe_hw *hw = &adapter->hw;
 869
 870         if (tx_ring->cpu != cpu) {
 871                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 872                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 873                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 874                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 875                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 876                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 877                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 878                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 879                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 880                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 881                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 882                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 883                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 884                 }
 885                 tx_ring->cpu = cpu;
 886         }
 887         put_cpu();
 888 }
 889
 890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 891 {
 892         int i;
 893
 894         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 895                 return;
 896
 897         /* always use CB2 mode, difference is masked in the CB driver */
 898         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 899
 900         for (i = 0; i < adapter->num_tx_queues; i++) {
 901                 adapter->tx_ring[i]->cpu = -1;
 902                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 903         }
 904         for (i = 0; i < adapter->num_rx_queues; i++) {
 905                 adapter->rx_ring[i]->cpu = -1;
 906                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 907         }
 908 }
 909
 910 static int __ixgbe_notify_dca(struct device *dev, void *data)
 911 {
 912         struct net_device *netdev = dev_get_drvdata(dev);
 913         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 914         unsigned long event = *(unsigned long *)data;
 915
 916         switch (event) {
 917         case DCA_PROVIDER_ADD:
 918                 /* if we're already enabled, don't do it again */
 919                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 920                         break;
 921                 if (dca_add_requester(dev) == 0) {
 922                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 923                         ixgbe_setup_dca(adapter);
 924                         break;
 925                 }
 926                 /* Fall Through since DCA is disabled. */
 927         case DCA_PROVIDER_REMOVE:
 928                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 929                         dca_remove_requester(dev);
 930                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 931                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 932                 }
 933                 break;
 934         }
 935
 936         return 0;
 937 }
 938
 939 #endif /* CONFIG_IXGBE_DCA */
 940 /**
 941  * ixgbe_receive_skb - Send a completed packet up the stack
 942  * @adapter: board private structure
 943  * @skb: packet to send up
 944  * @status: hardware indication of status of receive
 945  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 946  * @rx_desc: rx descriptor
 947  **/
 948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 949                               struct sk_buff *skb, u8 status,
 950                               struct ixgbe_ring *ring,
 951                               union ixgbe_adv_rx_desc *rx_desc)
 952 {
 953         struct ixgbe_adapter *adapter = q_vector->adapter;
 954         struct napi_struct *napi = &q_vector->napi;
 955         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 956         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 957
 958         skb_record_rx_queue(skb, ring->queue_index);
 959         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 960                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 961                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 962                 else
 963                         napi_gro_receive(napi, skb);
 964         } else {
 965                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 966                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 967                 else
 968                         netif_rx(skb);
 969         }
 970 }
 971
 972 /**
 973  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 974  * @adapter: address of board private structure
 975  * @status_err: hardware indication of status of receive
 976  * @skb: skb currently being received and modified
 977  **/
 978 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 979                                      union ixgbe_adv_rx_desc *rx_desc,
 980                                      struct sk_buff *skb)
 981 {
 982         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 983
 984         skb->ip_summed = CHECKSUM_NONE;
 985
 986         /* Rx csum disabled */
 987         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 988                 return;
 989
 990         /* if IP and error */
 991         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 992             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 993                 adapter->hw_csum_rx_error++;
 994                 return;
 995         }
 996
 997         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 998                 return;
 999
1000         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1001                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1002
1003                 /*
1004                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1005                  * checksum errors.
1006                  */
1007                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1008                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1009                         return;
1010
1011                 adapter->hw_csum_rx_error++;
1012                 return;
1013         }
1014
1015         /* It must be a TCP or UDP packet with a valid checksum */
1016         skb->ip_summed = CHECKSUM_UNNECESSARY;
1017 }
1018
1019 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1020                                          struct ixgbe_ring *rx_ring, u32 val)
1021 {
1022         /*
1023          * Force memory writes to complete before letting h/w
1024          * know there are new descriptors to fetch.  (Only
1025          * applicable for weak-ordered memory model archs,
1026          * such as IA-64).
1027          */
1028         wmb();
1029         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1030 }
1031
1032 /**
1033  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1034  * @adapter: address of board private structure
1035  **/
1036 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1037                                    struct ixgbe_ring *rx_ring,
1038                                    int cleaned_count)
1039 {
1040         struct pci_dev *pdev = adapter->pdev;
1041         union ixgbe_adv_rx_desc *rx_desc;
1042         struct ixgbe_rx_buffer *bi;
1043         unsigned int i;
1044
1045         i = rx_ring->next_to_use;
1046         bi = &rx_ring->rx_buffer_info[i];
1047
1048         while (cleaned_count--) {
1049                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1050
1051                 if (!bi->page_dma &&
1052                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1053                         if (!bi->page) {
1054                                 bi->page = alloc_page(GFP_ATOMIC);
1055                                 if (!bi->page) {
1056                                         adapter->alloc_rx_page_failed++;
1057                                         goto no_buffers;
1058                                 }
1059                                 bi->page_offset = 0;
1060                         } else {
1061                                 /* use a half page if we're re-using */
1062                                 bi->page_offset ^= (PAGE_SIZE / 2);
1063                         }
1064
1065                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1066                                                     bi->page_offset,
1067                                                     (PAGE_SIZE / 2),
1068                                                     DMA_FROM_DEVICE);
1069                 }
1070
1071                 if (!bi->skb) {
1072                         struct sk_buff *skb;
1073                         /* netdev_alloc_skb reserves 32 bytes up front!! */
1074                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1075                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
1076
1077                         if (!skb) {
1078                                 adapter->alloc_rx_buff_failed++;
1079                                 goto no_buffers;
1080                         }
1081
1082                         /* advance the data pointer to the next cache line */
1083                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1084                                           - skb->data));
1085
1086                         bi->skb = skb;
1087                         bi->dma = dma_map_single(&pdev->dev, skb->data,
1088                                                  rx_ring->rx_buf_len,
1089                                                  DMA_FROM_DEVICE);
1090                 }
1091                 /* Refresh the desc even if buffer_addrs didn't change because
1092                  * each write-back erases this info. */
1093                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096                 } else {
1097                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098                 }
1099
1100                 i++;
1101                 if (i == rx_ring->count)
1102                         i = 0;
1103                 bi = &rx_ring->rx_buffer_info[i];
1104         }
1105
1106 no_buffers:
1107         if (rx_ring->next_to_use != i) {
1108                 rx_ring->next_to_use = i;
1109                 if (i-- == 0)
1110                         i = (rx_ring->count - 1);
1111
1112                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113         }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129                 IXGBE_RXDADV_RSCCNT_MASK) >>
1130                 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135  * @skb: pointer to the last skb in the rsc queue
1136  * @count: pointer to number of packets coalesced in this context
1137  *
1138  * This function changes a queue full of hw rsc buffers into a completed
1139  * packet.  It uses the ->prev pointers to find the first packet and then
1140  * turns it into the frag list owner.
1141  **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143                                                         u64 *count)
1144 {
1145         unsigned int frag_list_size = 0;
1146
1147         while (skb->prev) {
1148                 struct sk_buff *prev = skb->prev;
1149                 frag_list_size += skb->len;
1150                 skb->prev = NULL;
1151                 skb = prev;
1152                 *count += 1;
1153         }
1154
1155         skb_shinfo(skb)->frag_list = skb->next;
1156         skb->next = NULL;
1157         skb->len += frag_list_size;
1158         skb->data_len += frag_list_size;
1159         skb->truesize += frag_list_size;
1160         return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164         dma_addr_t dma;
1165         bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171                                struct ixgbe_ring *rx_ring,
1172                                int *work_done, int work_to_do)
1173 {
1174         struct ixgbe_adapter *adapter = q_vector->adapter;
1175         struct net_device *netdev = adapter->netdev;
1176         struct pci_dev *pdev = adapter->pdev;
1177         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179         struct sk_buff *skb;
1180         unsigned int i, rsc_count = 0;
1181         u32 len, staterr;
1182         u16 hdr_info;
1183         bool cleaned = false;
1184         int cleaned_count = 0;
1185         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187         int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190         i = rx_ring->next_to_clean;
1191         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195         while (staterr & IXGBE_RXD_STAT_DD) {
1196                 u32 upper_len = 0;
1197                 if (*work_done >= work_to_do)
1198                         break;
1199                 (*work_done)++;
1200
1201                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207                         if ((len > IXGBE_RX_HDR_SIZE) ||
1208                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209                                 len = IXGBE_RX_HDR_SIZE;
1210                 } else {
1211                         len = le16_to_cpu(rx_desc->wb.upper.length);
1212                 }
1213
1214                 cleaned = true;
1215                 skb = rx_buffer_info->skb;
1216                 prefetch(skb->data);
1217                 rx_buffer_info->skb = NULL;
1218
1219                 if (rx_buffer_info->dma) {
1220                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222                                  (!(skb->prev))) {
1223                                 /*
1224                                  * When HWRSC is enabled, delay unmapping
1225                                  * of the first packet. It carries the
1226                                  * header information, HW may still
1227                                  * access the header after the writeback.
1228                                  * Only unmap it when EOP is reached
1229                                  */
1230                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232                         } else {
1233                                 dma_unmap_single(&pdev->dev,
1234                                                  rx_buffer_info->dma,
1235                                                  rx_ring->rx_buf_len,
1236                                                  DMA_FROM_DEVICE);
1237                         }
1238                         rx_buffer_info->dma = 0;
1239                         skb_put(skb, len);
1240                 }
1241
1242                 if (upper_len) {
1243                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245                         rx_buffer_info->page_dma = 0;
1246                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247                                            rx_buffer_info->page,
1248                                            rx_buffer_info->page_offset,
1249                                            upper_len);
1250
1251                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252                             (page_count(rx_buffer_info->page) != 1))
1253                                 rx_buffer_info->page = NULL;
1254                         else
1255                                 get_page(rx_buffer_info->page);
1256
1257                         skb->len += upper_len;
1258                         skb->data_len += upper_len;
1259                         skb->truesize += upper_len;
1260                 }
1261
1262                 i++;
1263                 if (i == rx_ring->count)
1264                         i = 0;
1265
1266                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267                 prefetch(next_rxd);
1268                 cleaned_count++;
1269
1270                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273                 if (rsc_count) {
1274                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275                                      IXGBE_RXDADV_NEXTP_SHIFT;
1276                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1277                 } else {
1278                         next_buffer = &rx_ring->rx_buffer_info[i];
1279                 }
1280
1281                 if (staterr & IXGBE_RXD_STAT_EOP) {
1282                         if (skb->prev)
1283                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286                                         dma_unmap_single(&pdev->dev,
1287                                                          IXGBE_RSC_CB(skb)->dma,
1288                                                          rx_ring->rx_buf_len,
1289                                                          DMA_FROM_DEVICE);
1290                                         IXGBE_RSC_CB(skb)->dma = 0;
1291                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1292                                 }
1293                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295                                 else
1296                                         rx_ring->rsc_count++;
1297                                 rx_ring->rsc_flush++;
1298                         }
1299                         rx_ring->stats.packets++;
1300                         rx_ring->stats.bytes += skb->len;
1301                 } else {
1302                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303                                 rx_buffer_info->skb = next_buffer->skb;
1304                                 rx_buffer_info->dma = next_buffer->dma;
1305                                 next_buffer->skb = skb;
1306                                 next_buffer->dma = 0;
1307                         } else {
1308                                 skb->next = next_buffer->skb;
1309                                 skb->next->prev = skb;
1310                         }
1311                         rx_ring->non_eop_descs++;
1312                         goto next_desc;
1313                 }
1314
1315                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316                         dev_kfree_skb_irq(skb);
1317                         goto next_desc;
1318                 }
1319
1320                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322                 /* probably a little skewed due to removing CRC */
1323                 total_rx_bytes += skb->len;
1324                 total_rx_packets++;
1325
1326                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331                         if (!ddp_bytes)
1332                                 goto next_desc;
1333                 }
1334 #endif /* IXGBE_FCOE */
1335                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338                 rx_desc->wb.upper.status_error = 0;
1339
1340                 /* return some buffers to hardware, one at a time is too slow */
1341                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343                         cleaned_count = 0;
1344                 }
1345
1346                 /* use prefetched values */
1347                 rx_desc = next_rxd;
1348                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351         }
1352
1353         rx_ring->next_to_clean = i;
1354         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356         if (cleaned_count)
1357                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360         /* include DDPed FCoE data */
1361         if (ddp_bytes > 0) {
1362                 unsigned int mss;
1363
1364                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365                         sizeof(struct fc_frame_header) -
1366                         sizeof(struct fcoe_crc_eof);
1367                 if (mss > 512)
1368                         mss &= ~511;
1369                 total_rx_bytes += ddp_bytes;
1370                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371         }
1372 #endif /* IXGBE_FCOE */
1373
1374         rx_ring->total_packets += total_rx_packets;
1375         rx_ring->total_bytes += total_rx_bytes;
1376         netdev->stats.rx_bytes += total_rx_bytes;
1377         netdev->stats.rx_packets += total_rx_packets;
1378
1379         return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384  * ixgbe_configure_msix - Configure MSI-X hardware
1385  * @adapter: board private structure
1386  *
1387  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388  * interrupts.
1389  **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392         struct ixgbe_q_vector *q_vector;
1393         int i, j, q_vectors, v_idx, r_idx;
1394         u32 mask;
1395
1396         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398         /*
1399          * Populate the IVAR table and set the ITR values to the
1400          * corresponding register.
1401          */
1402         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403                 q_vector = adapter->q_vector[v_idx];
1404                 /* XXX for_each_set_bit(...) */
1405                 r_idx = find_first_bit(q_vector->rxr_idx,
1406                                        adapter->num_rx_queues);
1407
1408                 for (i = 0; i < q_vector->rxr_count; i++) {
1409                         j = adapter->rx_ring[r_idx]->reg_idx;
1410                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1411                         r_idx = find_next_bit(q_vector->rxr_idx,
1412                                               adapter->num_rx_queues,
1413                                               r_idx + 1);
1414                 }
1415                 r_idx = find_first_bit(q_vector->txr_idx,
1416                                        adapter->num_tx_queues);
1417
1418                 for (i = 0; i < q_vector->txr_count; i++) {
1419                         j = adapter->tx_ring[r_idx]->reg_idx;
1420                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1421                         r_idx = find_next_bit(q_vector->txr_idx,
1422                                               adapter->num_tx_queues,
1423                                               r_idx + 1);
1424                 }
1425
1426                 if (q_vector->txr_count && !q_vector->rxr_count)
1427                         /* tx only */
1428                         q_vector->eitr = adapter->tx_eitr_param;
1429                 else if (q_vector->rxr_count)
1430                         /* rx or mixed */
1431                         q_vector->eitr = adapter->rx_eitr_param;
1432
1433                 ixgbe_write_eitr(q_vector);
1434         }
1435
1436         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438                                v_idx);
1439         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
1443         /* set up to autoclear timer, and the vectors */
1444         mask = IXGBE_EIMS_ENABLE_MASK;
1445         if (adapter->num_vfs)
1446                 mask &= ~(IXGBE_EIMS_OTHER |
1447                           IXGBE_EIMS_MAILBOX |
1448                           IXGBE_EIMS_LSC);
1449         else
1450                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1452 }
1453
1454 enum latency_range {
1455         lowest_latency = 0,
1456         low_latency = 1,
1457         bulk_latency = 2,
1458         latency_invalid = 255
1459 };
1460
1461 /**
1462  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463  * @adapter: pointer to adapter
1464  * @eitr: eitr setting (ints per sec) to give last timeslice
1465  * @itr_setting: current throttle rate in ints/second
1466  * @packets: the number of packets during this measurement interval
1467  * @bytes: the number of bytes during this measurement interval
1468  *
1469  *      Stores a new ITR value based on packets and byte
1470  *      counts during the last interrupt.  The advantage of per interrupt
1471  *      computation is faster updates and more accurate ITR for the current
1472  *      traffic pattern.  Constants in this function were computed
1473  *      based on theoretical maximum wire speed and thresholds were set based
1474  *      on testing data as well as attempting to minimize response time
1475  *      while increasing bulk throughput.
1476  *      this functionality is controlled by the InterruptThrottleRate module
1477  *      parameter (see ixgbe_param.c)
1478  **/
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480                            u32 eitr, u8 itr_setting,
1481                            int packets, int bytes)
1482 {
1483         unsigned int retval = itr_setting;
1484         u32 timepassed_us;
1485         u64 bytes_perint;
1486
1487         if (packets == 0)
1488                 goto update_itr_done;
1489
1490
1491         /* simple throttlerate management
1492          *    0-20MB/s lowest (100000 ints/s)
1493          *   20-100MB/s low   (20000 ints/s)
1494          *  100-1249MB/s bulk (8000 ints/s)
1495          */
1496         /* what was last interrupt timeslice? */
1497         timepassed_us = 1000000/eitr;
1498         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500         switch (itr_setting) {
1501         case lowest_latency:
1502                 if (bytes_perint > adapter->eitr_low)
1503                         retval = low_latency;
1504                 break;
1505         case low_latency:
1506                 if (bytes_perint > adapter->eitr_high)
1507                         retval = bulk_latency;
1508                 else if (bytes_perint <= adapter->eitr_low)
1509                         retval = lowest_latency;
1510                 break;
1511         case bulk_latency:
1512                 if (bytes_perint <= adapter->eitr_high)
1513                         retval = low_latency;
1514                 break;
1515         }
1516
1517 update_itr_done:
1518         return retval;
1519 }
1520
1521 /**
1522  * ixgbe_write_eitr - write EITR register in hardware specific way
1523  * @q_vector: structure containing interrupt and ring information
1524  *
1525  * This function is made to be called by ethtool and by the driver
1526  * when it needs to update EITR registers at runtime.  Hardware
1527  * specific quirks/differences are taken care of here.
1528  */
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1530 {
1531         struct ixgbe_adapter *adapter = q_vector->adapter;
1532         struct ixgbe_hw *hw = &adapter->hw;
1533         int v_idx = q_vector->v_idx;
1534         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
1536         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537                 /* must write high and low 16 bits to reset counter */
1538                 itr_reg |= (itr_reg << 16);
1539         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1540                 /*
1541                  * 82599 can support a value of zero, so allow it for
1542                  * max interrupt rate, but there is an errata where it can
1543                  * not be zero with RSC
1544                  */
1545                 if (itr_reg == 8 &&
1546                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547                         itr_reg = 0;
1548
1549                 /*
1550                  * set the WDIS bit to not clear the timer bits and cause an
1551                  * immediate assertion of the interrupt
1552                  */
1553                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554         }
1555         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556 }
1557
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559 {
1560         struct ixgbe_adapter *adapter = q_vector->adapter;
1561         u32 new_itr;
1562         u8 current_itr, ret_itr;
1563         int i, r_idx;
1564         struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567         for (i = 0; i < q_vector->txr_count; i++) {
1568                 tx_ring = adapter->tx_ring[r_idx];
1569                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1570                                            q_vector->tx_itr,
1571                                            tx_ring->total_packets,
1572                                            tx_ring->total_bytes);
1573                 /* if the result for this queue would decrease interrupt
1574                  * rate for this vector then use that result */
1575                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576                                     q_vector->tx_itr - 1 : ret_itr);
1577                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1578                                       r_idx + 1);
1579         }
1580
1581         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582         for (i = 0; i < q_vector->rxr_count; i++) {
1583                 rx_ring = adapter->rx_ring[r_idx];
1584                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585                                            q_vector->rx_itr,
1586                                            rx_ring->total_packets,
1587                                            rx_ring->total_bytes);
1588                 /* if the result for this queue would decrease interrupt
1589                  * rate for this vector then use that result */
1590                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591                                     q_vector->rx_itr - 1 : ret_itr);
1592                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1593                                       r_idx + 1);
1594         }
1595
1596         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1597
1598         switch (current_itr) {
1599         /* counts and packets in update_itr are dependent on these numbers */
1600         case lowest_latency:
1601                 new_itr = 100000;
1602                 break;
1603         case low_latency:
1604                 new_itr = 20000; /* aka hwitr = ~200 */
1605                 break;
1606         case bulk_latency:
1607         default:
1608                 new_itr = 8000;
1609                 break;
1610         }
1611
1612         if (new_itr != q_vector->eitr) {
1613                 /* do an exponential smoothing */
1614                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1615
1616                 /* save the algorithm value here, not the smoothed one */
1617                 q_vector->eitr = new_itr;
1618
1619                 ixgbe_write_eitr(q_vector);
1620         }
1621 }
1622
1623 /**
1624  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625  * @work: pointer to work_struct containing our data
1626  **/
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1628 {
1629         struct ixgbe_adapter *adapter = container_of(work,
1630                                                      struct ixgbe_adapter,
1631                                                      check_overtemp_task);
1632         struct ixgbe_hw *hw = &adapter->hw;
1633         u32 eicr = adapter->interrupt_event;
1634
1635         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636                 switch (hw->device_id) {
1637                 case IXGBE_DEV_ID_82599_T3_LOM: {
1638                         u32 autoneg;
1639                         bool link_up = false;
1640
1641                         if (hw->mac.ops.check_link)
1642                                 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644                         if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645                             (eicr & IXGBE_EICR_LSC))
1646                                 /* Check if this is due to overtemp */
1647                                 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648                                         break;
1649                         }
1650                         return;
1651                 default:
1652                         if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653                                 return;
1654                         break;
1655                 }
1656                 e_crit(drv, "Network adapter has been stopped because it has "
1657                        "over heated. Restart the computer. If the problem "
1658                        "persists, power off the system and replace the "
1659                        "adapter\n");
1660                 /* write to clear the interrupt */
1661                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662         }
1663 }
1664
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666 {
1667         struct ixgbe_hw *hw = &adapter->hw;
1668
1669         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670             (eicr & IXGBE_EICR_GPI_SDP1)) {
1671                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1672                 /* write to clear the interrupt */
1673                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674         }
1675 }
1676
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678 {
1679         struct ixgbe_hw *hw = &adapter->hw;
1680
1681         if (eicr & IXGBE_EICR_GPI_SDP1) {
1682                 /* Clear the interrupt */
1683                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684                 schedule_work(&adapter->multispeed_fiber_task);
1685         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686                 /* Clear the interrupt */
1687                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688                 schedule_work(&adapter->sfp_config_module_task);
1689         } else {
1690                 /* Interrupt isn't for us... */
1691                 return;
1692         }
1693 }
1694
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696 {
1697         struct ixgbe_hw *hw = &adapter->hw;
1698
1699         adapter->lsc_int++;
1700         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701         adapter->link_check_timeout = jiffies;
1702         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704                 IXGBE_WRITE_FLUSH(hw);
1705                 schedule_work(&adapter->watchdog_task);
1706         }
1707 }
1708
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         u32 eicr;
1715
1716         /*
1717          * Workaround for Silicon errata.  Use clear-by-write instead
1718          * of clear-by-read.  Reading with EICS will return the
1719          * interrupt causes without clearing, which later be done
1720          * with the write to EICR.
1721          */
1722         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1724
1725         if (eicr & IXGBE_EICR_LSC)
1726                 ixgbe_check_lsc(adapter);
1727
1728         if (eicr & IXGBE_EICR_MAILBOX)
1729                 ixgbe_msg_task(adapter);
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB)
1732                 ixgbe_check_fan_failure(adapter, eicr);
1733
1734         if (hw->mac.type == ixgbe_mac_82599EB) {
1735                 ixgbe_check_sfp_event(adapter, eicr);
1736                 adapter->interrupt_event = eicr;
1737                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739                         schedule_work(&adapter->check_overtemp_task);
1740
1741                 /* Handle Flow Director Full threshold interrupt */
1742                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743                         int i;
1744                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745                         /* Disable transmits before FDIR Re-initialization */
1746                         netif_tx_stop_all_queues(netdev);
1747                         for (i = 0; i < adapter->num_tx_queues; i++) {
1748                                 struct ixgbe_ring *tx_ring =
1749                                                             adapter->tx_ring[i];
1750                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751                                                        &tx_ring->reinit_state))
1752                                         schedule_work(&adapter->fdir_reinit_task);
1753                         }
1754                 }
1755         }
1756         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1758
1759         return IRQ_HANDLED;
1760 }
1761
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763                                            u64 qmask)
1764 {
1765         u32 mask;
1766
1767         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770         } else {
1771                 mask = (qmask & 0xFFFFFFFF);
1772                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773                 mask = (qmask >> 32);
1774                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775         }
1776         /* skip the flush */
1777 }
1778
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780                                             u64 qmask)
1781 {
1782         u32 mask;
1783
1784         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787         } else {
1788                 mask = (qmask & 0xFFFFFFFF);
1789                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790                 mask = (qmask >> 32);
1791                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792         }
1793         /* skip the flush */
1794 }
1795
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797 {
1798         struct ixgbe_q_vector *q_vector = data;
1799         struct ixgbe_adapter  *adapter = q_vector->adapter;
1800         struct ixgbe_ring     *tx_ring;
1801         int i, r_idx;
1802
1803         if (!q_vector->txr_count)
1804                 return IRQ_HANDLED;
1805
1806         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807         for (i = 0; i < q_vector->txr_count; i++) {
1808                 tx_ring = adapter->tx_ring[r_idx];
1809                 tx_ring->total_bytes = 0;
1810                 tx_ring->total_packets = 0;
1811                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1812                                       r_idx + 1);
1813         }
1814
1815         /* EIAM disabled interrupts (on this vector) for us */
1816         napi_schedule(&q_vector->napi);
1817
1818         return IRQ_HANDLED;
1819 }
1820
1821 /**
1822  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823  * @irq: unused
1824  * @data: pointer to our q_vector struct for this interrupt vector
1825  **/
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827 {
1828         struct ixgbe_q_vector *q_vector = data;
1829         struct ixgbe_adapter  *adapter = q_vector->adapter;
1830         struct ixgbe_ring  *rx_ring;
1831         int r_idx;
1832         int i;
1833
1834         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835         for (i = 0;  i < q_vector->rxr_count; i++) {
1836                 rx_ring = adapter->rx_ring[r_idx];
1837                 rx_ring->total_bytes = 0;
1838                 rx_ring->total_packets = 0;
1839                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840                                       r_idx + 1);
1841         }
1842
1843         if (!q_vector->rxr_count)
1844                 return IRQ_HANDLED;
1845
1846         /* disable interrupts on this vector only */
1847         /* EIAM disabled interrupts (on this vector) for us */
1848         napi_schedule(&q_vector->napi);
1849
1850         return IRQ_HANDLED;
1851 }
1852
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854 {
1855         struct ixgbe_q_vector *q_vector = data;
1856         struct ixgbe_adapter  *adapter = q_vector->adapter;
1857         struct ixgbe_ring  *ring;
1858         int r_idx;
1859         int i;
1860
1861         if (!q_vector->txr_count && !q_vector->rxr_count)
1862                 return IRQ_HANDLED;
1863
1864         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865         for (i = 0; i < q_vector->txr_count; i++) {
1866                 ring = adapter->tx_ring[r_idx];
1867                 ring->total_bytes = 0;
1868                 ring->total_packets = 0;
1869                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870                                       r_idx + 1);
1871         }
1872
1873         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874         for (i = 0; i < q_vector->rxr_count; i++) {
1875                 ring = adapter->rx_ring[r_idx];
1876                 ring->total_bytes = 0;
1877                 ring->total_packets = 0;
1878                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879                                       r_idx + 1);
1880         }
1881
1882         /* EIAM disabled interrupts (on this vector) for us */
1883         napi_schedule(&q_vector->napi);
1884
1885         return IRQ_HANDLED;
1886 }
1887
1888 /**
1889  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890  * @napi: napi struct with our devices info in it
1891  * @budget: amount of work driver is allowed to do this pass, in packets
1892  *
1893  * This function is optimized for cleaning one queue only on a single
1894  * q_vector!!!
1895  **/
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897 {
1898         struct ixgbe_q_vector *q_vector =
1899                                container_of(napi, struct ixgbe_q_vector, napi);
1900         struct ixgbe_adapter *adapter = q_vector->adapter;
1901         struct ixgbe_ring *rx_ring = NULL;
1902         int work_done = 0;
1903         long r_idx;
1904
1905         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906         rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909                 ixgbe_update_rx_dca(adapter, rx_ring);
1910 #endif
1911
1912         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1913
1914         /* If all Rx work done, exit the polling mode */
1915         if (work_done < budget) {
1916                 napi_complete(napi);
1917                 if (adapter->rx_itr_setting & 1)
1918                         ixgbe_set_itr_msix(q_vector);
1919                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920                         ixgbe_irq_enable_queues(adapter,
1921                                                 ((u64)1 << q_vector->v_idx));
1922         }
1923
1924         return work_done;
1925 }
1926
1927 /**
1928  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929  * @napi: napi struct with our devices info in it
1930  * @budget: amount of work driver is allowed to do this pass, in packets
1931  *
1932  * This function will clean more than one rx queue associated with a
1933  * q_vector.
1934  **/
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1936 {
1937         struct ixgbe_q_vector *q_vector =
1938                                container_of(napi, struct ixgbe_q_vector, napi);
1939         struct ixgbe_adapter *adapter = q_vector->adapter;
1940         struct ixgbe_ring *ring = NULL;
1941         int work_done = 0, i;
1942         long r_idx;
1943         bool tx_clean_complete = true;
1944
1945         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946         for (i = 0; i < q_vector->txr_count; i++) {
1947                 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950                         ixgbe_update_tx_dca(adapter, ring);
1951 #endif
1952                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954                                       r_idx + 1);
1955         }
1956
1957         /* attempt to distribute budget to each queue fairly, but don't allow
1958          * the budget to go below 1 because we'll exit polling */
1959         budget /= (q_vector->rxr_count ?: 1);
1960         budget = max(budget, 1);
1961         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962         for (i = 0; i < q_vector->rxr_count; i++) {
1963                 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966                         ixgbe_update_rx_dca(adapter, ring);
1967 #endif
1968                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970                                       r_idx + 1);
1971         }
1972
1973         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974         ring = adapter->rx_ring[r_idx];
1975         /* If all Rx work done, exit the polling mode */
1976         if (work_done < budget) {
1977                 napi_complete(napi);
1978                 if (adapter->rx_itr_setting & 1)
1979                         ixgbe_set_itr_msix(q_vector);
1980                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981                         ixgbe_irq_enable_queues(adapter,
1982                                                 ((u64)1 << q_vector->v_idx));
1983                 return 0;
1984         }
1985
1986         return work_done;
1987 }
1988
1989 /**
1990  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991  * @napi: napi struct with our devices info in it
1992  * @budget: amount of work driver is allowed to do this pass, in packets
1993  *
1994  * This function is optimized for cleaning one queue only on a single
1995  * q_vector!!!
1996  **/
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998 {
1999         struct ixgbe_q_vector *q_vector =
2000                                container_of(napi, struct ixgbe_q_vector, napi);
2001         struct ixgbe_adapter *adapter = q_vector->adapter;
2002         struct ixgbe_ring *tx_ring = NULL;
2003         int work_done = 0;
2004         long r_idx;
2005
2006         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007         tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010                 ixgbe_update_tx_dca(adapter, tx_ring);
2011 #endif
2012
2013         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014                 work_done = budget;
2015
2016         /* If all Tx work done, exit the polling mode */
2017         if (work_done < budget) {
2018                 napi_complete(napi);
2019                 if (adapter->tx_itr_setting & 1)
2020                         ixgbe_set_itr_msix(q_vector);
2021                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023         }
2024
2025         return work_done;
2026 }
2027
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2029                                      int r_idx)
2030 {
2031         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033         set_bit(r_idx, q_vector->rxr_idx);
2034         q_vector->rxr_count++;
2035 }
2036
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2038                                      int t_idx)
2039 {
2040         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042         set_bit(t_idx, q_vector->txr_idx);
2043         q_vector->txr_count++;
2044 }
2045
2046 /**
2047  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048  * @adapter: board private structure to initialize
2049  * @vectors: allotted vector count for descriptor rings
2050  *
2051  * This function maps descriptor rings to the queue-specific vectors
2052  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2053  * one vector per ring/queue, but on a constrained vector budget, we
2054  * group the rings as "efficiently" as possible.  You would add new
2055  * mapping configurations in here.
2056  **/
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2058                                       int vectors)
2059 {
2060         int v_start = 0;
2061         int rxr_idx = 0, txr_idx = 0;
2062         int rxr_remaining = adapter->num_rx_queues;
2063         int txr_remaining = adapter->num_tx_queues;
2064         int i, j;
2065         int rqpv, tqpv;
2066         int err = 0;
2067
2068         /* No mapping required if MSI-X is disabled. */
2069         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070                 goto out;
2071
2072         /*
2073          * The ideal configuration...
2074          * We have enough vectors to map one per queue.
2075          */
2076         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2079
2080                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081                         map_vector_to_txq(adapter, v_start, txr_idx);
2082
2083                 goto out;
2084         }
2085
2086         /*
2087          * If we don't have enough vectors for a 1-to-1
2088          * mapping, we'll have to group them so there are
2089          * multiple queues per vector.
2090          */
2091         /* Re-adjusting *qpv takes care of the remainder. */
2092         for (i = v_start; i < vectors; i++) {
2093                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094                 for (j = 0; j < rqpv; j++) {
2095                         map_vector_to_rxq(adapter, i, rxr_idx);
2096                         rxr_idx++;
2097                         rxr_remaining--;
2098                 }
2099         }
2100         for (i = v_start; i < vectors; i++) {
2101                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102                 for (j = 0; j < tqpv; j++) {
2103                         map_vector_to_txq(adapter, i, txr_idx);
2104                         txr_idx++;
2105                         txr_remaining--;
2106                 }
2107         }
2108
2109 out:
2110         return err;
2111 }
2112
2113 /**
2114  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115  * @adapter: board private structure
2116  *
2117  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118  * interrupts from the kernel.
2119  **/
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121 {
2122         struct net_device *netdev = adapter->netdev;
2123         irqreturn_t (*handler)(int, void *);
2124         int i, vector, q_vectors, err;
2125         int ri=0, ti=0;
2126
2127         /* Decrement for Other and TCP Timer vectors */
2128         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130         /* Map the Tx/Rx rings to the vectors we were allotted. */
2131         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132         if (err)
2133                 goto out;
2134
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137                          &ixgbe_msix_clean_many)
2138         for (vector = 0; vector < q_vectors; vector++) {
2139                 handler = SET_HANDLER(adapter->q_vector[vector]);
2140
2141                 if(handler == &ixgbe_msix_clean_rx) {
2142                         sprintf(adapter->name[vector], "%s-%s-%d",
2143                                 netdev->name, "rx", ri++);
2144                 }
2145                 else if(handler == &ixgbe_msix_clean_tx) {
2146                         sprintf(adapter->name[vector], "%s-%s-%d",
2147                                 netdev->name, "tx", ti++);
2148                 }
2149                 else
2150                         sprintf(adapter->name[vector], "%s-%s-%d",
2151                                 netdev->name, "TxRx", vector);
2152
2153                 err = request_irq(adapter->msix_entries[vector].vector,
2154                                   handler, 0, adapter->name[vector],
2155                                   adapter->q_vector[vector]);
2156                 if (err) {
2157                         e_err(probe, "request_irq failed for MSIX interrupt "
2158                               "Error: %d\n", err);
2159                         goto free_queue_irqs;
2160                 }
2161         }
2162
2163         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164         err = request_irq(adapter->msix_entries[vector].vector,
2165                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2166         if (err) {
2167                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2168                 goto free_queue_irqs;
2169         }
2170
2171         return 0;
2172
2173 free_queue_irqs:
2174         for (i = vector - 1; i >= 0; i--)
2175                 free_irq(adapter->msix_entries[--vector].vector,
2176                          adapter->q_vector[i]);
2177         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178         pci_disable_msix(adapter->pdev);
2179         kfree(adapter->msix_entries);
2180         adapter->msix_entries = NULL;
2181 out:
2182         return err;
2183 }
2184
2185 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186 {
2187         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2188         u8 current_itr;
2189         u32 new_itr = q_vector->eitr;
2190         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2192
2193         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2194                                             q_vector->tx_itr,
2195                                             tx_ring->total_packets,
2196                                             tx_ring->total_bytes);
2197         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2198                                             q_vector->rx_itr,
2199                                             rx_ring->total_packets,
2200                                             rx_ring->total_bytes);
2201
2202         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2203
2204         switch (current_itr) {
2205         /* counts and packets in update_itr are dependent on these numbers */
2206         case lowest_latency:
2207                 new_itr = 100000;
2208                 break;
2209         case low_latency:
2210                 new_itr = 20000; /* aka hwitr = ~200 */
2211                 break;
2212         case bulk_latency:
2213                 new_itr = 8000;
2214                 break;
2215         default:
2216                 break;
2217         }
2218
2219         if (new_itr != q_vector->eitr) {
2220                 /* do an exponential smoothing */
2221                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2222
2223                 /* save the algorithm value here, not the smoothed one */
2224                 q_vector->eitr = new_itr;
2225
2226                 ixgbe_write_eitr(q_vector);
2227         }
2228 }
2229
2230 /**
2231  * ixgbe_irq_enable - Enable default interrupt generation settings
2232  * @adapter: board private structure
2233  **/
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235 {
2236         u32 mask;
2237
2238         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240                 mask |= IXGBE_EIMS_GPI_SDP0;
2241         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242                 mask |= IXGBE_EIMS_GPI_SDP1;
2243         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2244                 mask |= IXGBE_EIMS_ECC;
2245                 mask |= IXGBE_EIMS_GPI_SDP1;
2246                 mask |= IXGBE_EIMS_GPI_SDP2;
2247                 if (adapter->num_vfs)
2248                         mask |= IXGBE_EIMS_MAILBOX;
2249         }
2250         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252                 mask |= IXGBE_EIMS_FLOW_DIR;
2253
2254         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2255         ixgbe_irq_enable_queues(adapter, ~0);
2256         IXGBE_WRITE_FLUSH(&adapter->hw);
2257
2258         if (adapter->num_vfs > 32) {
2259                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261         }
2262 }
2263
2264 /**
2265  * ixgbe_intr - legacy mode Interrupt Handler
2266  * @irq: interrupt number
2267  * @data: pointer to a network interface device structure
2268  **/
2269 static irqreturn_t ixgbe_intr(int irq, void *data)
2270 {
2271         struct net_device *netdev = data;
2272         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273         struct ixgbe_hw *hw = &adapter->hw;
2274         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2275         u32 eicr;
2276
2277         /*
2278          * Workaround for silicon errata.  Mask the interrupts
2279          * before the read of EICR.
2280          */
2281         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
2283         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284          * therefore no explict interrupt disable is necessary */
2285         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2286         if (!eicr) {
2287                 /* shared interrupt alert!
2288                  * make sure interrupts are enabled because the read will
2289                  * have disabled interrupts due to EIAM */
2290                 ixgbe_irq_enable(adapter);
2291                 return IRQ_NONE;        /* Not our interrupt */
2292         }
2293
2294         if (eicr & IXGBE_EICR_LSC)
2295                 ixgbe_check_lsc(adapter);
2296
2297         if (hw->mac.type == ixgbe_mac_82599EB)
2298                 ixgbe_check_sfp_event(adapter, eicr);
2299
2300         ixgbe_check_fan_failure(adapter, eicr);
2301         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303                 schedule_work(&adapter->check_overtemp_task);
2304
2305         if (napi_schedule_prep(&(q_vector->napi))) {
2306                 adapter->tx_ring[0]->total_packets = 0;
2307                 adapter->tx_ring[0]->total_bytes = 0;
2308                 adapter->rx_ring[0]->total_packets = 0;
2309                 adapter->rx_ring[0]->total_bytes = 0;
2310                 /* would disable interrupts here but EIAM disabled it */
2311                 __napi_schedule(&(q_vector->napi));
2312         }
2313
2314         return IRQ_HANDLED;
2315 }
2316
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318 {
2319         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321         for (i = 0; i < q_vectors; i++) {
2322                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2323                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325                 q_vector->rxr_count = 0;
2326                 q_vector->txr_count = 0;
2327         }
2328 }
2329
2330 /**
2331  * ixgbe_request_irq - initialize interrupts
2332  * @adapter: board private structure
2333  *
2334  * Attempts to configure interrupts using the best available
2335  * capabilities of the hardware and kernel.
2336  **/
2337 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2338 {
2339         struct net_device *netdev = adapter->netdev;
2340         int err;
2341
2342         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343                 err = ixgbe_request_msix_irqs(adapter);
2344         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2345                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2346                                   netdev->name, netdev);
2347         } else {
2348                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2349                                   netdev->name, netdev);
2350         }
2351
2352         if (err)
2353                 e_err(probe, "request_irq failed, Error %d\n", err);
2354
2355         return err;
2356 }
2357
2358 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359 {
2360         struct net_device *netdev = adapter->netdev;
2361
2362         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2363                 int i, q_vectors;
2364
2365                 q_vectors = adapter->num_msix_vectors;
2366
2367                 i = q_vectors - 1;
2368                 free_irq(adapter->msix_entries[i].vector, netdev);
2369
2370                 i--;
2371                 for (; i >= 0; i--) {
2372                         free_irq(adapter->msix_entries[i].vector,
2373                                  adapter->q_vector[i]);
2374                 }
2375
2376                 ixgbe_reset_q_vectors(adapter);
2377         } else {
2378                 free_irq(adapter->pdev->irq, netdev);
2379         }
2380 }
2381
2382 /**
2383  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384  * @adapter: board private structure
2385  **/
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387 {
2388         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390         } else {
2391                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2393                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2394                 if (adapter->num_vfs > 32)
2395                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2396         }
2397         IXGBE_WRITE_FLUSH(&adapter->hw);
2398         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399                 int i;
2400                 for (i = 0; i < adapter->num_msix_vectors; i++)
2401                         synchronize_irq(adapter->msix_entries[i].vector);
2402         } else {
2403                 synchronize_irq(adapter->pdev->irq);
2404         }
2405 }
2406
2407 /**
2408  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409  *
2410  **/
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412 {
2413         struct ixgbe_hw *hw = &adapter->hw;
2414
2415         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2416                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2417
2418         ixgbe_set_ivar(adapter, 0, 0, 0);
2419         ixgbe_set_ivar(adapter, 1, 0, 0);
2420
2421         map_vector_to_rxq(adapter, 0, 0);
2422         map_vector_to_txq(adapter, 0, 0);
2423
2424         e_info(hw, "Legacy interrupt IVAR setup done\n");
2425 }
2426
2427 /**
2428  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2429  * @adapter: board private structure
2430  *
2431  * Configure the Tx unit of the MAC after a reset.
2432  **/
2433 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2434 {
2435         u64 tdba;
2436         struct ixgbe_hw *hw = &adapter->hw;
2437         u32 i, j, tdlen, txctrl;
2438
2439         /* Setup the HW Tx Head and Tail descriptor pointers */
2440         for (i = 0; i < adapter->num_tx_queues; i++) {
2441                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2442                 j = ring->reg_idx;
2443                 tdba = ring->dma;
2444                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2445                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2446                                 (tdba & DMA_BIT_MASK(32)));
2447                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2448                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2449                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2450                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2451                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2452                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2453                 /*
2454                  * Disable Tx Head Writeback RO bit, since this hoses
2455                  * bookkeeping if things aren't delivered in order.
2456                  */
2457                 switch (hw->mac.type) {
2458                 case ixgbe_mac_82598EB:
2459                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2460                         break;
2461                 case ixgbe_mac_82599EB:
2462                 default:
2463                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2464                         break;
2465                 }
2466                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2467                 switch (hw->mac.type) {
2468                 case ixgbe_mac_82598EB:
2469                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2470                         break;
2471                 case ixgbe_mac_82599EB:
2472                 default:
2473                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2474                         break;
2475                 }
2476         }
2477
2478         if (hw->mac.type == ixgbe_mac_82599EB) {
2479                 u32 rttdcs;
2480                 u32 mask;
2481
2482                 /* disable the arbiter while setting MTQC */
2483                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2484                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2485                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2486
2487                 /* set transmit pool layout */
2488                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2489                 switch (adapter->flags & mask) {
2490
2491                 case (IXGBE_FLAG_SRIOV_ENABLED):
2492                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2493                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2494                         break;
2495
2496                 case (IXGBE_FLAG_DCB_ENABLED):
2497                         /* We enable 8 traffic classes, DCB only */
2498                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2499                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2500                         break;
2501
2502                 default:
2503                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2504                         break;
2505                 }
2506
2507                 /* re-eable the arbiter */
2508                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2509                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2510         }
2511 }
2512
2513 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2514
2515 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2516                                    struct ixgbe_ring *rx_ring)
2517 {
2518         u32 srrctl;
2519         int index;
2520         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2521
2522         index = rx_ring->reg_idx;
2523         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2524                 unsigned long mask;
2525                 mask = (unsigned long) feature[RING_F_RSS].mask;
2526                 index = index & mask;
2527         }
2528         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2529
2530         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2531         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2532
2533         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2534                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2535
2536         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2537 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2538                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2539 #else
2540                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2541 #endif
2542                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2543         } else {
2544                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2545                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2546                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2547         }
2548
2549         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2550 }
2551
2552 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2553 {
2554         u32 mrqc = 0;
2555         int mask;
2556
2557         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2558                 return mrqc;
2559
2560         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2561 #ifdef CONFIG_IXGBE_DCB
2562                                  | IXGBE_FLAG_DCB_ENABLED
2563 #endif
2564                                  | IXGBE_FLAG_SRIOV_ENABLED
2565                                 );
2566
2567         switch (mask) {
2568         case (IXGBE_FLAG_RSS_ENABLED):
2569                 mrqc = IXGBE_MRQC_RSSEN;
2570                 break;
2571         case (IXGBE_FLAG_SRIOV_ENABLED):
2572                 mrqc = IXGBE_MRQC_VMDQEN;
2573                 break;
2574 #ifdef CONFIG_IXGBE_DCB
2575         case (IXGBE_FLAG_DCB_ENABLED):
2576                 mrqc = IXGBE_MRQC_RT8TCEN;
2577                 break;
2578 #endif /* CONFIG_IXGBE_DCB */
2579         default:
2580                 break;
2581         }
2582
2583         return mrqc;
2584 }
2585
2586 /**
2587  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2588  * @adapter:    address of board private structure
2589  * @index:      index of ring to set
2590  **/
2591 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2592 {
2593         struct ixgbe_ring *rx_ring;
2594         struct ixgbe_hw *hw = &adapter->hw;
2595         int j;
2596         u32 rscctrl;
2597         int rx_buf_len;
2598
2599         rx_ring = adapter->rx_ring[index];
2600         j = rx_ring->reg_idx;
2601         rx_buf_len = rx_ring->rx_buf_len;
2602         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2603         rscctrl |= IXGBE_RSCCTL_RSCEN;
2604         /*
2605          * we must limit the number of descriptors so that the
2606          * total size of max desc * buf_len is not greater
2607          * than 65535
2608          */
2609         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2610 #if (MAX_SKB_FRAGS > 16)
2611                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2612 #elif (MAX_SKB_FRAGS > 8)
2613                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2614 #elif (MAX_SKB_FRAGS > 4)
2615                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2616 #else
2617                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2618 #endif
2619         } else {
2620                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2621                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2622                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2623                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2624                 else
2625                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2626         }
2627         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2628 }
2629
2630 /**
2631  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2632  * @adapter: board private structure
2633  *
2634  * Configure the Rx unit of the MAC after a reset.
2635  **/
2636 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2637 {
2638         u64 rdba;
2639         struct ixgbe_hw *hw = &adapter->hw;
2640         struct ixgbe_ring *rx_ring;
2641         struct net_device *netdev = adapter->netdev;
2642         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2643         int i, j;
2644         u32 rdlen, rxctrl, rxcsum;
2645         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2646                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2647                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2648         u32 fctrl, hlreg0;
2649         u32 reta = 0, mrqc = 0;
2650         u32 rdrxctl;
2651         int rx_buf_len;
2652
2653         /* Decide whether to use packet split mode or not */
2654         /* On by default */
2655         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2656
2657         /* Do not use packet split if we're in SR-IOV Mode */
2658         if (adapter->num_vfs)
2659                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2660
2661         /* Disable packet split due to 82599 erratum #45 */
2662         if (hw->mac.type == ixgbe_mac_82599EB)
2663                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2664
2665         /* Set the RX buffer length according to the mode */
2666         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2667                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2668                 if (hw->mac.type == ixgbe_mac_82599EB) {
2669                         /* PSRTYPE must be initialized in 82599 */
2670                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2671                                       IXGBE_PSRTYPE_UDPHDR |
2672                                       IXGBE_PSRTYPE_IPV4HDR |
2673                                       IXGBE_PSRTYPE_IPV6HDR |
2674                                       IXGBE_PSRTYPE_L2HDR;
2675                         IXGBE_WRITE_REG(hw,
2676                                         IXGBE_PSRTYPE(adapter->num_vfs),
2677                                         psrtype);
2678                 }
2679         } else {
2680                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2681                     (netdev->mtu <= ETH_DATA_LEN))
2682                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2683                 else
2684                         rx_buf_len = ALIGN(max_frame, 1024);
2685         }
2686
2687         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2688         fctrl |= IXGBE_FCTRL_BAM;
2689         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2690         fctrl |= IXGBE_FCTRL_PMCF;
2691         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2692
2693         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2694         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2695                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2696         else
2697                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2698 #ifdef IXGBE_FCOE
2699         if (netdev->features & NETIF_F_FCOE_MTU)
2700                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2701 #endif
2702         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2703
2704         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2705         /* disable receives while setting up the descriptors */
2706         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2707         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2708
2709         /*
2710          * Setup the HW Rx Head and Tail Descriptor Pointers and
2711          * the Base and Length of the Rx Descriptor Ring
2712          */
2713         for (i = 0; i < adapter->num_rx_queues; i++) {
2714                 rx_ring = adapter->rx_ring[i];
2715                 rdba = rx_ring->dma;
2716                 j = rx_ring->reg_idx;
2717                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2718                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2719                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2720                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2721                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2722                 rx_ring->head = IXGBE_RDH(j);
2723                 rx_ring->tail = IXGBE_RDT(j);
2724                 rx_ring->rx_buf_len = rx_buf_len;
2725
2726                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2727                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2728                 else
2729                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2730
2731 #ifdef IXGBE_FCOE
2732                 if (netdev->features & NETIF_F_FCOE_MTU) {
2733                         struct ixgbe_ring_feature *f;
2734                         f = &adapter->ring_feature[RING_F_FCOE];
2735                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2736                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2737                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2738                                         rx_ring->rx_buf_len =
2739                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2740                         }
2741                 }
2742
2743 #endif /* IXGBE_FCOE */
2744                 ixgbe_configure_srrctl(adapter, rx_ring);
2745         }
2746
2747         if (hw->mac.type == ixgbe_mac_82598EB) {
2748                 /*
2749                  * For VMDq support of different descriptor types or
2750                  * buffer sizes through the use of multiple SRRCTL
2751                  * registers, RDRXCTL.MVMEN must be set to 1
2752                  *
2753                  * also, the manual doesn't mention it clearly but DCA hints
2754                  * will only use queue 0's tags unless this bit is set.  Side
2755                  * effects of setting this bit are only that SRRCTL must be
2756                  * fully programmed [0..15]
2757                  */
2758                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2759                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2760                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2761         }
2762
2763         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2764                 u32 vt_reg_bits;
2765                 u32 reg_offset, vf_shift;
2766                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2767                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2768                         | IXGBE_VT_CTL_REPLEN;
2769                 vt_reg_bits |= (adapter->num_vfs <<
2770                                 IXGBE_VT_CTL_POOL_SHIFT);
2771                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2772                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2773
2774                 vf_shift = adapter->num_vfs % 32;
2775                 reg_offset = adapter->num_vfs / 32;
2776                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2777                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2778                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2779                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2780                 /* Enable only the PF's pool for Tx/Rx */
2781                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2782                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2783                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2784                 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2785         }
2786
2787         /* Program MRQC for the distribution of queues */
2788         mrqc = ixgbe_setup_mrqc(adapter);
2789
2790         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2791                 /* Fill out redirection table */
2792                 for (i = 0, j = 0; i < 128; i++, j++) {
2793                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2794                                 j = 0;
2795                         /* reta = 4-byte sliding window of
2796                          * 0x00..(indices-1)(indices-1)00..etc. */
2797                         reta = (reta << 8) | (j * 0x11);
2798                         if ((i & 3) == 3)
2799                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2800                 }
2801
2802                 /* Fill out hash function seeds */
2803                 for (i = 0; i < 10; i++)
2804                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2805
2806                 if (hw->mac.type == ixgbe_mac_82598EB)
2807                         mrqc |= IXGBE_MRQC_RSSEN;
2808                     /* Perform hash on these packet types */
2809                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2810                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2811                       | IXGBE_MRQC_RSS_FIELD_IPV6
2812                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2813         }
2814         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2815
2816         if (adapter->num_vfs) {
2817                 u32 reg;
2818
2819                 /* Map PF MAC address in RAR Entry 0 to first pool
2820                  * following VFs */
2821                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2822
2823                 /* Set up VF register offsets for selected VT Mode, i.e.
2824                  * 64 VFs for SR-IOV */
2825                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2826                 reg |= IXGBE_GCR_EXT_SRIOV;
2827                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2828         }
2829
2830         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2831
2832         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2833             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2834                 /* Disable indicating checksum in descriptor, enables
2835                  * RSS hash */
2836                 rxcsum |= IXGBE_RXCSUM_PCSD;
2837         }
2838         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2839                 /* Enable IPv4 payload checksum for UDP fragments
2840                  * if PCSD is not set */
2841                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2842         }
2843
2844         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2845
2846         if (hw->mac.type == ixgbe_mac_82599EB) {
2847                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2848                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2849                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2850                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2851         }
2852
2853         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2854                 /* Enable 82599 HW-RSC */
2855                 for (i = 0; i < adapter->num_rx_queues; i++)
2856                         ixgbe_configure_rscctl(adapter, i);
2857
2858                 /* Disable RSC for ACK packets */
2859                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2860                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2861         }
2862 }
2863
2864 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2865 {
2866         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2867         struct ixgbe_hw *hw = &adapter->hw;
2868         int pool_ndx = adapter->num_vfs;
2869
2870         /* add VID to filter table */
2871         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2872 }
2873
2874 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2875 {
2876         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2877         struct ixgbe_hw *hw = &adapter->hw;
2878         int pool_ndx = adapter->num_vfs;
2879
2880         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2881                 ixgbe_irq_disable(adapter);
2882
2883         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2884
2885         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2886                 ixgbe_irq_enable(adapter);
2887
2888         /* remove VID from filter table */
2889         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2890 }
2891
2892 /**
2893  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2894  * @adapter: driver data
2895  */
2896 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2897 {
2898         struct ixgbe_hw *hw = &adapter->hw;
2899         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2900         int i, j;
2901
2902         switch (hw->mac.type) {
2903         case ixgbe_mac_82598EB:
2904                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2905 #ifdef CONFIG_IXGBE_DCB
2906                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2907                         vlnctrl &= ~IXGBE_VLNCTRL_VME;
2908 #endif
2909                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2910                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2911                 break;
2912         case ixgbe_mac_82599EB:
2913                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2914                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2915                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2916 #ifdef CONFIG_IXGBE_DCB
2917                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2918                         break;
2919 #endif
2920                 for (i = 0; i < adapter->num_rx_queues; i++) {
2921                         j = adapter->rx_ring[i]->reg_idx;
2922                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2923                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2924                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2925                 }
2926                 break;
2927         default:
2928                 break;
2929         }
2930 }
2931
2932 /**
2933  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2934  * @adapter: driver data
2935  */
2936 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2937 {
2938         struct ixgbe_hw *hw = &adapter->hw;
2939         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2940         int i, j;
2941
2942         switch (hw->mac.type) {
2943         case ixgbe_mac_82598EB:
2944                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2945                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2946                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2947                 break;
2948         case ixgbe_mac_82599EB:
2949                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2950                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2951                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2952                 for (i = 0; i < adapter->num_rx_queues; i++) {
2953                         j = adapter->rx_ring[i]->reg_idx;
2954                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2955                         vlnctrl |= IXGBE_RXDCTL_VME;
2956                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2957                 }
2958                 break;
2959         default:
2960                 break;
2961         }
2962 }
2963
2964 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2965                                    struct vlan_group *grp)
2966 {
2967         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2968
2969         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2970                 ixgbe_irq_disable(adapter);
2971         adapter->vlgrp = grp;
2972
2973         /*
2974          * For a DCB driver, always enable VLAN tag stripping so we can
2975          * still receive traffic from a DCB-enabled host even if we're
2976          * not in DCB mode.
2977          */
2978         ixgbe_vlan_filter_enable(adapter);
2979
2980         ixgbe_vlan_rx_add_vid(netdev, 0);
2981
2982         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2983                 ixgbe_irq_enable(adapter);
2984 }
2985
2986 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2987 {
2988         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2989
2990         if (adapter->vlgrp) {
2991                 u16 vid;
2992                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2993                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2994                                 continue;
2995                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2996                 }
2997         }
2998 }
2999
3000 /**
3001  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3002  * @netdev: network interface device structure
3003  *
3004  * Writes unicast address list to the RAR table.
3005  * Returns: -ENOMEM on failure/insufficient address space
3006  *                0 on no addresses written
3007  *                X on writing X addresses to the RAR table
3008  **/
3009 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3010 {
3011         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3012         struct ixgbe_hw *hw = &adapter->hw;
3013         unsigned int vfn = adapter->num_vfs;
3014         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3015         int count = 0;
3016
3017         /* return ENOMEM indicating insufficient memory for addresses */
3018         if (netdev_uc_count(netdev) > rar_entries)
3019                 return -ENOMEM;
3020
3021         if (!netdev_uc_empty(netdev) && rar_entries) {
3022                 struct netdev_hw_addr *ha;
3023                 /* return error if we do not support writing to RAR table */
3024                 if (!hw->mac.ops.set_rar)
3025                         return -ENOMEM;
3026
3027                 netdev_for_each_uc_addr(ha, netdev) {
3028                         if (!rar_entries)
3029                                 break;
3030                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3031                                             vfn, IXGBE_RAH_AV);
3032                         count++;
3033                 }
3034         }
3035         /* write the addresses in reverse order to avoid write combining */
3036         for (; rar_entries > 0 ; rar_entries--)
3037                 hw->mac.ops.clear_rar(hw, rar_entries);
3038
3039         return count;
3040 }
3041
3042 /**
3043  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3044  * @netdev: network interface device structure
3045  *
3046  * The set_rx_method entry point is called whenever the unicast/multicast
3047  * address list or the network interface flags are updated.  This routine is
3048  * responsible for configuring the hardware for proper unicast, multicast and
3049  * promiscuous mode.
3050  **/
3051 void ixgbe_set_rx_mode(struct net_device *netdev)
3052 {
3053         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3054         struct ixgbe_hw *hw = &adapter->hw;
3055         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3056         int count;
3057
3058         /* Check for Promiscuous and All Multicast modes */
3059
3060         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3061
3062         /* clear the bits we are changing the status of */
3063         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3064
3065         if (netdev->flags & IFF_PROMISC) {
3066                 hw->addr_ctrl.user_set_promisc = true;
3067                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3068                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3069                 /* don't hardware filter vlans in promisc mode */
3070                 ixgbe_vlan_filter_disable(adapter);
3071         } else {
3072                 if (netdev->flags & IFF_ALLMULTI) {
3073                         fctrl |= IXGBE_FCTRL_MPE;
3074                         vmolr |= IXGBE_VMOLR_MPE;
3075                 } else {
3076                         /*
3077                          * Write addresses to the MTA, if the attempt fails
3078                          * then we should just turn on promiscous mode so
3079                          * that we can at least receive multicast traffic
3080                          */
3081                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3082                         vmolr |= IXGBE_VMOLR_ROMPE;
3083                 }
3084                 ixgbe_vlan_filter_enable(adapter);
3085                 hw->addr_ctrl.user_set_promisc = false;
3086                 /*
3087                  * Write addresses to available RAR registers, if there is not
3088                  * sufficient space to store all the addresses then enable
3089                  * unicast promiscous mode
3090                  */
3091                 count = ixgbe_write_uc_addr_list(netdev);
3092                 if (count < 0) {
3093                         fctrl |= IXGBE_FCTRL_UPE;
3094                         vmolr |= IXGBE_VMOLR_ROPE;
3095                 }
3096         }
3097
3098         if (adapter->num_vfs) {
3099                 ixgbe_restore_vf_multicasts(adapter);
3100                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3101                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3102                            IXGBE_VMOLR_ROPE);
3103                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3104         }
3105
3106         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3107 }
3108
3109 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3110 {
3111         int q_idx;
3112         struct ixgbe_q_vector *q_vector;
3113         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3114
3115         /* legacy and MSI only use one vector */
3116         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3117                 q_vectors = 1;
3118
3119         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3120                 struct napi_struct *napi;
3121                 q_vector = adapter->q_vector[q_idx];
3122                 napi = &q_vector->napi;
3123                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3124                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3125                                 if (q_vector->txr_count == 1)
3126                                         napi->poll = &ixgbe_clean_txonly;
3127                                 else if (q_vector->rxr_count == 1)
3128                                         napi->poll = &ixgbe_clean_rxonly;
3129                         }
3130                 }
3131
3132                 napi_enable(napi);
3133         }
3134 }
3135
3136 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3137 {
3138         int q_idx;
3139         struct ixgbe_q_vector *q_vector;
3140         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3141
3142         /* legacy and MSI only use one vector */
3143         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3144                 q_vectors = 1;
3145
3146         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3147                 q_vector = adapter->q_vector[q_idx];
3148                 napi_disable(&q_vector->napi);
3149         }
3150 }
3151
3152 #ifdef CONFIG_IXGBE_DCB
3153 /*
3154  * ixgbe_configure_dcb - Configure DCB hardware
3155  * @adapter: ixgbe adapter struct
3156  *
3157  * This is called by the driver on open to configure the DCB hardware.
3158  * This is also called by the gennetlink interface when reconfiguring
3159  * the DCB state.
3160  */
3161 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3162 {
3163         struct ixgbe_hw *hw = &adapter->hw;
3164         u32 txdctl;
3165         int i, j;
3166
3167         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3168         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3169         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3170
3171         /* reconfigure the hardware */
3172         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3173
3174         for (i = 0; i < adapter->num_tx_queues; i++) {
3175                 j = adapter->tx_ring[i]->reg_idx;
3176                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3177                 /* PThresh workaround for Tx hang with DFP enabled. */
3178                 txdctl |= 32;
3179                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3180         }
3181         /* Enable VLAN tag insert/strip */
3182         ixgbe_vlan_filter_enable(adapter);
3183
3184         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3185 }
3186
3187 #endif
3188 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3189 {
3190         struct net_device *netdev = adapter->netdev;
3191         struct ixgbe_hw *hw = &adapter->hw;
3192         int i;
3193
3194         ixgbe_set_rx_mode(netdev);
3195
3196         ixgbe_restore_vlan(adapter);
3197 #ifdef CONFIG_IXGBE_DCB
3198         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3199                 if (hw->mac.type == ixgbe_mac_82598EB)
3200                         netif_set_gso_max_size(netdev, 32768);
3201                 else
3202                         netif_set_gso_max_size(netdev, 65536);
3203                 ixgbe_configure_dcb(adapter);
3204         } else {
3205                 netif_set_gso_max_size(netdev, 65536);
3206         }
3207 #else
3208         netif_set_gso_max_size(netdev, 65536);
3209 #endif
3210
3211 #ifdef IXGBE_FCOE
3212         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3213                 ixgbe_configure_fcoe(adapter);
3214
3215 #endif /* IXGBE_FCOE */
3216         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3217                 for (i = 0; i < adapter->num_tx_queues; i++)
3218                         adapter->tx_ring[i]->atr_sample_rate =
3219                                                        adapter->atr_sample_rate;
3220                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3221         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3222                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3223         }
3224
3225         ixgbe_configure_tx(adapter);
3226         ixgbe_configure_rx(adapter);
3227         for (i = 0; i < adapter->num_rx_queues; i++)
3228                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3229                                        (adapter->rx_ring[i]->count - 1));
3230 }
3231
3232 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3233 {
3234         switch (hw->phy.type) {
3235         case ixgbe_phy_sfp_avago:
3236         case ixgbe_phy_sfp_ftl:
3237         case ixgbe_phy_sfp_intel:
3238         case ixgbe_phy_sfp_unknown:
3239         case ixgbe_phy_sfp_passive_tyco:
3240         case ixgbe_phy_sfp_passive_unknown:
3241         case ixgbe_phy_sfp_active_unknown:
3242         case ixgbe_phy_sfp_ftl_active:
3243                 return true;
3244         default:
3245                 return false;
3246         }
3247 }
3248
3249 /**
3250  * ixgbe_sfp_link_config - set up SFP+ link
3251  * @adapter: pointer to private adapter struct
3252  **/
3253 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3254 {
3255         struct ixgbe_hw *hw = &adapter->hw;
3256
3257                 if (hw->phy.multispeed_fiber) {
3258                         /*
3259                          * In multispeed fiber setups, the device may not have
3260                          * had a physical connection when the driver loaded.
3261                          * If that's the case, the initial link configuration
3262                          * couldn't get the MAC into 10G or 1G mode, so we'll
3263                          * never have a link status change interrupt fire.
3264                          * We need to try and force an autonegotiation
3265                          * session, then bring up link.
3266                          */
3267                         hw->mac.ops.setup_sfp(hw);
3268                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3269                                 schedule_work(&adapter->multispeed_fiber_task);
3270                 } else {
3271                         /*
3272                          * Direct Attach Cu and non-multispeed fiber modules
3273                          * still need to be configured properly prior to
3274                          * attempting link.
3275                          */
3276                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3277                                 schedule_work(&adapter->sfp_config_module_task);
3278                 }
3279 }
3280
3281 /**
3282  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3283  * @hw: pointer to private hardware struct
3284  *
3285  * Returns 0 on success, negative on failure
3286  **/
3287 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3288 {
3289         u32 autoneg;
3290         bool negotiation, link_up = false;
3291         u32 ret = IXGBE_ERR_LINK_SETUP;
3292
3293         if (hw->mac.ops.check_link)
3294                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3295
3296         if (ret)
3297                 goto link_cfg_out;
3298
3299         if (hw->mac.ops.get_link_capabilities)
3300                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3301         if (ret)
3302                 goto link_cfg_out;
3303
3304         if (hw->mac.ops.setup_link)
3305                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3306 link_cfg_out:
3307         return ret;
3308 }
3309
3310 #define IXGBE_MAX_RX_DESC_POLL 10
3311 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3312                                               int rxr)
3313 {
3314         int j = adapter->rx_ring[rxr]->reg_idx;
3315         int k;
3316
3317         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3318                 if (IXGBE_READ_REG(&adapter->hw,
3319                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3320                         break;
3321                 else
3322                         msleep(1);
3323         }
3324         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3325                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3326                       "the polling period\n", rxr);
3327         }
3328         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3329                               (adapter->rx_ring[rxr]->count - 1));
3330 }
3331
3332 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3333 {
3334         struct net_device *netdev = adapter->netdev;
3335         struct ixgbe_hw *hw = &adapter->hw;
3336         int i, j = 0;
3337         int num_rx_rings = adapter->num_rx_queues;
3338         int err;
3339         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3340         u32 txdctl, rxdctl, mhadd;
3341         u32 dmatxctl;
3342         u32 gpie;
3343         u32 ctrl_ext;
3344
3345         ixgbe_get_hw_control(adapter);
3346
3347         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3348             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3349                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3350                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3351                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3352                 } else {
3353                         /* MSI only */
3354                         gpie = 0;
3355                 }
3356                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3357                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3358                         gpie |= IXGBE_GPIE_VTMODE_64;
3359                 }
3360                 /* XXX: to interrupt immediately for EICS writes, enable this */
3361                 /* gpie |= IXGBE_GPIE_EIMEN; */
3362                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3363         }
3364
3365         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3366                 /*
3367                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3368                  * this saves a register write for every interrupt
3369                  */
3370                 switch (hw->mac.type) {
3371                 case ixgbe_mac_82598EB:
3372                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3373                         break;
3374                 default:
3375                 case ixgbe_mac_82599EB:
3376                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3377                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3378                         break;
3379                 }
3380         } else {
3381                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3382                  * specifically only auto mask tx and rx interrupts */
3383                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3384         }
3385
3386         /* Enable Thermal over heat sensor interrupt */
3387         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3388                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3389                 gpie |= IXGBE_SDP0_GPIEN;
3390                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3391         }
3392
3393         /* Enable fan failure interrupt if media type is copper */
3394         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3395                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3396                 gpie |= IXGBE_SDP1_GPIEN;
3397                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3398         }
3399
3400         if (hw->mac.type == ixgbe_mac_82599EB) {
3401                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3402                 gpie |= IXGBE_SDP1_GPIEN;
3403                 gpie |= IXGBE_SDP2_GPIEN;
3404                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3405         }
3406
3407 #ifdef IXGBE_FCOE
3408         /* adjust max frame to be able to do baby jumbo for FCoE */
3409         if ((netdev->features & NETIF_F_FCOE_MTU) &&
3410             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3411                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3412
3413 #endif /* IXGBE_FCOE */
3414         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3415         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3416                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3417                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3418
3419                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3420         }
3421
3422         for (i = 0; i < adapter->num_tx_queues; i++) {
3423                 j = adapter->tx_ring[i]->reg_idx;
3424                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3425                 if (adapter->rx_itr_setting == 0) {
3426                         /* cannot set wthresh when itr==0 */
3427                         txdctl &= ~0x007F0000;
3428                 } else {
3429                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3430                         txdctl |= (8 << 16);
3431                 }
3432                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3433         }
3434
3435         if (hw->mac.type == ixgbe_mac_82599EB) {
3436                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3437                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3438                 dmatxctl |= IXGBE_DMATXCTL_TE;
3439                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3440         }
3441         for (i = 0; i < adapter->num_tx_queues; i++) {
3442                 j = adapter->tx_ring[i]->reg_idx;
3443                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3444                 txdctl |= IXGBE_TXDCTL_ENABLE;
3445                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3446                 if (hw->mac.type == ixgbe_mac_82599EB) {
3447                         int wait_loop = 10;
3448                         /* poll for Tx Enable ready */
3449                         do {
3450                                 msleep(1);
3451                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3452                         } while (--wait_loop &&
3453                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3454                         if (!wait_loop)
3455                                 e_err(drv, "Could not enable Tx Queue %d\n", j);
3456                 }
3457         }
3458
3459         for (i = 0; i < num_rx_rings; i++) {
3460                 j = adapter->rx_ring[i]->reg_idx;
3461                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3462                 /* enable PTHRESH=32 descriptors (half the internal cache)
3463                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3464                  * this also removes a pesky rx_no_buffer_count increment */
3465                 rxdctl |= 0x0020;
3466                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3467                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3468                 if (hw->mac.type == ixgbe_mac_82599EB)
3469                         ixgbe_rx_desc_queue_enable(adapter, i);
3470         }
3471         /* enable all receives */
3472         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3473         if (hw->mac.type == ixgbe_mac_82598EB)
3474                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3475         else
3476                 rxdctl |= IXGBE_RXCTRL_RXEN;
3477         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3478
3479         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3480                 ixgbe_configure_msix(adapter);
3481         else
3482                 ixgbe_configure_msi_and_legacy(adapter);
3483
3484         /* enable the optics */
3485         if (hw->phy.multispeed_fiber)
3486                 hw->mac.ops.enable_tx_laser(hw);
3487
3488         clear_bit(__IXGBE_DOWN, &adapter->state);
3489         ixgbe_napi_enable_all(adapter);
3490
3491         /* clear any pending interrupts, may auto mask */
3492         IXGBE_READ_REG(hw, IXGBE_EICR);
3493
3494         ixgbe_irq_enable(adapter);
3495
3496         /*
3497          * If this adapter has a fan, check to see if we had a failure
3498          * before we enabled the interrupt.
3499          */
3500         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3501                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3502                 if (esdp & IXGBE_ESDP_SDP1)
3503                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3504         }
3505
3506         /*
3507          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3508          * arrived before interrupts were enabled but after probe.  Such
3509          * devices wouldn't have their type identified yet. We need to
3510          * kick off the SFP+ module setup first, then try to bring up link.
3511          * If we're not hot-pluggable SFP+, we just need to configure link
3512          * and bring it up.
3513          */
3514         if (hw->phy.type == ixgbe_phy_unknown) {
3515                 err = hw->phy.ops.identify(hw);
3516                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3517                         /*
3518                          * Take the device down and schedule the sfp tasklet
3519                          * which will unregister_netdev and log it.
3520                          */
3521                         ixgbe_down(adapter);
3522                         schedule_work(&adapter->sfp_config_module_task);
3523                         return err;
3524                 }
3525         }
3526
3527         if (ixgbe_is_sfp(hw)) {
3528                 ixgbe_sfp_link_config(adapter);
3529         } else {
3530                 err = ixgbe_non_sfp_link_config(hw);
3531                 if (err)
3532                         e_err(probe, "link_config FAILED %d\n", err);
3533         }
3534
3535         for (i = 0; i < adapter->num_tx_queues; i++)
3536                 set_bit(__IXGBE_FDIR_INIT_DONE,
3537                         &(adapter->tx_ring[i]->reinit_state));
3538
3539         /* enable transmits */
3540         netif_tx_start_all_queues(netdev);
3541
3542         /* bring the link up in the watchdog, this could race with our first
3543          * link up interrupt but shouldn't be a problem */
3544         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3545         adapter->link_check_timeout = jiffies;
3546         mod_timer(&adapter->watchdog_timer, jiffies);
3547
3548         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3549         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3550         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3551         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3552
3553         return 0;
3554 }
3555
3556 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3557 {
3558         WARN_ON(in_interrupt());
3559         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3560                 msleep(1);
3561         ixgbe_down(adapter);
3562         /*
3563          * If SR-IOV enabled then wait a bit before bringing the adapter
3564          * back up to give the VFs time to respond to the reset.  The
3565          * two second wait is based upon the watchdog timer cycle in
3566          * the VF driver.
3567          */
3568         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3569                 msleep(2000);
3570         ixgbe_up(adapter);
3571         clear_bit(__IXGBE_RESETTING, &adapter->state);
3572 }
3573
3574 int ixgbe_up(struct ixgbe_adapter *adapter)
3575 {
3576         /* hardware has been reset, we need to reload some things */
3577         ixgbe_configure(adapter);
3578
3579         return ixgbe_up_complete(adapter);
3580 }
3581
3582 void ixgbe_reset(struct ixgbe_adapter *adapter)
3583 {
3584         struct ixgbe_hw *hw = &adapter->hw;
3585         int err;
3586
3587         err = hw->mac.ops.init_hw(hw);
3588         switch (err) {
3589         case 0:
3590         case IXGBE_ERR_SFP_NOT_PRESENT:
3591                 break;
3592         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3593                 e_dev_err("master disable timed out\n");
3594                 break;
3595         case IXGBE_ERR_EEPROM_VERSION:
3596                 /* We are running on a pre-production device, log a warning */
3597                 e_dev_warn("This device is a pre-production adapter/LOM. "
3598                            "Please be aware there may be issuesassociated with "
3599                            "your hardware.  If you are experiencing problems "
3600                            "please contact your Intel or hardware "
3601                            "representative who provided you with this "
3602                            "hardware.\n");
3603                 break;
3604         default:
3605                 e_dev_err("Hardware Error: %d\n", err);
3606         }
3607
3608         /* reprogram the RAR[0] in case user changed it. */
3609         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3610                             IXGBE_RAH_AV);
3611 }
3612
3613 /**
3614  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3615  * @adapter: board private structure
3616  * @rx_ring: ring to free buffers from
3617  **/
3618 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3619                                 struct ixgbe_ring *rx_ring)
3620 {
3621         struct pci_dev *pdev = adapter->pdev;
3622         unsigned long size;
3623         unsigned int i;
3624
3625         /* Free all the Rx ring sk_buffs */
3626
3627         for (i = 0; i < rx_ring->count; i++) {
3628                 struct ixgbe_rx_buffer *rx_buffer_info;
3629
3630                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3631                 if (rx_buffer_info->dma) {
3632                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3633                                          rx_ring->rx_buf_len,
3634                                          DMA_FROM_DEVICE);
3635                         rx_buffer_info->dma = 0;
3636                 }
3637                 if (rx_buffer_info->skb) {
3638                         struct sk_buff *skb = rx_buffer_info->skb;
3639                         rx_buffer_info->skb = NULL;
3640                         do {
3641                                 struct sk_buff *this = skb;
3642                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3643                                         dma_unmap_single(&pdev->dev,
3644                                                          IXGBE_RSC_CB(this)->dma,
3645                                                          rx_ring->rx_buf_len,
3646                                                          DMA_FROM_DEVICE);
3647                                         IXGBE_RSC_CB(this)->dma = 0;
3648                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3649                                 }
3650                                 skb = skb->prev;
3651                                 dev_kfree_skb(this);
3652                         } while (skb);
3653                 }
3654                 if (!rx_buffer_info->page)
3655                         continue;
3656                 if (rx_buffer_info->page_dma) {
3657                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3658                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3659                         rx_buffer_info->page_dma = 0;
3660                 }
3661                 put_page(rx_buffer_info->page);
3662                 rx_buffer_info->page = NULL;
3663                 rx_buffer_info->page_offset = 0;
3664         }
3665
3666         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3667         memset(rx_ring->rx_buffer_info, 0, size);
3668
3669         /* Zero out the descriptor ring */
3670         memset(rx_ring->desc, 0, rx_ring->size);
3671
3672         rx_ring->next_to_clean = 0;
3673         rx_ring->next_to_use = 0;
3674
3675         if (rx_ring->head)
3676                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3677         if (rx_ring->tail)
3678                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3679 }
3680
3681 /**
3682  * ixgbe_clean_tx_ring - Free Tx Buffers
3683  * @adapter: board private structure
3684  * @tx_ring: ring to be cleaned
3685  **/
3686 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3687                                 struct ixgbe_ring *tx_ring)
3688 {
3689         struct ixgbe_tx_buffer *tx_buffer_info;
3690         unsigned long size;
3691         unsigned int i;
3692
3693         /* Free all the Tx ring sk_buffs */
3694
3695         for (i = 0; i < tx_ring->count; i++) {
3696                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3697                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3698         }
3699
3700         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3701         memset(tx_ring->tx_buffer_info, 0, size);
3702
3703         /* Zero out the descriptor ring */
3704         memset(tx_ring->desc, 0, tx_ring->size);
3705
3706         tx_ring->next_to_use = 0;
3707         tx_ring->next_to_clean = 0;
3708
3709         if (tx_ring->head)
3710                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3711         if (tx_ring->tail)
3712                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3713 }
3714
3715 /**
3716  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3717  * @adapter: board private structure
3718  **/
3719 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3720 {
3721         int i;
3722
3723         for (i = 0; i < adapter->num_rx_queues; i++)
3724                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3725 }
3726
3727 /**
3728  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3729  * @adapter: board private structure
3730  **/
3731 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3732 {
3733         int i;
3734
3735         for (i = 0; i < adapter->num_tx_queues; i++)
3736                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3737 }
3738
3739 void ixgbe_down(struct ixgbe_adapter *adapter)
3740 {
3741         struct net_device *netdev = adapter->netdev;
3742         struct ixgbe_hw *hw = &adapter->hw;
3743         u32 rxctrl;
3744         u32 txdctl;
3745         int i, j;
3746
3747         /* signal that we are down to the interrupt handler */
3748         set_bit(__IXGBE_DOWN, &adapter->state);
3749
3750         /* disable receive for all VFs and wait one second */
3751         if (adapter->num_vfs) {
3752                 /* ping all the active vfs to let them know we are going down */
3753                 ixgbe_ping_all_vfs(adapter);
3754
3755                 /* Disable all VFTE/VFRE TX/RX */
3756                 ixgbe_disable_tx_rx(adapter);
3757
3758                 /* Mark all the VFs as inactive */
3759                 for (i = 0 ; i < adapter->num_vfs; i++)
3760                         adapter->vfinfo[i].clear_to_send = 0;
3761         }
3762
3763         /* disable receives */
3764         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3765         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3766
3767         IXGBE_WRITE_FLUSH(hw);
3768         msleep(10);
3769
3770         netif_tx_stop_all_queues(netdev);
3771
3772         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3773         del_timer_sync(&adapter->sfp_timer);
3774         del_timer_sync(&adapter->watchdog_timer);
3775         cancel_work_sync(&adapter->watchdog_task);
3776
3777         netif_carrier_off(netdev);
3778         netif_tx_disable(netdev);
3779
3780         ixgbe_irq_disable(adapter);
3781
3782         ixgbe_napi_disable_all(adapter);
3783
3784         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3785             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3786                 cancel_work_sync(&adapter->fdir_reinit_task);
3787
3788         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3789                 cancel_work_sync(&adapter->check_overtemp_task);
3790
3791         /* disable transmits in the hardware now that interrupts are off */
3792         for (i = 0; i < adapter->num_tx_queues; i++) {
3793                 j = adapter->tx_ring[i]->reg_idx;
3794                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3795                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3796                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3797         }
3798         /* Disable the Tx DMA engine on 82599 */
3799         if (hw->mac.type == ixgbe_mac_82599EB)
3800                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3801                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3802                                  ~IXGBE_DMATXCTL_TE));
3803
3804         /* power down the optics */
3805         if (hw->phy.multispeed_fiber)
3806                 hw->mac.ops.disable_tx_laser(hw);
3807
3808         /* clear n-tuple filters that are cached */
3809         ethtool_ntuple_flush(netdev);
3810
3811         if (!pci_channel_offline(adapter->pdev))
3812                 ixgbe_reset(adapter);
3813         ixgbe_clean_all_tx_rings(adapter);
3814         ixgbe_clean_all_rx_rings(adapter);
3815
3816 #ifdef CONFIG_IXGBE_DCA
3817         /* since we reset the hardware DCA settings were cleared */
3818         ixgbe_setup_dca(adapter);
3819 #endif
3820 }
3821
3822 /**
3823  * ixgbe_poll - NAPI Rx polling callback
3824  * @napi: structure for representing this polling device
3825  * @budget: how many packets driver is allowed to clean
3826  *
3827  * This function is used for legacy and MSI, NAPI mode
3828  **/
3829 static int ixgbe_poll(struct napi_struct *napi, int budget)
3830 {
3831         struct ixgbe_q_vector *q_vector =
3832                                 container_of(napi, struct ixgbe_q_vector, napi);
3833         struct ixgbe_adapter *adapter = q_vector->adapter;
3834         int tx_clean_complete, work_done = 0;
3835
3836 #ifdef CONFIG_IXGBE_DCA
3837         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3838                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3839                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3840         }
3841 #endif
3842
3843         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3844         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3845
3846         if (!tx_clean_complete)
3847                 work_done = budget;
3848
3849         /* If budget not fully consumed, exit the polling mode */
3850         if (work_done < budget) {
3851                 napi_complete(napi);
3852                 if (adapter->rx_itr_setting & 1)
3853                         ixgbe_set_itr(adapter);
3854                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3855                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3856         }
3857         return work_done;
3858 }
3859
3860 /**
3861  * ixgbe_tx_timeout - Respond to a Tx Hang
3862  * @netdev: network interface device structure
3863  **/
3864 static void ixgbe_tx_timeout(struct net_device *netdev)
3865 {
3866         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3867
3868         /* Do the reset outside of interrupt context */
3869         schedule_work(&adapter->reset_task);
3870 }
3871
3872 static void ixgbe_reset_task(struct work_struct *work)
3873 {
3874         struct ixgbe_adapter *adapter;
3875         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3876
3877         /* If we're already down or resetting, just bail */
3878         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3879             test_bit(__IXGBE_RESETTING, &adapter->state))
3880                 return;
3881
3882         adapter->tx_timeout_count++;
3883
3884         ixgbe_dump(adapter);
3885         netdev_err(adapter->netdev, "Reset adapter\n");
3886         ixgbe_reinit_locked(adapter);
3887 }
3888
3889 #ifdef CONFIG_IXGBE_DCB
3890 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3891 {
3892         bool ret = false;
3893         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3894
3895         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3896                 return ret;
3897
3898         f->mask = 0x7 << 3;
3899         adapter->num_rx_queues = f->indices;
3900         adapter->num_tx_queues = f->indices;
3901         ret = true;
3902
3903         return ret;
3904 }
3905 #endif
3906
3907 /**
3908  * ixgbe_set_rss_queues: Allocate queues for RSS
3909  * @adapter: board private structure to initialize
3910  *
3911  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3912  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3913  *
3914  **/
3915 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3916 {
3917         bool ret = false;
3918         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3919
3920         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3921                 f->mask = 0xF;
3922                 adapter->num_rx_queues = f->indices;
3923                 adapter->num_tx_queues = f->indices;
3924                 ret = true;
3925         } else {
3926                 ret = false;
3927         }
3928
3929         return ret;
3930 }
3931
3932 /**
3933  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3934  * @adapter: board private structure to initialize
3935  *
3936  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3937  * to the original CPU that initiated the Tx session.  This runs in addition
3938  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3939  * Rx load across CPUs using RSS.
3940  *
3941  **/
3942 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3943 {
3944         bool ret = false;
3945         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3946
3947         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3948         f_fdir->mask = 0;
3949
3950         /* Flow Director must have RSS enabled */
3951         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3952             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3953              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3954                 adapter->num_tx_queues = f_fdir->indices;
3955                 adapter->num_rx_queues = f_fdir->indices;
3956                 ret = true;
3957         } else {
3958                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3959                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3960         }
3961         return ret;
3962 }
3963
3964 #ifdef IXGBE_FCOE
3965 /**
3966  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3967  * @adapter: board private structure to initialize
3968  *
3969  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3970  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3971  * rx queues out of the max number of rx queues, instead, it is used as the
3972  * index of the first rx queue used by FCoE.
3973  *
3974  **/
3975 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3976 {
3977         bool ret = false;
3978         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3979
3980         f->indices = min((int)num_online_cpus(), f->indices);
3981         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3982                 adapter->num_rx_queues = 1;
3983                 adapter->num_tx_queues = 1;
3984 #ifdef CONFIG_IXGBE_DCB
3985                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3986                         e_info(probe, "FCoE enabled with DCB\n");
3987                         ixgbe_set_dcb_queues(adapter);
3988                 }
3989 #endif
3990                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3991                         e_info(probe, "FCoE enabled with RSS\n");
3992                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3993                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3994                                 ixgbe_set_fdir_queues(adapter);
3995                         else
3996                                 ixgbe_set_rss_queues(adapter);
3997                 }
3998                 /* adding FCoE rx rings to the end */
3999                 f->mask = adapter->num_rx_queues;
4000                 adapter->num_rx_queues += f->indices;
4001                 adapter->num_tx_queues += f->indices;
4002
4003                 ret = true;
4004         }
4005
4006         return ret;
4007 }
4008
4009 #endif /* IXGBE_FCOE */
4010 /**
4011  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4012  * @adapter: board private structure to initialize
4013  *
4014  * IOV doesn't actually use anything, so just NAK the
4015  * request for now and let the other queue routines
4016  * figure out what to do.
4017  */
4018 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4019 {
4020         return false;
4021 }
4022
4023 /*
4024  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4025  * @adapter: board private structure to initialize
4026  *
4027  * This is the top level queue allocation routine.  The order here is very
4028  * important, starting with the "most" number of features turned on at once,
4029  * and ending with the smallest set of features.  This way large combinations
4030  * can be allocated if they're turned on, and smaller combinations are the
4031  * fallthrough conditions.
4032  *
4033  **/
4034 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4035 {
4036         /* Start with base case */
4037         adapter->num_rx_queues = 1;
4038         adapter->num_tx_queues = 1;
4039         adapter->num_rx_pools = adapter->num_rx_queues;
4040         adapter->num_rx_queues_per_pool = 1;
4041
4042         if (ixgbe_set_sriov_queues(adapter))
4043                 return;
4044
4045 #ifdef IXGBE_FCOE
4046         if (ixgbe_set_fcoe_queues(adapter))
4047                 goto done;
4048
4049 #endif /* IXGBE_FCOE */
4050 #ifdef CONFIG_IXGBE_DCB
4051         if (ixgbe_set_dcb_queues(adapter))
4052                 goto done;
4053
4054 #endif
4055         if (ixgbe_set_fdir_queues(adapter))
4056                 goto done;
4057
4058         if (ixgbe_set_rss_queues(adapter))
4059                 goto done;
4060
4061         /* fallback to base case */
4062         adapter->num_rx_queues = 1;
4063         adapter->num_tx_queues = 1;
4064
4065 done:
4066         /* Notify the stack of the (possibly) reduced Tx Queue count. */
4067         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4068 }
4069
4070 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4071                                        int vectors)
4072 {
4073         int err, vector_threshold;
4074
4075         /* We'll want at least 3 (vector_threshold):
4076          * 1) TxQ[0] Cleanup
4077          * 2) RxQ[0] Cleanup
4078          * 3) Other (Link Status Change, etc.)
4079          * 4) TCP Timer (optional)
4080          */
4081         vector_threshold = MIN_MSIX_COUNT;
4082
4083         /* The more we get, the more we will assign to Tx/Rx Cleanup
4084          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4085          * Right now, we simply care about how many we'll get; we'll
4086          * set them up later while requesting irq's.
4087          */
4088         while (vectors >= vector_threshold) {
4089                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4090                                       vectors);
4091                 if (!err) /* Success in acquiring all requested vectors. */
4092                         break;
4093                 else if (err < 0)
4094                         vectors = 0; /* Nasty failure, quit now */
4095                 else /* err == number of vectors we should try again with */
4096                         vectors = err;
4097         }
4098
4099         if (vectors < vector_threshold) {
4100                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4101                  * This just means we'll go with either a single MSI
4102                  * vector or fall back to legacy interrupts.
4103                  */
4104                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4105                              "Unable to allocate MSI-X interrupts\n");
4106                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4107                 kfree(adapter->msix_entries);
4108                 adapter->msix_entries = NULL;
4109         } else {
4110                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4111                 /*
4112                  * Adjust for only the vectors we'll use, which is minimum
4113                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4114                  * vectors we were allocated.
4115                  */
4116                 adapter->num_msix_vectors = min(vectors,
4117                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4118         }
4119 }
4120
4121 /**
4122  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4123  * @adapter: board private structure to initialize
4124  *
4125  * Cache the descriptor ring offsets for RSS to the assigned rings.
4126  *
4127  **/
4128 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4129 {
4130         int i;
4131         bool ret = false;
4132
4133         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4134                 for (i = 0; i < adapter->num_rx_queues; i++)
4135                         adapter->rx_ring[i]->reg_idx = i;
4136                 for (i = 0; i < adapter->num_tx_queues; i++)
4137                         adapter->tx_ring[i]->reg_idx = i;
4138                 ret = true;
4139         } else {
4140                 ret = false;
4141         }
4142
4143         return ret;
4144 }
4145
4146 #ifdef CONFIG_IXGBE_DCB
4147 /**
4148  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4149  * @adapter: board private structure to initialize
4150  *
4151  * Cache the descriptor ring offsets for DCB to the assigned rings.
4152  *
4153  **/
4154 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4155 {
4156         int i;
4157         bool ret = false;
4158         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4159
4160         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4161                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4162                         /* the number of queues is assumed to be symmetric */
4163                         for (i = 0; i < dcb_i; i++) {
4164                                 adapter->rx_ring[i]->reg_idx = i << 3;
4165                                 adapter->tx_ring[i]->reg_idx = i << 2;
4166                         }
4167                         ret = true;
4168                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4169                         if (dcb_i == 8) {
4170                                 /*
4171                                  * Tx TC0 starts at: descriptor queue 0
4172                                  * Tx TC1 starts at: descriptor queue 32
4173                                  * Tx TC2 starts at: descriptor queue 64
4174                                  * Tx TC3 starts at: descriptor queue 80
4175                                  * Tx TC4 starts at: descriptor queue 96
4176                                  * Tx TC5 starts at: descriptor queue 104
4177                                  * Tx TC6 starts at: descriptor queue 112
4178                                  * Tx TC7 starts at: descriptor queue 120
4179                                  *
4180                                  * Rx TC0-TC7 are offset by 16 queues each
4181                                  */
4182                                 for (i = 0; i < 3; i++) {
4183                                         adapter->tx_ring[i]->reg_idx = i << 5;
4184                                         adapter->rx_ring[i]->reg_idx = i << 4;
4185                                 }
4186                                 for ( ; i < 5; i++) {
4187                                         adapter->tx_ring[i]->reg_idx =
4188                                                                  ((i + 2) << 4);
4189                                         adapter->rx_ring[i]->reg_idx = i << 4;
4190                                 }
4191                                 for ( ; i < dcb_i; i++) {
4192                                         adapter->tx_ring[i]->reg_idx =
4193                                                                  ((i + 8) << 3);
4194                                         adapter->rx_ring[i]->reg_idx = i << 4;
4195                                 }
4196
4197                                 ret = true;
4198                         } else if (dcb_i == 4) {
4199                                 /*
4200                                  * Tx TC0 starts at: descriptor queue 0
4201                                  * Tx TC1 starts at: descriptor queue 64
4202                                  * Tx TC2 starts at: descriptor queue 96
4203                                  * Tx TC3 starts at: descriptor queue 112
4204                                  *
4205                                  * Rx TC0-TC3 are offset by 32 queues each
4206                                  */
4207                                 adapter->tx_ring[0]->reg_idx = 0;
4208                                 adapter->tx_ring[1]->reg_idx = 64;
4209                                 adapter->tx_ring[2]->reg_idx = 96;
4210                                 adapter->tx_ring[3]->reg_idx = 112;
4211                                 for (i = 0 ; i < dcb_i; i++)
4212                                         adapter->rx_ring[i]->reg_idx = i << 5;
4213
4214                                 ret = true;
4215                         } else {
4216                                 ret = false;
4217                         }
4218                 } else {
4219                         ret = false;
4220                 }
4221         } else {
4222                 ret = false;
4223         }
4224
4225         return ret;
4226 }
4227 #endif
4228
4229 /**
4230  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4231  * @adapter: board private structure to initialize
4232  *
4233  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4234  *
4235  **/
4236 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4237 {
4238         int i;
4239         bool ret = false;
4240
4241         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4242             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4243              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4244                 for (i = 0; i < adapter->num_rx_queues; i++)
4245                         adapter->rx_ring[i]->reg_idx = i;
4246                 for (i = 0; i < adapter->num_tx_queues; i++)
4247                         adapter->tx_ring[i]->reg_idx = i;
4248                 ret = true;
4249         }
4250
4251         return ret;
4252 }
4253
4254 #ifdef IXGBE_FCOE
4255 /**
4256  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4257  * @adapter: board private structure to initialize
4258  *
4259  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4260  *
4261  */
4262 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4263 {
4264         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4265         bool ret = false;
4266         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4267
4268         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4269 #ifdef CONFIG_IXGBE_DCB
4270                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4271                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4272
4273                         ixgbe_cache_ring_dcb(adapter);
4274                         /* find out queues in TC for FCoE */
4275                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4276                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4277                         /*
4278                          * In 82599, the number of Tx queues for each traffic
4279                          * class for both 8-TC and 4-TC modes are:
4280                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4281                          * 8 TCs:  32  32  16  16   8   8   8   8
4282                          * 4 TCs:  64  64  32  32
4283                          * We have max 8 queues for FCoE, where 8 the is
4284                          * FCoE redirection table size. If TC for FCoE is
4285                          * less than or equal to TC3, we have enough queues
4286                          * to add max of 8 queues for FCoE, so we start FCoE
4287                          * tx descriptor from the next one, i.e., reg_idx + 1.
4288                          * If TC for FCoE is above TC3, implying 8 TC mode,
4289                          * and we need 8 for FCoE, we have to take all queues
4290                          * in that traffic class for FCoE.
4291                          */
4292                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4293                                 fcoe_tx_i--;
4294                 }
4295 #endif /* CONFIG_IXGBE_DCB */
4296                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4297                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4298                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4299                                 ixgbe_cache_ring_fdir(adapter);
4300                         else
4301                                 ixgbe_cache_ring_rss(adapter);
4302
4303                         fcoe_rx_i = f->mask;
4304                         fcoe_tx_i = f->mask;
4305                 }
4306                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4307                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4308                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4309                 }
4310                 ret = true;
4311         }
4312         return ret;
4313 }
4314
4315 #endif /* IXGBE_FCOE */
4316 /**
4317  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4318  * @adapter: board private structure to initialize
4319  *
4320  * SR-IOV doesn't use any descriptor rings but changes the default if
4321  * no other mapping is used.
4322  *
4323  */
4324 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4325 {
4326         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4327         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4328         if (adapter->num_vfs)
4329                 return true;
4330         else
4331                 return false;
4332 }
4333
4334 /**
4335  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4336  * @adapter: board private structure to initialize
4337  *
4338  * Once we know the feature-set enabled for the device, we'll cache
4339  * the register offset the descriptor ring is assigned to.
4340  *
4341  * Note, the order the various feature calls is important.  It must start with
4342  * the "most" features enabled at the same time, then trickle down to the
4343  * least amount of features turned on at once.
4344  **/
4345 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4346 {
4347         /* start with default case */
4348         adapter->rx_ring[0]->reg_idx = 0;
4349         adapter->tx_ring[0]->reg_idx = 0;
4350
4351         if (ixgbe_cache_ring_sriov(adapter))
4352                 return;
4353
4354 #ifdef IXGBE_FCOE
4355         if (ixgbe_cache_ring_fcoe(adapter))
4356                 return;
4357
4358 #endif /* IXGBE_FCOE */
4359 #ifdef CONFIG_IXGBE_DCB
4360         if (ixgbe_cache_ring_dcb(adapter))
4361                 return;
4362
4363 #endif
4364         if (ixgbe_cache_ring_fdir(adapter))
4365                 return;
4366
4367         if (ixgbe_cache_ring_rss(adapter))
4368                 return;
4369 }
4370
4371 /**
4372  * ixgbe_alloc_queues - Allocate memory for all rings
4373  * @adapter: board private structure to initialize
4374  *
4375  * We allocate one ring per queue at run-time since we don't know the
4376  * number of queues at compile-time.  The polling_netdev array is
4377  * intended for Multiqueue, but should work fine with a single queue.
4378  **/
4379 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4380 {
4381         int i;
4382         int orig_node = adapter->node;
4383
4384         for (i = 0; i < adapter->num_tx_queues; i++) {
4385                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4386                 if (orig_node == -1) {
4387                         int cur_node = next_online_node(adapter->node);
4388                         if (cur_node == MAX_NUMNODES)
4389                                 cur_node = first_online_node;
4390                         adapter->node = cur_node;
4391                 }
4392                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4393                                     adapter->node);
4394                 if (!ring)
4395                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4396                 if (!ring)
4397                         goto err_tx_ring_allocation;
4398                 ring->count = adapter->tx_ring_count;
4399                 ring->queue_index = i;
4400                 ring->numa_node = adapter->node;
4401
4402                 adapter->tx_ring[i] = ring;
4403         }
4404
4405         /* Restore the adapter's original node */
4406         adapter->node = orig_node;
4407
4408         for (i = 0; i < adapter->num_rx_queues; i++) {
4409                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4410                 if (orig_node == -1) {
4411                         int cur_node = next_online_node(adapter->node);
4412                         if (cur_node == MAX_NUMNODES)
4413                                 cur_node = first_online_node;
4414                         adapter->node = cur_node;
4415                 }
4416                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4417                                     adapter->node);
4418                 if (!ring)
4419                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4420                 if (!ring)
4421                         goto err_rx_ring_allocation;
4422                 ring->count = adapter->rx_ring_count;
4423                 ring->queue_index = i;
4424                 ring->numa_node = adapter->node;
4425
4426                 adapter->rx_ring[i] = ring;
4427         }
4428
4429         /* Restore the adapter's original node */
4430         adapter->node = orig_node;
4431
4432         ixgbe_cache_ring_register(adapter);
4433
4434         return 0;
4435
4436 err_rx_ring_allocation:
4437         for (i = 0; i < adapter->num_tx_queues; i++)
4438                 kfree(adapter->tx_ring[i]);
4439 err_tx_ring_allocation:
4440         return -ENOMEM;
4441 }
4442
4443 /**
4444  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4445  * @adapter: board private structure to initialize
4446  *
4447  * Attempt to configure the interrupts using the best available
4448  * capabilities of the hardware and the kernel.
4449  **/
4450 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4451 {
4452         struct ixgbe_hw *hw = &adapter->hw;
4453         int err = 0;
4454         int vector, v_budget;
4455
4456         /*
4457          * It's easy to be greedy for MSI-X vectors, but it really
4458          * doesn't do us much good if we have a lot more vectors
4459          * than CPU's.  So let's be conservative and only ask for
4460          * (roughly) the same number of vectors as there are CPU's.
4461          */
4462         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4463                        (int)num_online_cpus()) + NON_Q_VECTORS;
4464
4465         /*
4466          * At the same time, hardware can only support a maximum of
4467          * hw.mac->max_msix_vectors vectors.  With features
4468          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4469          * descriptor queues supported by our device.  Thus, we cap it off in
4470          * those rare cases where the cpu count also exceeds our vector limit.
4471          */
4472         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4473
4474         /* A failure in MSI-X entry allocation isn't fatal, but it does
4475          * mean we disable MSI-X capabilities of the adapter. */
4476         adapter->msix_entries = kcalloc(v_budget,
4477                                         sizeof(struct msix_entry), GFP_KERNEL);
4478         if (adapter->msix_entries) {
4479                 for (vector = 0; vector < v_budget; vector++)
4480                         adapter->msix_entries[vector].entry = vector;
4481
4482                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4483
4484                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4485                         goto out;
4486         }
4487
4488         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4489         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4490         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4491         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4492         adapter->atr_sample_rate = 0;
4493         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4494                 ixgbe_disable_sriov(adapter);
4495
4496         ixgbe_set_num_queues(adapter);
4497
4498         err = pci_enable_msi(adapter->pdev);
4499         if (!err) {
4500                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4501         } else {
4502                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4503                              "Unable to allocate MSI interrupt, "
4504                              "falling back to legacy.  Error: %d\n", err);
4505                 /* reset err */
4506                 err = 0;
4507         }
4508
4509 out:
4510         return err;
4511 }
4512
4513 /**
4514  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4515  * @adapter: board private structure to initialize
4516  *
4517  * We allocate one q_vector per queue interrupt.  If allocation fails we
4518  * return -ENOMEM.
4519  **/
4520 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4521 {
4522         int q_idx, num_q_vectors;
4523         struct ixgbe_q_vector *q_vector;
4524         int napi_vectors;
4525         int (*poll)(struct napi_struct *, int);
4526
4527         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4528                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4529                 napi_vectors = adapter->num_rx_queues;
4530                 poll = &ixgbe_clean_rxtx_many;
4531         } else {
4532                 num_q_vectors = 1;
4533                 napi_vectors = 1;
4534                 poll = &ixgbe_poll;
4535         }
4536
4537         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4538                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4539                                         GFP_KERNEL, adapter->node);
4540                 if (!q_vector)
4541                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4542                                            GFP_KERNEL);
4543                 if (!q_vector)
4544                         goto err_out;
4545                 q_vector->adapter = adapter;
4546                 if (q_vector->txr_count && !q_vector->rxr_count)
4547                         q_vector->eitr = adapter->tx_eitr_param;
4548                 else
4549                         q_vector->eitr = adapter->rx_eitr_param;
4550                 q_vector->v_idx = q_idx;
4551                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4552                 adapter->q_vector[q_idx] = q_vector;
4553         }
4554
4555         return 0;
4556
4557 err_out:
4558         while (q_idx) {
4559                 q_idx--;
4560                 q_vector = adapter->q_vector[q_idx];
4561                 netif_napi_del(&q_vector->napi);
4562                 kfree(q_vector);
4563                 adapter->q_vector[q_idx] = NULL;
4564         }
4565         return -ENOMEM;
4566 }
4567
4568 /**
4569  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4570  * @adapter: board private structure to initialize
4571  *
4572  * This function frees the memory allocated to the q_vectors.  In addition if
4573  * NAPI is enabled it will delete any references to the NAPI struct prior
4574  * to freeing the q_vector.
4575  **/
4576 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4577 {
4578         int q_idx, num_q_vectors;
4579
4580         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4581                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4582         else
4583                 num_q_vectors = 1;
4584
4585         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4586                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4587                 adapter->q_vector[q_idx] = NULL;
4588                 netif_napi_del(&q_vector->napi);
4589                 kfree(q_vector);
4590         }
4591 }
4592
4593 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4594 {
4595         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4596                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4597                 pci_disable_msix(adapter->pdev);
4598                 kfree(adapter->msix_entries);
4599                 adapter->msix_entries = NULL;
4600         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4601                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4602                 pci_disable_msi(adapter->pdev);
4603         }
4604 }
4605
4606 /**
4607  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4608  * @adapter: board private structure to initialize
4609  *
4610  * We determine which interrupt scheme to use based on...
4611  * - Kernel support (MSI, MSI-X)
4612  *   - which can be user-defined (via MODULE_PARAM)
4613  * - Hardware queue count (num_*_queues)
4614  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4615  **/
4616 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4617 {
4618         int err;
4619
4620         /* Number of supported queues */
4621         ixgbe_set_num_queues(adapter);
4622
4623         err = ixgbe_set_interrupt_capability(adapter);
4624         if (err) {
4625                 e_dev_err("Unable to setup interrupt capabilities\n");
4626                 goto err_set_interrupt;
4627         }
4628
4629         err = ixgbe_alloc_q_vectors(adapter);
4630         if (err) {
4631                 e_dev_err("Unable to allocate memory for queue vectors\n");
4632                 goto err_alloc_q_vectors;
4633         }
4634
4635         err = ixgbe_alloc_queues(adapter);
4636         if (err) {
4637                 e_dev_err("Unable to allocate memory for queues\n");
4638                 goto err_alloc_queues;
4639         }
4640
4641         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4642                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4643                    adapter->num_rx_queues, adapter->num_tx_queues);
4644
4645         set_bit(__IXGBE_DOWN, &adapter->state);
4646
4647         return 0;
4648
4649 err_alloc_queues:
4650         ixgbe_free_q_vectors(adapter);
4651 err_alloc_q_vectors:
4652         ixgbe_reset_interrupt_capability(adapter);
4653 err_set_interrupt:
4654         return err;
4655 }
4656
4657 /**
4658  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4659  * @adapter: board private structure to clear interrupt scheme on
4660  *
4661  * We go through and clear interrupt specific resources and reset the structure
4662  * to pre-load conditions
4663  **/
4664 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4665 {
4666         int i;
4667
4668         for (i = 0; i < adapter->num_tx_queues; i++) {
4669                 kfree(adapter->tx_ring[i]);
4670                 adapter->tx_ring[i] = NULL;
4671         }
4672         for (i = 0; i < adapter->num_rx_queues; i++) {
4673                 kfree(adapter->rx_ring[i]);
4674                 adapter->rx_ring[i] = NULL;
4675         }
4676
4677         ixgbe_free_q_vectors(adapter);
4678         ixgbe_reset_interrupt_capability(adapter);
4679 }
4680
4681 /**
4682  * ixgbe_sfp_timer - worker thread to find a missing module
4683  * @data: pointer to our adapter struct
4684  **/
4685 static void ixgbe_sfp_timer(unsigned long data)
4686 {
4687         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4688
4689         /*
4690          * Do the sfp_timer outside of interrupt context due to the
4691          * delays that sfp+ detection requires
4692          */
4693         schedule_work(&adapter->sfp_task);
4694 }
4695
4696 /**
4697  * ixgbe_sfp_task - worker thread to find a missing module
4698  * @work: pointer to work_struct containing our data
4699  **/
4700 static void ixgbe_sfp_task(struct work_struct *work)
4701 {
4702         struct ixgbe_adapter *adapter = container_of(work,
4703                                                      struct ixgbe_adapter,
4704                                                      sfp_task);
4705         struct ixgbe_hw *hw = &adapter->hw;
4706
4707         if ((hw->phy.type == ixgbe_phy_nl) &&
4708             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4709                 s32 ret = hw->phy.ops.identify_sfp(hw);
4710                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4711                         goto reschedule;
4712                 ret = hw->phy.ops.reset(hw);
4713                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4714                         e_dev_err("failed to initialize because an unsupported "
4715                                   "SFP+ module type was detected.\n");
4716                         e_dev_err("Reload the driver after installing a "
4717                                   "supported module.\n");
4718                         unregister_netdev(adapter->netdev);
4719                 } else {
4720                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4721                 }
4722                 /* don't need this routine any more */
4723                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4724         }
4725         return;
4726 reschedule:
4727         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4728                 mod_timer(&adapter->sfp_timer,
4729                           round_jiffies(jiffies + (2 * HZ)));
4730 }
4731
4732 /**
4733  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4734  * @adapter: board private structure to initialize
4735  *
4736  * ixgbe_sw_init initializes the Adapter private data structure.
4737  * Fields are initialized based on PCI device information and
4738  * OS network device settings (MTU size).
4739  **/
4740 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4741 {
4742         struct ixgbe_hw *hw = &adapter->hw;
4743         struct pci_dev *pdev = adapter->pdev;
4744         struct net_device *dev = adapter->netdev;
4745         unsigned int rss;
4746 #ifdef CONFIG_IXGBE_DCB
4747         int j;
4748         struct tc_configuration *tc;
4749 #endif
4750
4751         /* PCI config space info */
4752
4753         hw->vendor_id = pdev->vendor;
4754         hw->device_id = pdev->device;
4755         hw->revision_id = pdev->revision;
4756         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4757         hw->subsystem_device_id = pdev->subsystem_device;
4758
4759         /* Set capability flags */
4760         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4761         adapter->ring_feature[RING_F_RSS].indices = rss;
4762         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4763         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4764         if (hw->mac.type == ixgbe_mac_82598EB) {
4765                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4766                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4767                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4768         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4769                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4770                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4771                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4772                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4773                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4774                 if (dev->features & NETIF_F_NTUPLE) {
4775                         /* Flow Director perfect filter enabled */
4776                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4777                         adapter->atr_sample_rate = 0;
4778                         spin_lock_init(&adapter->fdir_perfect_lock);
4779                 } else {
4780                         /* Flow Director hash filters enabled */
4781                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4782                         adapter->atr_sample_rate = 20;
4783                 }
4784                 adapter->ring_feature[RING_F_FDIR].indices =
4785                                                          IXGBE_MAX_FDIR_INDICES;
4786                 adapter->fdir_pballoc = 0;
4787 #ifdef IXGBE_FCOE
4788                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4789                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4790                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4791 #ifdef CONFIG_IXGBE_DCB
4792                 /* Default traffic class to use for FCoE */
4793                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4794                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4795 #endif
4796 #endif /* IXGBE_FCOE */
4797         }
4798
4799 #ifdef CONFIG_IXGBE_DCB
4800         /* Configure DCB traffic classes */
4801         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4802                 tc = &adapter->dcb_cfg.tc_config[j];
4803                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4804                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4805                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4806                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4807                 tc->dcb_pfc = pfc_disabled;
4808         }
4809         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4810         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4811         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4812         adapter->dcb_cfg.pfc_mode_enable = false;
4813         adapter->dcb_cfg.round_robin_enable = false;
4814         adapter->dcb_set_bitmap = 0x00;
4815         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4816                            adapter->ring_feature[RING_F_DCB].indices);
4817
4818 #endif
4819
4820         /* default flow control settings */
4821         hw->fc.requested_mode = ixgbe_fc_full;
4822         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4823 #ifdef CONFIG_DCB
4824         adapter->last_lfc_mode = hw->fc.current_mode;
4825 #endif
4826         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4827         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4828         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4829         hw->fc.send_xon = true;
4830         hw->fc.disable_fc_autoneg = false;
4831
4832         /* enable itr by default in dynamic mode */
4833         adapter->rx_itr_setting = 1;
4834         adapter->rx_eitr_param = 20000;
4835         adapter->tx_itr_setting = 1;
4836         adapter->tx_eitr_param = 10000;
4837
4838         /* set defaults for eitr in MegaBytes */
4839         adapter->eitr_low = 10;
4840         adapter->eitr_high = 20;
4841
4842         /* set default ring sizes */
4843         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4844         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4845
4846         /* initialize eeprom parameters */
4847         if (ixgbe_init_eeprom_params_generic(hw)) {
4848                 e_dev_err("EEPROM initialization failed\n");
4849                 return -EIO;
4850         }
4851
4852         /* enable rx csum by default */
4853         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4854
4855         /* get assigned NUMA node */
4856         adapter->node = dev_to_node(&pdev->dev);
4857
4858         set_bit(__IXGBE_DOWN, &adapter->state);
4859
4860         return 0;
4861 }
4862
4863 /**
4864  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4865  * @adapter: board private structure
4866  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4867  *
4868  * Return 0 on success, negative on failure
4869  **/
4870 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4871                              struct ixgbe_ring *tx_ring)
4872 {
4873         struct pci_dev *pdev = adapter->pdev;
4874         int size;
4875
4876         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4877         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4878         if (!tx_ring->tx_buffer_info)
4879                 tx_ring->tx_buffer_info = vmalloc(size);
4880         if (!tx_ring->tx_buffer_info)
4881                 goto err;
4882         memset(tx_ring->tx_buffer_info, 0, size);
4883
4884         /* round up to nearest 4K */
4885         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4886         tx_ring->size = ALIGN(tx_ring->size, 4096);
4887
4888         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4889                                            &tx_ring->dma, GFP_KERNEL);
4890         if (!tx_ring->desc)
4891                 goto err;
4892
4893         tx_ring->next_to_use = 0;
4894         tx_ring->next_to_clean = 0;
4895         tx_ring->work_limit = tx_ring->count;
4896         return 0;
4897
4898 err:
4899         vfree(tx_ring->tx_buffer_info);
4900         tx_ring->tx_buffer_info = NULL;
4901         e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4902         return -ENOMEM;
4903 }
4904
4905 /**
4906  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4907  * @adapter: board private structure
4908  *
4909  * If this function returns with an error, then it's possible one or
4910  * more of the rings is populated (while the rest are not).  It is the
4911  * callers duty to clean those orphaned rings.
4912  *
4913  * Return 0 on success, negative on failure
4914  **/
4915 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4916 {
4917         int i, err = 0;
4918
4919         for (i = 0; i < adapter->num_tx_queues; i++) {
4920                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4921                 if (!err)
4922                         continue;
4923                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4924                 break;
4925         }
4926
4927         return err;
4928 }
4929
4930 /**
4931  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4932  * @adapter: board private structure
4933  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4934  *
4935  * Returns 0 on success, negative on failure
4936  **/
4937 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4938                              struct ixgbe_ring *rx_ring)
4939 {
4940         struct pci_dev *pdev = adapter->pdev;
4941         int size;
4942
4943         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4944         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4945         if (!rx_ring->rx_buffer_info)
4946                 rx_ring->rx_buffer_info = vmalloc(size);
4947         if (!rx_ring->rx_buffer_info) {
4948                 e_err(probe, "vmalloc allocation failed for the Rx "
4949                       "descriptor ring\n");
4950                 goto alloc_failed;
4951         }
4952         memset(rx_ring->rx_buffer_info, 0, size);
4953
4954         /* Round up to nearest 4K */
4955         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4956         rx_ring->size = ALIGN(rx_ring->size, 4096);
4957
4958         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4959                                            &rx_ring->dma, GFP_KERNEL);
4960
4961         if (!rx_ring->desc) {
4962                 e_err(probe, "Memory allocation failed for the Rx "
4963                       "descriptor ring\n");
4964                 vfree(rx_ring->rx_buffer_info);
4965                 goto alloc_failed;
4966         }
4967
4968         rx_ring->next_to_clean = 0;
4969         rx_ring->next_to_use = 0;
4970
4971         return 0;
4972
4973 alloc_failed:
4974         return -ENOMEM;
4975 }
4976
4977 /**
4978  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4979  * @adapter: board private structure
4980  *
4981  * If this function returns with an error, then it's possible one or
4982  * more of the rings is populated (while the rest are not).  It is the
4983  * callers duty to clean those orphaned rings.
4984  *
4985  * Return 0 on success, negative on failure
4986  **/
4987
4988 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4989 {
4990         int i, err = 0;
4991
4992         for (i = 0; i < adapter->num_rx_queues; i++) {
4993                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4994                 if (!err)
4995                         continue;
4996                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4997                 break;
4998         }
4999
5000         return err;
5001 }
5002
5003 /**
5004  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5005  * @adapter: board private structure
5006  * @tx_ring: Tx descriptor ring for a specific queue
5007  *
5008  * Free all transmit software resources
5009  **/
5010 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5011                              struct ixgbe_ring *tx_ring)
5012 {
5013         struct pci_dev *pdev = adapter->pdev;
5014
5015         ixgbe_clean_tx_ring(adapter, tx_ring);
5016
5017         vfree(tx_ring->tx_buffer_info);
5018         tx_ring->tx_buffer_info = NULL;
5019
5020         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5021                           tx_ring->dma);
5022
5023         tx_ring->desc = NULL;
5024 }
5025
5026 /**
5027  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5028  * @adapter: board private structure
5029  *
5030  * Free all transmit software resources
5031  **/
5032 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5033 {
5034         int i;
5035
5036         for (i = 0; i < adapter->num_tx_queues; i++)
5037                 if (adapter->tx_ring[i]->desc)
5038                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5039 }
5040
5041 /**
5042  * ixgbe_free_rx_resources - Free Rx Resources
5043  * @adapter: board private structure
5044  * @rx_ring: ring to clean the resources from
5045  *
5046  * Free all receive software resources
5047  **/
5048 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5049                              struct ixgbe_ring *rx_ring)
5050 {
5051         struct pci_dev *pdev = adapter->pdev;
5052
5053         ixgbe_clean_rx_ring(adapter, rx_ring);
5054
5055         vfree(rx_ring->rx_buffer_info);
5056         rx_ring->rx_buffer_info = NULL;
5057
5058         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5059                           rx_ring->dma);
5060
5061         rx_ring->desc = NULL;
5062 }
5063
5064 /**
5065  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5066  * @adapter: board private structure
5067  *
5068  * Free all receive software resources
5069  **/
5070 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5071 {
5072         int i;
5073
5074         for (i = 0; i < adapter->num_rx_queues; i++)
5075                 if (adapter->rx_ring[i]->desc)
5076                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5077 }
5078
5079 /**
5080  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5081  * @netdev: network interface device structure
5082  * @new_mtu: new value for maximum frame size
5083  *
5084  * Returns 0 on success, negative on failure
5085  **/
5086 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5087 {
5088         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5089         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5090
5091         /* MTU < 68 is an error and causes problems on some kernels */
5092         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5093                 return -EINVAL;
5094
5095         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5096         /* must set new MTU before calling down or up */
5097         netdev->mtu = new_mtu;
5098
5099         if (netif_running(netdev))
5100                 ixgbe_reinit_locked(adapter);
5101
5102         return 0;
5103 }
5104
5105 /**
5106  * ixgbe_open - Called when a network interface is made active
5107  * @netdev: network interface device structure
5108  *
5109  * Returns 0 on success, negative value on failure
5110  *
5111  * The open entry point is called when a network interface is made
5112  * active by the system (IFF_UP).  At this point all resources needed
5113  * for transmit and receive operations are allocated, the interrupt
5114  * handler is registered with the OS, the watchdog timer is started,
5115  * and the stack is notified that the interface is ready.
5116  **/
5117 static int ixgbe_open(struct net_device *netdev)
5118 {
5119         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5120         int err;
5121
5122         /* disallow open during test */
5123         if (test_bit(__IXGBE_TESTING, &adapter->state))
5124                 return -EBUSY;
5125
5126         netif_carrier_off(netdev);
5127
5128         /* allocate transmit descriptors */
5129         err = ixgbe_setup_all_tx_resources(adapter);
5130         if (err)
5131                 goto err_setup_tx;
5132
5133         /* allocate receive descriptors */
5134         err = ixgbe_setup_all_rx_resources(adapter);
5135         if (err)
5136                 goto err_setup_rx;
5137
5138         ixgbe_configure(adapter);
5139
5140         err = ixgbe_request_irq(adapter);
5141         if (err)
5142                 goto err_req_irq;
5143
5144         err = ixgbe_up_complete(adapter);
5145         if (err)
5146                 goto err_up;
5147
5148         netif_tx_start_all_queues(netdev);
5149
5150         return 0;
5151
5152 err_up:
5153         ixgbe_release_hw_control(adapter);
5154         ixgbe_free_irq(adapter);
5155 err_req_irq:
5156 err_setup_rx:
5157         ixgbe_free_all_rx_resources(adapter);
5158 err_setup_tx:
5159         ixgbe_free_all_tx_resources(adapter);
5160         ixgbe_reset(adapter);
5161
5162         return err;
5163 }
5164
5165 /**
5166  * ixgbe_close - Disables a network interface
5167  * @netdev: network interface device structure
5168  *
5169  * Returns 0, this is not allowed to fail
5170  *
5171  * The close entry point is called when an interface is de-activated
5172  * by the OS.  The hardware is still under the drivers control, but
5173  * needs to be disabled.  A global MAC reset is issued to stop the
5174  * hardware, and all transmit and receive resources are freed.
5175  **/
5176 static int ixgbe_close(struct net_device *netdev)
5177 {
5178         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5179
5180         ixgbe_down(adapter);
5181         ixgbe_free_irq(adapter);
5182
5183         ixgbe_free_all_tx_resources(adapter);
5184         ixgbe_free_all_rx_resources(adapter);
5185
5186         ixgbe_release_hw_control(adapter);
5187
5188         return 0;
5189 }
5190
5191 #ifdef CONFIG_PM
5192 static int ixgbe_resume(struct pci_dev *pdev)
5193 {
5194         struct net_device *netdev = pci_get_drvdata(pdev);
5195         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5196         u32 err;
5197
5198         pci_set_power_state(pdev, PCI_D0);
5199         pci_restore_state(pdev);
5200         /*
5201          * pci_restore_state clears dev->state_saved so call
5202          * pci_save_state to restore it.
5203          */
5204         pci_save_state(pdev);
5205
5206         err = pci_enable_device_mem(pdev);
5207         if (err) {
5208                 e_dev_err("Cannot enable PCI device from suspend\n");
5209                 return err;
5210         }
5211         pci_set_master(pdev);
5212
5213         pci_wake_from_d3(pdev, false);
5214
5215         err = ixgbe_init_interrupt_scheme(adapter);
5216         if (err) {
5217                 e_dev_err("Cannot initialize interrupts for device\n");
5218                 return err;
5219         }
5220
5221         ixgbe_reset(adapter);
5222
5223         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5224
5225         if (netif_running(netdev)) {
5226                 err = ixgbe_open(adapter->netdev);
5227                 if (err)
5228                         return err;
5229         }
5230
5231         netif_device_attach(netdev);
5232
5233         return 0;
5234 }
5235 #endif /* CONFIG_PM */
5236
5237 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5238 {
5239         struct net_device *netdev = pci_get_drvdata(pdev);
5240         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5241         struct ixgbe_hw *hw = &adapter->hw;
5242         u32 ctrl, fctrl;
5243         u32 wufc = adapter->wol;
5244 #ifdef CONFIG_PM
5245         int retval = 0;
5246 #endif
5247
5248         netif_device_detach(netdev);
5249
5250         if (netif_running(netdev)) {
5251                 ixgbe_down(adapter);
5252                 ixgbe_free_irq(adapter);
5253                 ixgbe_free_all_tx_resources(adapter);
5254                 ixgbe_free_all_rx_resources(adapter);
5255         }
5256
5257 #ifdef CONFIG_PM
5258         retval = pci_save_state(pdev);
5259         if (retval)
5260                 return retval;
5261
5262 #endif
5263         if (wufc) {
5264                 ixgbe_set_rx_mode(netdev);
5265
5266                 /* turn on all-multi mode if wake on multicast is enabled */
5267                 if (wufc & IXGBE_WUFC_MC) {
5268                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5269                         fctrl |= IXGBE_FCTRL_MPE;
5270                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5271                 }
5272
5273                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5274                 ctrl |= IXGBE_CTRL_GIO_DIS;
5275                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5276
5277                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5278         } else {
5279                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5280                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5281         }
5282
5283         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5284                 pci_wake_from_d3(pdev, true);
5285         else
5286                 pci_wake_from_d3(pdev, false);
5287
5288         *enable_wake = !!wufc;
5289
5290         ixgbe_clear_interrupt_scheme(adapter);
5291
5292         ixgbe_release_hw_control(adapter);
5293
5294         pci_disable_device(pdev);
5295
5296         return 0;
5297 }
5298
5299 #ifdef CONFIG_PM
5300 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5301 {
5302         int retval;
5303         bool wake;
5304
5305         retval = __ixgbe_shutdown(pdev, &wake);
5306         if (retval)
5307                 return retval;
5308
5309         if (wake) {
5310                 pci_prepare_to_sleep(pdev);
5311         } else {
5312                 pci_wake_from_d3(pdev, false);
5313                 pci_set_power_state(pdev, PCI_D3hot);
5314         }
5315
5316         return 0;
5317 }
5318 #endif /* CONFIG_PM */
5319
5320 static void ixgbe_shutdown(struct pci_dev *pdev)
5321 {
5322         bool wake;
5323
5324         __ixgbe_shutdown(pdev, &wake);
5325
5326         if (system_state == SYSTEM_POWER_OFF) {
5327                 pci_wake_from_d3(pdev, wake);
5328                 pci_set_power_state(pdev, PCI_D3hot);
5329         }
5330 }
5331
5332 /**
5333  * ixgbe_update_stats - Update the board statistics counters.
5334  * @adapter: board private structure
5335  **/
5336 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5337 {
5338         struct net_device *netdev = adapter->netdev;
5339         struct ixgbe_hw *hw = &adapter->hw;
5340         u64 total_mpc = 0;
5341         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5342         u64 non_eop_descs = 0, restart_queue = 0;
5343
5344         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5345             test_bit(__IXGBE_RESETTING, &adapter->state))
5346                 return;
5347
5348         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5349                 u64 rsc_count = 0;
5350                 u64 rsc_flush = 0;
5351                 for (i = 0; i < 16; i++)
5352                         adapter->hw_rx_no_dma_resources +=
5353                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5354                 for (i = 0; i < adapter->num_rx_queues; i++) {
5355                         rsc_count += adapter->rx_ring[i]->rsc_count;
5356                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5357                 }
5358                 adapter->rsc_total_count = rsc_count;
5359                 adapter->rsc_total_flush = rsc_flush;
5360         }
5361
5362         /* gather some stats to the adapter struct that are per queue */
5363         for (i = 0; i < adapter->num_tx_queues; i++)
5364                 restart_queue += adapter->tx_ring[i]->restart_queue;
5365         adapter->restart_queue = restart_queue;
5366
5367         for (i = 0; i < adapter->num_rx_queues; i++)
5368                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5369         adapter->non_eop_descs = non_eop_descs;
5370
5371         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5372         for (i = 0; i < 8; i++) {
5373                 /* for packet buffers not used, the register should read 0 */
5374                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5375                 missed_rx += mpc;
5376                 adapter->stats.mpc[i] += mpc;
5377                 total_mpc += adapter->stats.mpc[i];
5378                 if (hw->mac.type == ixgbe_mac_82598EB)
5379                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5380                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5381                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5382                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5383                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5384                 if (hw->mac.type == ixgbe_mac_82599EB) {
5385                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5386                                                             IXGBE_PXONRXCNT(i));
5387                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5388                                                            IXGBE_PXOFFRXCNT(i));
5389                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5390                 } else {
5391                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5392                                                               IXGBE_PXONRXC(i));
5393                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5394                                                              IXGBE_PXOFFRXC(i));
5395                 }
5396                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5397                                                             IXGBE_PXONTXC(i));
5398                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5399                                                              IXGBE_PXOFFTXC(i));
5400         }
5401         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5402         /* work around hardware counting issue */
5403         adapter->stats.gprc -= missed_rx;
5404
5405         /* 82598 hardware only has a 32 bit counter in the high register */
5406         if (hw->mac.type == ixgbe_mac_82599EB) {
5407                 u64 tmp;
5408                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5409                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5410                 adapter->stats.gorc += (tmp << 32);
5411                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5412                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5413                 adapter->stats.gotc += (tmp << 32);
5414                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5415                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5416                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5417                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5418                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5419                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5420 #ifdef IXGBE_FCOE
5421                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5422                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5423                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5424                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5425                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5426                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5427 #endif /* IXGBE_FCOE */
5428         } else {
5429                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5430                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5431                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5432                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5433                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5434         }
5435         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5436         adapter->stats.bprc += bprc;
5437         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5438         if (hw->mac.type == ixgbe_mac_82598EB)
5439                 adapter->stats.mprc -= bprc;
5440         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5441         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5442         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5443         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5444         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5445         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5446         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5447         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5448         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5449         adapter->stats.lxontxc += lxon;
5450         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5451         adapter->stats.lxofftxc += lxoff;
5452         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5453         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5454         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5455         /*
5456          * 82598 errata - tx of flow control packets is included in tx counters
5457          */
5458         xon_off_tot = lxon + lxoff;
5459         adapter->stats.gptc -= xon_off_tot;
5460         adapter->stats.mptc -= xon_off_tot;
5461         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5462         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5463         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5464         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5465         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5466         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5467         adapter->stats.ptc64 -= xon_off_tot;
5468         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5469         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5470         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5471         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5472         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5473         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5474
5475         /* Fill out the OS statistics structure */
5476         netdev->stats.multicast = adapter->stats.mprc;
5477
5478         /* Rx Errors */
5479         netdev->stats.rx_errors = adapter->stats.crcerrs +
5480                                        adapter->stats.rlec;
5481         netdev->stats.rx_dropped = 0;
5482         netdev->stats.rx_length_errors = adapter->stats.rlec;
5483         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5484         netdev->stats.rx_missed_errors = total_mpc;
5485 }
5486
5487 /**
5488  * ixgbe_watchdog - Timer Call-back
5489  * @data: pointer to adapter cast into an unsigned long
5490  **/
5491 static void ixgbe_watchdog(unsigned long data)
5492 {
5493         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5494         struct ixgbe_hw *hw = &adapter->hw;
5495         u64 eics = 0;
5496         int i;
5497
5498         /*
5499          *  Do the watchdog outside of interrupt context due to the lovely
5500          * delays that some of the newer hardware requires
5501          */
5502
5503         if (test_bit(__IXGBE_DOWN, &adapter->state))
5504                 goto watchdog_short_circuit;
5505
5506         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5507                 /*
5508                  * for legacy and MSI interrupts don't set any bits
5509                  * that are enabled for EIAM, because this operation
5510                  * would set *both* EIMS and EICS for any bit in EIAM
5511                  */
5512                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5513                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5514                 goto watchdog_reschedule;
5515         }
5516
5517         /* get one bit for every active tx/rx interrupt vector */
5518         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5519                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5520                 if (qv->rxr_count || qv->txr_count)
5521                         eics |= ((u64)1 << i);
5522         }
5523
5524         /* Cause software interrupt to ensure rx rings are cleaned */
5525         ixgbe_irq_rearm_queues(adapter, eics);
5526
5527 watchdog_reschedule:
5528         /* Reset the timer */
5529         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5530
5531 watchdog_short_circuit:
5532         schedule_work(&adapter->watchdog_task);
5533 }
5534
5535 /**
5536  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5537  * @work: pointer to work_struct containing our data
5538  **/
5539 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5540 {
5541         struct ixgbe_adapter *adapter = container_of(work,
5542                                                      struct ixgbe_adapter,
5543                                                      multispeed_fiber_task);
5544         struct ixgbe_hw *hw = &adapter->hw;
5545         u32 autoneg;
5546         bool negotiation;
5547
5548         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5549         autoneg = hw->phy.autoneg_advertised;
5550         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5551                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5552         hw->mac.autotry_restart = false;
5553         if (hw->mac.ops.setup_link)
5554                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5555         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5556         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5557 }
5558
5559 /**
5560  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5561  * @work: pointer to work_struct containing our data
5562  **/
5563 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5564 {
5565         struct ixgbe_adapter *adapter = container_of(work,
5566                                                      struct ixgbe_adapter,
5567                                                      sfp_config_module_task);
5568         struct ixgbe_hw *hw = &adapter->hw;
5569         u32 err;
5570
5571         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5572
5573         /* Time for electrical oscillations to settle down */
5574         msleep(100);
5575         err = hw->phy.ops.identify_sfp(hw);
5576
5577         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5578                 e_dev_err("failed to initialize because an unsupported SFP+ "
5579                           "module type was detected.\n");
5580                 e_dev_err("Reload the driver after installing a supported "
5581                           "module.\n");
5582                 unregister_netdev(adapter->netdev);
5583                 return;
5584         }
5585         hw->mac.ops.setup_sfp(hw);
5586
5587         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5588                 /* This will also work for DA Twinax connections */
5589                 schedule_work(&adapter->multispeed_fiber_task);
5590         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5591 }
5592
5593 /**
5594  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5595  * @work: pointer to work_struct containing our data
5596  **/
5597 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5598 {
5599         struct ixgbe_adapter *adapter = container_of(work,
5600                                                      struct ixgbe_adapter,
5601                                                      fdir_reinit_task);
5602         struct ixgbe_hw *hw = &adapter->hw;
5603         int i;
5604
5605         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5606                 for (i = 0; i < adapter->num_tx_queues; i++)
5607                         set_bit(__IXGBE_FDIR_INIT_DONE,
5608                                 &(adapter->tx_ring[i]->reinit_state));
5609         } else {
5610                 e_err(probe, "failed to finish FDIR re-initialization, "
5611                       "ignored adding FDIR ATR filters\n");
5612         }
5613         /* Done FDIR Re-initialization, enable transmits */
5614         netif_tx_start_all_queues(adapter->netdev);
5615 }
5616
5617 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5618
5619 /**
5620  * ixgbe_watchdog_task - worker thread to bring link up
5621  * @work: pointer to work_struct containing our data
5622  **/
5623 static void ixgbe_watchdog_task(struct work_struct *work)
5624 {
5625         struct ixgbe_adapter *adapter = container_of(work,
5626                                                      struct ixgbe_adapter,
5627                                                      watchdog_task);
5628         struct net_device *netdev = adapter->netdev;
5629         struct ixgbe_hw *hw = &adapter->hw;
5630         u32 link_speed;
5631         bool link_up;
5632         int i;
5633         struct ixgbe_ring *tx_ring;
5634         int some_tx_pending = 0;
5635
5636         mutex_lock(&ixgbe_watchdog_lock);
5637
5638         link_up = adapter->link_up;
5639         link_speed = adapter->link_speed;
5640
5641         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5642                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5643                 if (link_up) {
5644 #ifdef CONFIG_DCB
5645                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5646                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5647                                         hw->mac.ops.fc_enable(hw, i);
5648                         } else {
5649                                 hw->mac.ops.fc_enable(hw, 0);
5650                         }
5651 #else
5652                         hw->mac.ops.fc_enable(hw, 0);
5653 #endif
5654                 }
5655
5656                 if (link_up ||
5657                     time_after(jiffies, (adapter->link_check_timeout +
5658                                          IXGBE_TRY_LINK_TIMEOUT))) {
5659                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5660                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5661                 }
5662                 adapter->link_up = link_up;
5663                 adapter->link_speed = link_speed;
5664         }
5665
5666         if (link_up) {
5667                 if (!netif_carrier_ok(netdev)) {
5668                         bool flow_rx, flow_tx;
5669
5670                         if (hw->mac.type == ixgbe_mac_82599EB) {
5671                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5672                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5673                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5674                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5675                         } else {
5676                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5677                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5678                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5679                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5680                         }
5681
5682                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5683                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5684                                "10 Gbps" :
5685                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5686                                "1 Gbps" : "unknown speed")),
5687                                ((flow_rx && flow_tx) ? "RX/TX" :
5688                                (flow_rx ? "RX" :
5689                                (flow_tx ? "TX" : "None"))));
5690
5691                         netif_carrier_on(netdev);
5692                 } else {
5693                         /* Force detection of hung controller */
5694                         adapter->detect_tx_hung = true;
5695                 }
5696         } else {
5697                 adapter->link_up = false;
5698                 adapter->link_speed = 0;
5699                 if (netif_carrier_ok(netdev)) {
5700                         e_info(drv, "NIC Link is Down\n");
5701                         netif_carrier_off(netdev);
5702                 }
5703         }
5704
5705         if (!netif_carrier_ok(netdev)) {
5706                 for (i = 0; i < adapter->num_tx_queues; i++) {
5707                         tx_ring = adapter->tx_ring[i];
5708                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5709                                 some_tx_pending = 1;
5710                                 break;
5711                         }
5712                 }
5713
5714                 if (some_tx_pending) {
5715                         /* We've lost link, so the controller stops DMA,
5716                          * but we've got queued Tx work that's never going
5717                          * to get done, so reset controller to flush Tx.
5718                          * (Do the reset outside of interrupt context).
5719                          */
5720                          schedule_work(&adapter->reset_task);
5721                 }
5722         }
5723
5724         ixgbe_update_stats(adapter);
5725         mutex_unlock(&ixgbe_watchdog_lock);
5726 }
5727
5728 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5729                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5730                      u32 tx_flags, u8 *hdr_len)
5731 {
5732         struct ixgbe_adv_tx_context_desc *context_desc;
5733         unsigned int i;
5734         int err;
5735         struct ixgbe_tx_buffer *tx_buffer_info;
5736         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5737         u32 mss_l4len_idx, l4len;
5738
5739         if (skb_is_gso(skb)) {
5740                 if (skb_header_cloned(skb)) {
5741                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5742                         if (err)
5743                                 return err;
5744                 }
5745                 l4len = tcp_hdrlen(skb);
5746                 *hdr_len += l4len;
5747
5748                 if (skb->protocol == htons(ETH_P_IP)) {
5749                         struct iphdr *iph = ip_hdr(skb);
5750                         iph->tot_len = 0;
5751                         iph->check = 0;
5752                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5753                                                                  iph->daddr, 0,
5754                                                                  IPPROTO_TCP,
5755                                                                  0);
5756                 } else if (skb_is_gso_v6(skb)) {
5757                         ipv6_hdr(skb)->payload_len = 0;
5758                         tcp_hdr(skb)->check =
5759                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5760                                              &ipv6_hdr(skb)->daddr,
5761                                              0, IPPROTO_TCP, 0);
5762                 }
5763
5764                 i = tx_ring->next_to_use;
5765
5766                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5767                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5768
5769                 /* VLAN MACLEN IPLEN */
5770                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5771                         vlan_macip_lens |=
5772                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5773                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5774                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5775                 *hdr_len += skb_network_offset(skb);
5776                 vlan_macip_lens |=
5777                     (skb_transport_header(skb) - skb_network_header(skb));
5778                 *hdr_len +=
5779                     (skb_transport_header(skb) - skb_network_header(skb));
5780                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5781                 context_desc->seqnum_seed = 0;
5782
5783                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5784                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5785                                    IXGBE_ADVTXD_DTYP_CTXT);
5786
5787                 if (skb->protocol == htons(ETH_P_IP))
5788                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5789                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5790                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5791
5792                 /* MSS L4LEN IDX */
5793                 mss_l4len_idx =
5794                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5795                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5796                 /* use index 1 for TSO */
5797                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5798                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5799
5800                 tx_buffer_info->time_stamp = jiffies;
5801                 tx_buffer_info->next_to_watch = i;
5802
5803                 i++;
5804                 if (i == tx_ring->count)
5805                         i = 0;
5806                 tx_ring->next_to_use = i;
5807
5808                 return true;
5809         }
5810         return false;
5811 }
5812
5813 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5814                           struct ixgbe_ring *tx_ring,
5815                           struct sk_buff *skb, u32 tx_flags)
5816 {
5817         struct ixgbe_adv_tx_context_desc *context_desc;
5818         unsigned int i;
5819         struct ixgbe_tx_buffer *tx_buffer_info;
5820         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5821
5822         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5823             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5824                 i = tx_ring->next_to_use;
5825                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5826                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5827
5828                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5829                         vlan_macip_lens |=
5830                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5831                 vlan_macip_lens |= (skb_network_offset(skb) <<
5832                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5833                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5834                         vlan_macip_lens |= (skb_transport_header(skb) -
5835                                             skb_network_header(skb));
5836
5837                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5838                 context_desc->seqnum_seed = 0;
5839
5840                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5841                                     IXGBE_ADVTXD_DTYP_CTXT);
5842
5843                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5844                         __be16 protocol;
5845
5846                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5847                                 const struct vlan_ethhdr *vhdr =
5848                                         (const struct vlan_ethhdr *)skb->data;
5849
5850                                 protocol = vhdr->h_vlan_encapsulated_proto;
5851                         } else {
5852                                 protocol = skb->protocol;
5853                         }
5854
5855                         switch (protocol) {
5856                         case cpu_to_be16(ETH_P_IP):
5857                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5858                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5859                                         type_tucmd_mlhl |=
5860                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5861                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5862                                         type_tucmd_mlhl |=
5863                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5864                                 break;
5865                         case cpu_to_be16(ETH_P_IPV6):
5866                                 /* XXX what about other V6 headers?? */
5867                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5868                                         type_tucmd_mlhl |=
5869                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5870                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5871                                         type_tucmd_mlhl |=
5872                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5873                                 break;
5874                         default:
5875                                 if (unlikely(net_ratelimit())) {
5876                                         e_warn(probe, "partial checksum "
5877                                                "but proto=%x!\n",
5878                                                skb->protocol);
5879                                 }
5880                                 break;
5881                         }
5882                 }
5883
5884                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5885                 /* use index zero for tx checksum offload */
5886                 context_desc->mss_l4len_idx = 0;
5887
5888                 tx_buffer_info->time_stamp = jiffies;
5889                 tx_buffer_info->next_to_watch = i;
5890
5891                 i++;
5892                 if (i == tx_ring->count)
5893                         i = 0;
5894                 tx_ring->next_to_use = i;
5895
5896                 return true;
5897         }
5898
5899         return false;
5900 }
5901
5902 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5903                         struct ixgbe_ring *tx_ring,
5904                         struct sk_buff *skb, u32 tx_flags,
5905                         unsigned int first)
5906 {
5907         struct pci_dev *pdev = adapter->pdev;
5908         struct ixgbe_tx_buffer *tx_buffer_info;
5909         unsigned int len;
5910         unsigned int total = skb->len;
5911         unsigned int offset = 0, size, count = 0, i;
5912         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5913         unsigned int f;
5914
5915         i = tx_ring->next_to_use;
5916
5917         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5918                 /* excluding fcoe_crc_eof for FCoE */
5919                 total -= sizeof(struct fcoe_crc_eof);
5920
5921         len = min(skb_headlen(skb), total);
5922         while (len) {
5923                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5924                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5925
5926                 tx_buffer_info->length = size;
5927                 tx_buffer_info->mapped_as_page = false;
5928                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5929                                                      skb->data + offset,
5930                                                      size, DMA_TO_DEVICE);
5931                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5932                         goto dma_error;
5933                 tx_buffer_info->time_stamp = jiffies;
5934                 tx_buffer_info->next_to_watch = i;
5935
5936                 len -= size;
5937                 total -= size;
5938                 offset += size;
5939                 count++;
5940
5941                 if (len) {
5942                         i++;
5943                         if (i == tx_ring->count)
5944                                 i = 0;
5945                 }
5946         }
5947
5948         for (f = 0; f < nr_frags; f++) {
5949                 struct skb_frag_struct *frag;
5950
5951                 frag = &skb_shinfo(skb)->frags[f];
5952                 len = min((unsigned int)frag->size, total);
5953                 offset = frag->page_offset;
5954
5955                 while (len) {
5956                         i++;
5957                         if (i == tx_ring->count)
5958                                 i = 0;
5959
5960                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5961                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5962
5963                         tx_buffer_info->length = size;
5964                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5965                                                            frag->page,
5966                                                            offset, size,
5967                                                            DMA_TO_DEVICE);
5968                         tx_buffer_info->mapped_as_page = true;
5969                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5970                                 goto dma_error;
5971                         tx_buffer_info->time_stamp = jiffies;
5972                         tx_buffer_info->next_to_watch = i;
5973
5974                         len -= size;
5975                         total -= size;
5976                         offset += size;
5977                         count++;
5978                 }
5979                 if (total == 0)
5980                         break;
5981         }
5982
5983         tx_ring->tx_buffer_info[i].skb = skb;
5984         tx_ring->tx_buffer_info[first].next_to_watch = i;
5985
5986         return count;
5987
5988 dma_error:
5989         e_dev_err("TX DMA map failed\n");
5990
5991         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5992         tx_buffer_info->dma = 0;
5993         tx_buffer_info->time_stamp = 0;
5994         tx_buffer_info->next_to_watch = 0;
5995         if (count)
5996                 count--;
5997
5998         /* clear timestamp and dma mappings for remaining portion of packet */
5999         while (count--) {
6000                 if (i==0)
6001                         i += tx_ring->count;
6002                 i--;
6003                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6004                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6005         }
6006
6007         return 0;
6008 }
6009
6010 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6011                            struct ixgbe_ring *tx_ring,
6012                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6013 {
6014         union ixgbe_adv_tx_desc *tx_desc = NULL;
6015         struct ixgbe_tx_buffer *tx_buffer_info;
6016         u32 olinfo_status = 0, cmd_type_len = 0;
6017         unsigned int i;
6018         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6019
6020         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6021
6022         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6023
6024         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6025                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6026
6027         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6028                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6029
6030                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6031                                  IXGBE_ADVTXD_POPTS_SHIFT;
6032
6033                 /* use index 1 context for tso */
6034                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6035                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6036                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6037                                          IXGBE_ADVTXD_POPTS_SHIFT;
6038
6039         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6040                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6041                                  IXGBE_ADVTXD_POPTS_SHIFT;
6042
6043         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6044                 olinfo_status |= IXGBE_ADVTXD_CC;
6045                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6046                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6047                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6048         }
6049
6050         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6051
6052         i = tx_ring->next_to_use;
6053         while (count--) {
6054                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6055                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6056                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6057                 tx_desc->read.cmd_type_len =
6058                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6059                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6060                 i++;
6061                 if (i == tx_ring->count)
6062                         i = 0;
6063         }
6064
6065         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6066
6067         /*
6068          * Force memory writes to complete before letting h/w
6069          * know there are new descriptors to fetch.  (Only
6070          * applicable for weak-ordered memory model archs,
6071          * such as IA-64).
6072          */
6073         wmb();
6074
6075         tx_ring->next_to_use = i;
6076         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6077 }
6078
6079 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6080                       int queue, u32 tx_flags)
6081 {
6082         struct ixgbe_atr_input atr_input;
6083         struct tcphdr *th;
6084         struct iphdr *iph = ip_hdr(skb);
6085         struct ethhdr *eth = (struct ethhdr *)skb->data;
6086         u16 vlan_id, src_port, dst_port, flex_bytes;
6087         u32 src_ipv4_addr, dst_ipv4_addr;
6088         u8 l4type = 0;
6089
6090         /* Right now, we support IPv4 only */
6091         if (skb->protocol != htons(ETH_P_IP))
6092                 return;
6093         /* check if we're UDP or TCP */
6094         if (iph->protocol == IPPROTO_TCP) {
6095                 th = tcp_hdr(skb);
6096                 src_port = th->source;
6097                 dst_port = th->dest;
6098                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6099                 /* l4type IPv4 type is 0, no need to assign */
6100         } else {
6101                 /* Unsupported L4 header, just bail here */
6102                 return;
6103         }
6104
6105         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6106
6107         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6108                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6109         src_ipv4_addr = iph->saddr;
6110         dst_ipv4_addr = iph->daddr;
6111         flex_bytes = eth->h_proto;
6112
6113         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6114         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6115         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6116         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6117         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6118         /* src and dst are inverted, think how the receiver sees them */
6119         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6120         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6121
6122         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6123         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6124 }
6125
6126 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6127                                  struct ixgbe_ring *tx_ring, int size)
6128 {
6129         netif_stop_subqueue(netdev, tx_ring->queue_index);
6130         /* Herbert's original patch had:
6131          *  smp_mb__after_netif_stop_queue();
6132          * but since that doesn't exist yet, just open code it. */
6133         smp_mb();
6134
6135         /* We need to check again in a case another CPU has just
6136          * made room available. */
6137         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6138                 return -EBUSY;
6139
6140         /* A reprieve! - use start_queue because it doesn't call schedule */
6141         netif_start_subqueue(netdev, tx_ring->queue_index);
6142         ++tx_ring->restart_queue;
6143         return 0;
6144 }
6145
6146 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6147                               struct ixgbe_ring *tx_ring, int size)
6148 {
6149         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6150                 return 0;
6151         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6152 }
6153
6154 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6155 {
6156         struct ixgbe_adapter *adapter = netdev_priv(dev);
6157         int txq = smp_processor_id();
6158
6159 #ifdef IXGBE_FCOE
6160         if ((skb->protocol == htons(ETH_P_FCOE)) ||
6161             (skb->protocol == htons(ETH_P_FIP))) {
6162                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6163                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6164                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6165                         return txq;
6166 #ifdef CONFIG_IXGBE_DCB
6167                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6168                         txq = adapter->fcoe.up;
6169                         return txq;
6170 #endif
6171                 }
6172         }
6173 #endif
6174
6175         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6176                 while (unlikely(txq >= dev->real_num_tx_queues))
6177                         txq -= dev->real_num_tx_queues;
6178                 return txq;
6179         }
6180
6181         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6182                 if (skb->priority == TC_PRIO_CONTROL)
6183                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6184                 else
6185                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6186                                >> 13;
6187                 return txq;
6188         }
6189
6190         return skb_tx_hash(dev, skb);
6191 }
6192
6193 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6194                                     struct net_device *netdev)
6195 {
6196         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6197         struct ixgbe_ring *tx_ring;
6198         struct netdev_queue *txq;
6199         unsigned int first;
6200         unsigned int tx_flags = 0;
6201         u8 hdr_len = 0;
6202         int tso;
6203         int count = 0;
6204         unsigned int f;
6205
6206         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6207                 tx_flags |= vlan_tx_tag_get(skb);
6208                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6209                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6210                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6211                 }
6212                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6213                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6214         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6215                    skb->priority != TC_PRIO_CONTROL) {
6216                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6217                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6218                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6219         }
6220
6221         tx_ring = adapter->tx_ring[skb->queue_mapping];
6222
6223 #ifdef IXGBE_FCOE
6224         /* for FCoE with DCB, we force the priority to what
6225          * was specified by the switch */
6226         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6227             (skb->protocol == htons(ETH_P_FCOE) ||
6228              skb->protocol == htons(ETH_P_FIP))) {
6229 #ifdef CONFIG_IXGBE_DCB
6230                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6231                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6232                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6233                         tx_flags |= ((adapter->fcoe.up << 13)
6234                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6235                 }
6236 #endif
6237                 /* flag for FCoE offloads */
6238                 if (skb->protocol == htons(ETH_P_FCOE))
6239                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6240         }
6241 #endif
6242
6243         /* four things can cause us to need a context descriptor */
6244         if (skb_is_gso(skb) ||
6245             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6246             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6247             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6248                 count++;
6249
6250         count += TXD_USE_COUNT(skb_headlen(skb));
6251         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6252                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6253
6254         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6255                 adapter->tx_busy++;
6256                 return NETDEV_TX_BUSY;
6257         }
6258
6259         first = tx_ring->next_to_use;
6260         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6261 #ifdef IXGBE_FCOE
6262                 /* setup tx offload for FCoE */
6263                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6264                 if (tso < 0) {
6265                         dev_kfree_skb_any(skb);
6266                         return NETDEV_TX_OK;
6267                 }
6268                 if (tso)
6269                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6270 #endif /* IXGBE_FCOE */
6271         } else {
6272                 if (skb->protocol == htons(ETH_P_IP))
6273                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6274                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6275                 if (tso < 0) {
6276                         dev_kfree_skb_any(skb);
6277                         return NETDEV_TX_OK;
6278                 }
6279
6280                 if (tso)
6281                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6282                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6283                          (skb->ip_summed == CHECKSUM_PARTIAL))
6284                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6285         }
6286
6287         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6288         if (count) {
6289                 /* add the ATR filter if ATR is on */
6290                 if (tx_ring->atr_sample_rate) {
6291                         ++tx_ring->atr_count;
6292                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6293                              test_bit(__IXGBE_FDIR_INIT_DONE,
6294                                       &tx_ring->reinit_state)) {
6295                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6296                                           tx_flags);
6297                                 tx_ring->atr_count = 0;
6298                         }
6299                 }
6300                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6301                 txq->tx_bytes += skb->len;
6302                 txq->tx_packets++;
6303                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6304                                hdr_len);
6305                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6306
6307         } else {
6308                 dev_kfree_skb_any(skb);
6309                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6310                 tx_ring->next_to_use = first;
6311         }
6312
6313         return NETDEV_TX_OK;
6314 }
6315
6316 /**
6317  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6318  * @netdev: network interface device structure
6319  * @p: pointer to an address structure
6320  *
6321  * Returns 0 on success, negative on failure
6322  **/
6323 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6324 {
6325         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6326         struct ixgbe_hw *hw = &adapter->hw;
6327         struct sockaddr *addr = p;
6328
6329         if (!is_valid_ether_addr(addr->sa_data))
6330                 return -EADDRNOTAVAIL;
6331
6332         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6333         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6334
6335         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6336                             IXGBE_RAH_AV);
6337
6338         return 0;
6339 }
6340
6341 static int
6342 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6343 {
6344         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6345         struct ixgbe_hw *hw = &adapter->hw;
6346         u16 value;
6347         int rc;
6348
6349         if (prtad != hw->phy.mdio.prtad)
6350                 return -EINVAL;
6351         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6352         if (!rc)
6353                 rc = value;
6354         return rc;
6355 }
6356
6357 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6358                             u16 addr, u16 value)
6359 {
6360         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6361         struct ixgbe_hw *hw = &adapter->hw;
6362
6363         if (prtad != hw->phy.mdio.prtad)
6364                 return -EINVAL;
6365         return hw->phy.ops.write_reg(hw, addr, devad, value);
6366 }
6367
6368 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6369 {
6370         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6371
6372         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6373 }
6374
6375 /**
6376  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6377  * netdev->dev_addrs
6378  * @netdev: network interface device structure
6379  *
6380  * Returns non-zero on failure
6381  **/
6382 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6383 {
6384         int err = 0;
6385         struct ixgbe_adapter *adapter = netdev_priv(dev);
6386         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6387
6388         if (is_valid_ether_addr(mac->san_addr)) {
6389                 rtnl_lock();
6390                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6391                 rtnl_unlock();
6392         }
6393         return err;
6394 }
6395
6396 /**
6397  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6398  * netdev->dev_addrs
6399  * @netdev: network interface device structure
6400  *
6401  * Returns non-zero on failure
6402  **/
6403 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6404 {
6405         int err = 0;
6406         struct ixgbe_adapter *adapter = netdev_priv(dev);
6407         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6408
6409         if (is_valid_ether_addr(mac->san_addr)) {
6410                 rtnl_lock();
6411                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6412                 rtnl_unlock();
6413         }
6414         return err;
6415 }
6416
6417 #ifdef CONFIG_NET_POLL_CONTROLLER
6418 /*
6419  * Polling 'interrupt' - used by things like netconsole to send skbs
6420  * without having to re-enable interrupts. It's not called while
6421  * the interrupt routine is executing.
6422  */
6423 static void ixgbe_netpoll(struct net_device *netdev)
6424 {
6425         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6426         int i;
6427
6428         /* if interface is down do nothing */
6429         if (test_bit(__IXGBE_DOWN, &adapter->state))
6430                 return;
6431
6432         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6433         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6434                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6435                 for (i = 0; i < num_q_vectors; i++) {
6436                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6437                         ixgbe_msix_clean_many(0, q_vector);
6438                 }
6439         } else {
6440                 ixgbe_intr(adapter->pdev->irq, netdev);
6441         }
6442         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6443 }
6444 #endif
6445
6446 static const struct net_device_ops ixgbe_netdev_ops = {
6447         .ndo_open               = ixgbe_open,
6448         .ndo_stop               = ixgbe_close,
6449         .ndo_start_xmit         = ixgbe_xmit_frame,
6450         .ndo_select_queue       = ixgbe_select_queue,
6451         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6452         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6453         .ndo_validate_addr      = eth_validate_addr,
6454         .ndo_set_mac_address    = ixgbe_set_mac,
6455         .ndo_change_mtu         = ixgbe_change_mtu,
6456         .ndo_tx_timeout         = ixgbe_tx_timeout,
6457         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6458         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6459         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6460         .ndo_do_ioctl           = ixgbe_ioctl,
6461         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6462         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6463         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6464         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6465 #ifdef CONFIG_NET_POLL_CONTROLLER
6466         .ndo_poll_controller    = ixgbe_netpoll,
6467 #endif
6468 #ifdef IXGBE_FCOE
6469         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6470         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6471         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6472         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6473         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6474 #endif /* IXGBE_FCOE */
6475 };
6476
6477 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6478                            const struct ixgbe_info *ii)
6479 {
6480 #ifdef CONFIG_PCI_IOV
6481         struct ixgbe_hw *hw = &adapter->hw;
6482         int err;
6483
6484         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6485                 return;
6486
6487         /* The 82599 supports up to 64 VFs per physical function
6488          * but this implementation limits allocation to 63 so that
6489          * basic networking resources are still available to the
6490          * physical function
6491          */
6492         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6493         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6494         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6495         if (err) {
6496                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6497                 goto err_novfs;
6498         }
6499         /* If call to enable VFs succeeded then allocate memory
6500          * for per VF control structures.
6501          */
6502         adapter->vfinfo =
6503                 kcalloc(adapter->num_vfs,
6504                         sizeof(struct vf_data_storage), GFP_KERNEL);
6505         if (adapter->vfinfo) {
6506                 /* Now that we're sure SR-IOV is enabled
6507                  * and memory allocated set up the mailbox parameters
6508                  */
6509                 ixgbe_init_mbx_params_pf(hw);
6510                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6511                        sizeof(hw->mbx.ops));
6512
6513                 /* Disable RSC when in SR-IOV mode */
6514                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6515                                      IXGBE_FLAG2_RSC_ENABLED);
6516                 return;
6517         }
6518
6519         /* Oh oh */
6520         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6521               "SRIOV disabled\n");
6522         pci_disable_sriov(adapter->pdev);
6523
6524 err_novfs:
6525         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6526         adapter->num_vfs = 0;
6527 #endif /* CONFIG_PCI_IOV */
6528 }
6529
6530 /**
6531  * ixgbe_probe - Device Initialization Routine
6532  * @pdev: PCI device information struct
6533  * @ent: entry in ixgbe_pci_tbl
6534  *
6535  * Returns 0 on success, negative on failure
6536  *
6537  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6538  * The OS initialization, configuring of the adapter private structure,
6539  * and a hardware reset occur.
6540  **/
6541 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6542                                  const struct pci_device_id *ent)
6543 {
6544         struct net_device *netdev;
6545         struct ixgbe_adapter *adapter = NULL;
6546         struct ixgbe_hw *hw;
6547         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6548         static int cards_found;
6549         int i, err, pci_using_dac;
6550         unsigned int indices = num_possible_cpus();
6551 #ifdef IXGBE_FCOE
6552         u16 device_caps;
6553 #endif
6554         u32 part_num, eec;
6555
6556         /* Catch broken hardware that put the wrong VF device ID in
6557          * the PCIe SR-IOV capability.
6558          */
6559         if (pdev->is_virtfn) {
6560                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6561                      pci_name(pdev), pdev->vendor, pdev->device);
6562                 return -EINVAL;
6563         }
6564
6565         err = pci_enable_device_mem(pdev);
6566         if (err)
6567                 return err;
6568
6569         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6570             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6571                 pci_using_dac = 1;
6572         } else {
6573                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6574                 if (err) {
6575                         err = dma_set_coherent_mask(&pdev->dev,
6576                                                     DMA_BIT_MASK(32));
6577                         if (err) {
6578                                 dev_err(&pdev->dev,
6579                                         "No usable DMA configuration, aborting\n");
6580                                 goto err_dma;
6581                         }
6582                 }
6583                 pci_using_dac = 0;
6584         }
6585
6586         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6587                                            IORESOURCE_MEM), ixgbe_driver_name);
6588         if (err) {
6589                 dev_err(&pdev->dev,
6590                         "pci_request_selected_regions failed 0x%x\n", err);
6591                 goto err_pci_reg;
6592         }
6593
6594         pci_enable_pcie_error_reporting(pdev);
6595
6596         pci_set_master(pdev);
6597         pci_save_state(pdev);
6598
6599         if (ii->mac == ixgbe_mac_82598EB)
6600                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6601         else
6602                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6603
6604         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6605 #ifdef IXGBE_FCOE
6606         indices += min_t(unsigned int, num_possible_cpus(),
6607                          IXGBE_MAX_FCOE_INDICES);
6608 #endif
6609         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6610         if (!netdev) {
6611                 err = -ENOMEM;
6612                 goto err_alloc_etherdev;
6613         }
6614
6615         SET_NETDEV_DEV(netdev, &pdev->dev);
6616
6617         pci_set_drvdata(pdev, netdev);
6618         adapter = netdev_priv(netdev);
6619
6620         adapter->netdev = netdev;
6621         adapter->pdev = pdev;
6622         hw = &adapter->hw;
6623         hw->back = adapter;
6624         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6625
6626         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6627                               pci_resource_len(pdev, 0));
6628         if (!hw->hw_addr) {
6629                 err = -EIO;
6630                 goto err_ioremap;
6631         }
6632
6633         for (i = 1; i <= 5; i++) {
6634                 if (pci_resource_len(pdev, i) == 0)
6635                         continue;
6636         }
6637
6638         netdev->netdev_ops = &ixgbe_netdev_ops;
6639         ixgbe_set_ethtool_ops(netdev);
6640         netdev->watchdog_timeo = 5 * HZ;
6641         strcpy(netdev->name, pci_name(pdev));
6642
6643         adapter->bd_number = cards_found;
6644
6645         /* Setup hw api */
6646         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6647         hw->mac.type  = ii->mac;
6648
6649         /* EEPROM */
6650         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6651         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6652         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6653         if (!(eec & (1 << 8)))
6654                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6655
6656         /* PHY */
6657         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6658         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6659         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6660         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6661         hw->phy.mdio.mmds = 0;
6662         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6663         hw->phy.mdio.dev = netdev;
6664         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6665         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6666
6667         /* set up this timer and work struct before calling get_invariants
6668          * which might start the timer
6669          */
6670         init_timer(&adapter->sfp_timer);
6671         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6672         adapter->sfp_timer.data = (unsigned long) adapter;
6673
6674         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6675
6676         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6677         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6678
6679         /* a new SFP+ module arrival, called from GPI SDP2 context */
6680         INIT_WORK(&adapter->sfp_config_module_task,
6681                   ixgbe_sfp_config_module_task);
6682
6683         ii->get_invariants(hw);
6684
6685         /* setup the private structure */
6686         err = ixgbe_sw_init(adapter);
6687         if (err)
6688                 goto err_sw_init;
6689
6690         /* Make it possible the adapter to be woken up via WOL */
6691         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6692                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6693
6694         /*
6695          * If there is a fan on this device and it has failed log the
6696          * failure.
6697          */
6698         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6699                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6700                 if (esdp & IXGBE_ESDP_SDP1)
6701                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6702         }
6703
6704         /* reset_hw fills in the perm_addr as well */
6705         hw->phy.reset_if_overtemp = true;
6706         err = hw->mac.ops.reset_hw(hw);
6707         hw->phy.reset_if_overtemp = false;
6708         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6709             hw->mac.type == ixgbe_mac_82598EB) {
6710                 /*
6711                  * Start a kernel thread to watch for a module to arrive.
6712                  * Only do this for 82598, since 82599 will generate
6713                  * interrupts on module arrival.
6714                  */
6715                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6716                 mod_timer(&adapter->sfp_timer,
6717                           round_jiffies(jiffies + (2 * HZ)));
6718                 err = 0;
6719         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6720                 e_dev_err("failed to initialize because an unsupported SFP+ "
6721                           "module type was detected.\n");
6722                 e_dev_err("Reload the driver after installing a supported "
6723                           "module.\n");
6724                 goto err_sw_init;
6725         } else if (err) {
6726                 e_dev_err("HW Init failed: %d\n", err);
6727                 goto err_sw_init;
6728         }
6729
6730         ixgbe_probe_vf(adapter, ii);
6731
6732         netdev->features = NETIF_F_SG |
6733                            NETIF_F_IP_CSUM |
6734                            NETIF_F_HW_VLAN_TX |
6735                            NETIF_F_HW_VLAN_RX |
6736                            NETIF_F_HW_VLAN_FILTER;
6737
6738         netdev->features |= NETIF_F_IPV6_CSUM;
6739         netdev->features |= NETIF_F_TSO;
6740         netdev->features |= NETIF_F_TSO6;
6741         netdev->features |= NETIF_F_GRO;
6742
6743         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6744                 netdev->features |= NETIF_F_SCTP_CSUM;
6745
6746         netdev->vlan_features |= NETIF_F_TSO;
6747         netdev->vlan_features |= NETIF_F_TSO6;
6748         netdev->vlan_features |= NETIF_F_IP_CSUM;
6749         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6750         netdev->vlan_features |= NETIF_F_SG;
6751
6752         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6753                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6754                                     IXGBE_FLAG_DCB_ENABLED);
6755         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6756                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6757
6758 #ifdef CONFIG_IXGBE_DCB
6759         netdev->dcbnl_ops = &dcbnl_ops;
6760 #endif
6761
6762 #ifdef IXGBE_FCOE
6763         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6764                 if (hw->mac.ops.get_device_caps) {
6765                         hw->mac.ops.get_device_caps(hw, &device_caps);
6766                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6767                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6768                 }
6769         }
6770         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6771                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6772                 netdev->vlan_features |= NETIF_F_FSO;
6773                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6774         }
6775 #endif /* IXGBE_FCOE */
6776         if (pci_using_dac)
6777                 netdev->features |= NETIF_F_HIGHDMA;
6778
6779         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6780                 netdev->features |= NETIF_F_LRO;
6781
6782         /* make sure the EEPROM is good */
6783         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6784                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6785                 err = -EIO;
6786                 goto err_eeprom;
6787         }
6788
6789         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6790         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6791
6792         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6793                 e_dev_err("invalid MAC address\n");
6794                 err = -EIO;
6795                 goto err_eeprom;
6796         }
6797
6798         /* power down the optics */
6799         if (hw->phy.multispeed_fiber)
6800                 hw->mac.ops.disable_tx_laser(hw);
6801
6802         init_timer(&adapter->watchdog_timer);
6803         adapter->watchdog_timer.function = &ixgbe_watchdog;
6804         adapter->watchdog_timer.data = (unsigned long)adapter;
6805
6806         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6807         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6808
6809         err = ixgbe_init_interrupt_scheme(adapter);
6810         if (err)
6811                 goto err_sw_init;
6812
6813         switch (pdev->device) {
6814         case IXGBE_DEV_ID_82599_KX4:
6815                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6816                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6817                 break;
6818         default:
6819                 adapter->wol = 0;
6820                 break;
6821         }
6822         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6823
6824         /* pick up the PCI bus settings for reporting later */
6825         hw->mac.ops.get_bus_info(hw);
6826
6827         /* print bus type/speed/width info */
6828         e_dev_info("(PCI Express:%s:%s) %pM\n",
6829                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6830                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6831                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6832                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6833                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6834                  "Unknown"),
6835                 netdev->dev_addr);
6836         ixgbe_read_pba_num_generic(hw, &part_num);
6837         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6838                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6839                            "PBA No: %06x-%03x\n",
6840                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6841                            (part_num >> 8), (part_num & 0xff));
6842         else
6843                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6844                            hw->mac.type, hw->phy.type,
6845                            (part_num >> 8), (part_num & 0xff));
6846
6847         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6848                 e_dev_warn("PCI-Express bandwidth available for this card is "
6849                            "not sufficient for optimal performance.\n");
6850                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6851                            "is required.\n");
6852         }
6853
6854         /* save off EEPROM version number */
6855         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6856
6857         /* reset the hardware with the new settings */
6858         err = hw->mac.ops.start_hw(hw);
6859
6860         if (err == IXGBE_ERR_EEPROM_VERSION) {
6861                 /* We are running on a pre-production device, log a warning */
6862                 e_dev_warn("This device is a pre-production adapter/LOM. "
6863                            "Please be aware there may be issues associated "
6864                            "with your hardware.  If you are experiencing "
6865                            "problems please contact your Intel or hardware "
6866                            "representative who provided you with this "
6867                            "hardware.\n");
6868         }
6869         strcpy(netdev->name, "eth%d");
6870         err = register_netdev(netdev);
6871         if (err)
6872                 goto err_register;
6873
6874         /* carrier off reporting is important to ethtool even BEFORE open */
6875         netif_carrier_off(netdev);
6876
6877         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6878             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6879                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6880
6881         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6882                 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6883 #ifdef CONFIG_IXGBE_DCA
6884         if (dca_add_requester(&pdev->dev) == 0) {
6885                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6886                 ixgbe_setup_dca(adapter);
6887         }
6888 #endif
6889         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6890                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6891                 for (i = 0; i < adapter->num_vfs; i++)
6892                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6893         }
6894
6895         /* add san mac addr to netdev */
6896         ixgbe_add_sanmac_netdev(netdev);
6897
6898         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6899         cards_found++;
6900         return 0;
6901
6902 err_register:
6903         ixgbe_release_hw_control(adapter);
6904         ixgbe_clear_interrupt_scheme(adapter);
6905 err_sw_init:
6906 err_eeprom:
6907         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6908                 ixgbe_disable_sriov(adapter);
6909         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6910         del_timer_sync(&adapter->sfp_timer);
6911         cancel_work_sync(&adapter->sfp_task);
6912         cancel_work_sync(&adapter->multispeed_fiber_task);
6913         cancel_work_sync(&adapter->sfp_config_module_task);
6914         iounmap(hw->hw_addr);
6915 err_ioremap:
6916         free_netdev(netdev);
6917 err_alloc_etherdev:
6918         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6919                                      IORESOURCE_MEM));
6920 err_pci_reg:
6921 err_dma:
6922         pci_disable_device(pdev);
6923         return err;
6924 }
6925
6926 /**
6927  * ixgbe_remove - Device Removal Routine
6928  * @pdev: PCI device information struct
6929  *
6930  * ixgbe_remove is called by the PCI subsystem to alert the driver
6931  * that it should release a PCI device.  The could be caused by a
6932  * Hot-Plug event, or because the driver is going to be removed from
6933  * memory.
6934  **/
6935 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6936 {
6937         struct net_device *netdev = pci_get_drvdata(pdev);
6938         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6939
6940         set_bit(__IXGBE_DOWN, &adapter->state);
6941         /* clear the module not found bit to make sure the worker won't
6942          * reschedule
6943          */
6944         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6945         del_timer_sync(&adapter->watchdog_timer);
6946
6947         del_timer_sync(&adapter->sfp_timer);
6948         cancel_work_sync(&adapter->watchdog_task);
6949         cancel_work_sync(&adapter->sfp_task);
6950         cancel_work_sync(&adapter->multispeed_fiber_task);
6951         cancel_work_sync(&adapter->sfp_config_module_task);
6952         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6953             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6954                 cancel_work_sync(&adapter->fdir_reinit_task);
6955         flush_scheduled_work();
6956
6957 #ifdef CONFIG_IXGBE_DCA
6958         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6959                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6960                 dca_remove_requester(&pdev->dev);
6961                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6962         }
6963
6964 #endif
6965 #ifdef IXGBE_FCOE
6966         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6967                 ixgbe_cleanup_fcoe(adapter);
6968
6969 #endif /* IXGBE_FCOE */
6970
6971         /* remove the added san mac */
6972         ixgbe_del_sanmac_netdev(netdev);
6973
6974         if (netdev->reg_state == NETREG_REGISTERED)
6975                 unregister_netdev(netdev);
6976
6977         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6978                 ixgbe_disable_sriov(adapter);
6979
6980         ixgbe_clear_interrupt_scheme(adapter);
6981
6982         ixgbe_release_hw_control(adapter);
6983
6984         iounmap(adapter->hw.hw_addr);
6985         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6986                                      IORESOURCE_MEM));
6987
6988         e_dev_info("complete\n");
6989
6990         free_netdev(netdev);
6991
6992         pci_disable_pcie_error_reporting(pdev);
6993
6994         pci_disable_device(pdev);
6995 }
6996
6997 /**
6998  * ixgbe_io_error_detected - called when PCI error is detected
6999  * @pdev: Pointer to PCI device
7000  * @state: The current pci connection state
7001  *
7002  * This function is called after a PCI bus error affecting
7003  * this device has been detected.
7004  */
7005 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7006                                                 pci_channel_state_t state)
7007 {
7008         struct net_device *netdev = pci_get_drvdata(pdev);
7009         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7010
7011         netif_device_detach(netdev);
7012
7013         if (state == pci_channel_io_perm_failure)
7014                 return PCI_ERS_RESULT_DISCONNECT;
7015
7016         if (netif_running(netdev))
7017                 ixgbe_down(adapter);
7018         pci_disable_device(pdev);
7019
7020         /* Request a slot reset. */
7021         return PCI_ERS_RESULT_NEED_RESET;
7022 }
7023
7024 /**
7025  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7026  * @pdev: Pointer to PCI device
7027  *
7028  * Restart the card from scratch, as if from a cold-boot.
7029  */
7030 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7031 {
7032         struct net_device *netdev = pci_get_drvdata(pdev);
7033         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7034         pci_ers_result_t result;
7035         int err;
7036
7037         if (pci_enable_device_mem(pdev)) {
7038                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7039                 result = PCI_ERS_RESULT_DISCONNECT;
7040         } else {
7041                 pci_set_master(pdev);
7042                 pci_restore_state(pdev);
7043                 pci_save_state(pdev);
7044
7045                 pci_wake_from_d3(pdev, false);
7046
7047                 ixgbe_reset(adapter);
7048                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7049                 result = PCI_ERS_RESULT_RECOVERED;
7050         }
7051
7052         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7053         if (err) {
7054                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7055                           "failed 0x%0x\n", err);
7056                 /* non-fatal, continue */
7057         }
7058
7059         return result;
7060 }
7061
7062 /**
7063  * ixgbe_io_resume - called when traffic can start flowing again.
7064  * @pdev: Pointer to PCI device
7065  *
7066  * This callback is called when the error recovery driver tells us that
7067  * its OK to resume normal operation.
7068  */
7069 static void ixgbe_io_resume(struct pci_dev *pdev)
7070 {
7071         struct net_device *netdev = pci_get_drvdata(pdev);
7072         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7073
7074         if (netif_running(netdev)) {
7075                 if (ixgbe_up(adapter)) {
7076                         e_info(probe, "ixgbe_up failed after reset\n");
7077                         return;
7078                 }
7079         }
7080
7081         netif_device_attach(netdev);
7082 }
7083
7084 static struct pci_error_handlers ixgbe_err_handler = {
7085         .error_detected = ixgbe_io_error_detected,
7086         .slot_reset = ixgbe_io_slot_reset,
7087         .resume = ixgbe_io_resume,
7088 };
7089
7090 static struct pci_driver ixgbe_driver = {
7091         .name     = ixgbe_driver_name,
7092         .id_table = ixgbe_pci_tbl,
7093         .probe    = ixgbe_probe,
7094         .remove   = __devexit_p(ixgbe_remove),
7095 #ifdef CONFIG_PM
7096         .suspend  = ixgbe_suspend,
7097         .resume   = ixgbe_resume,
7098 #endif
7099         .shutdown = ixgbe_shutdown,
7100         .err_handler = &ixgbe_err_handler
7101 };
7102
7103 /**
7104  * ixgbe_init_module - Driver Registration Routine
7105  *
7106  * ixgbe_init_module is the first routine called when the driver is
7107  * loaded. All it does is register with the PCI subsystem.
7108  **/
7109 static int __init ixgbe_init_module(void)
7110 {
7111         int ret;
7112         pr_info("%s - version %s\n", ixgbe_driver_string,
7113                    ixgbe_driver_version);
7114         pr_info("%s\n", ixgbe_copyright);
7115
7116 #ifdef CONFIG_IXGBE_DCA
7117         dca_register_notify(&dca_notifier);
7118 #endif
7119
7120         ret = pci_register_driver(&ixgbe_driver);
7121         return ret;
7122 }
7123
7124 module_init(ixgbe_init_module);
7125
7126 /**
7127  * ixgbe_exit_module - Driver Exit Cleanup Routine
7128  *
7129  * ixgbe_exit_module is called just before the driver is removed
7130  * from memory.
7131  **/
7132 static void __exit ixgbe_exit_module(void)
7133 {
7134 #ifdef CONFIG_IXGBE_DCA
7135         dca_unregister_notify(&dca_notifier);
7136 #endif
7137         pci_unregister_driver(&ixgbe_driver);
7138 }
7139
7140 #ifdef CONFIG_IXGBE_DCA
7141 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7142                             void *p)
7143 {
7144         int ret_val;
7145
7146         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7147                                          __ixgbe_notify_dca);
7148
7149         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7150 }
7151
7152 #endif /* CONFIG_IXGBE_DCA */
7153
7154 /**
7155  * ixgbe_get_hw_dev return device
7156  * used by hardware layer to print debugging information
7157  **/
7158 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7159 {
7160         struct ixgbe_adapter *adapter = hw->back;
7161         return adapter->netdev;
7162 }
7163
7164 module_exit(ixgbe_exit_module);
7165
7166 /* ixgbe_main.c */