drivers/net/inca-ip_sw.c

   1 /*
   2  * INCA-IP internal switch ethernet driver.
   3  *
   4  * (C) Copyright 2003-2004
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26
  27 #include <common.h>
  28
  29 #include <malloc.h>
  30 #include <net.h>
  31 #include <asm/inca-ip.h>
  32 #include <asm/addrspace.h>
  33
  34
  35 #define NUM_RX_DESC     PKTBUFSRX
  36 #define NUM_TX_DESC     3
  37 #define TOUT_LOOP       1000000
  38
  39
  40 #define DELAY   udelay(10000)
  41   /* Sometimes the store word instruction hangs while writing to one
  42    * of the Switch registers. Moving the instruction into a separate
  43    * function somehow makes the problem go away.
  44    */
  45 static void SWORD(volatile u32 * reg, u32 value)
  46 {
  47         *reg = value;
  48 }
  49
  50 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
  51 #define DMA_READ_REG(reg, value)    value = (u32)*((volatile u32*)reg)
  52 #define SW_WRITE_REG(reg, value)   \
  53         SWORD(reg, value);\
  54         DELAY;\
  55         SWORD(reg, value);
  56
  57 #define SW_READ_REG(reg, value)    \
  58         value = (u32)*((volatile u32*)reg);\
  59         DELAY;\
  60         value = (u32)*((volatile u32*)reg);
  61
  62 #define INCA_DMA_TX_POLLING_TIME        0x07
  63 #define INCA_DMA_RX_POLLING_TIME        0x07
  64
  65 #define INCA_DMA_TX_HOLD                0x80000000
  66 #define INCA_DMA_TX_EOP                 0x40000000
  67 #define INCA_DMA_TX_SOP                 0x20000000
  68 #define INCA_DMA_TX_ICPT                0x10000000
  69 #define INCA_DMA_TX_IEOP                0x08000000
  70
  71 #define INCA_DMA_RX_C                   0x80000000
  72 #define INCA_DMA_RX_SOP                 0x40000000
  73 #define INCA_DMA_RX_EOP                 0x20000000
  74
  75 #define INCA_SWITCH_PHY_SPEED_10H       0x1
  76 #define INCA_SWITCH_PHY_SPEED_10F       0x5
  77 #define INCA_SWITCH_PHY_SPEED_100H      0x2
  78 #define INCA_SWITCH_PHY_SPEED_100F      0x6
  79
  80 /************************ Auto MDIX settings ************************/
  81 #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR         INCA_IP_Ports_P1_DIR
  82 #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL      INCA_IP_Ports_P1_ALTSEL
  83 #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT         INCA_IP_Ports_P1_OUT
  84 #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX     16
  85
  86 #define WAIT_SIGNAL_RETRIES                     100
  87 #define WAIT_LINK_RETRIES                       100
  88 #define LINK_RETRY_DELAY                        2000  /* ms */
  89 /********************************************************************/
  90
  91 typedef struct
  92 {
  93         union {
  94                 struct {
  95                         volatile u32 HOLD               :1;
  96                         volatile u32 ICpt               :1;
  97                         volatile u32 IEop               :1;
  98                         volatile u32 offset             :3;
  99                         volatile u32 reserved0          :4;
 100                         volatile u32 NFB                :22;
 101                 }field;
 102
 103                 volatile u32 word;
 104         }params;
 105
 106         volatile u32 nextRxDescPtr;
 107
 108         volatile u32 RxDataPtr;
 109
 110         union {
 111                 struct {
 112                         volatile u32 C                  :1;
 113                         volatile u32 Sop                :1;
 114                         volatile u32 Eop                :1;
 115                         volatile u32 reserved3          :12;
 116                         volatile u32 NBT                :17;
 117                 }field;
 118
 119                 volatile u32 word;
 120         }status;
 121
 122 } inca_rx_descriptor_t;
 123
 124
 125 typedef struct
 126 {
 127         union {
 128                 struct {
 129                         volatile u32 HOLD               :1;
 130                         volatile u32 Eop                :1;
 131                         volatile u32 Sop                :1;
 132                         volatile u32 ICpt               :1;
 133                         volatile u32 IEop               :1;
 134                         volatile u32 reserved0          :5;
 135                         volatile u32 NBA                :22;
 136                 }field;
 137
 138                 volatile u32 word;
 139         }params;
 140
 141         volatile u32 nextTxDescPtr;
 142
 143         volatile u32 TxDataPtr;
 144
 145         volatile u32 C                  :1;
 146         volatile u32 reserved3          :31;
 147
 148 } inca_tx_descriptor_t;
 149
 150
 151 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
 152 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
 153
 154 static int tx_new, rx_new, tx_hold, rx_hold;
 155 static int tx_old_hold = -1;
 156 static int initialized  = 0;
 157
 158
 159 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
 160 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
 161 static int inca_switch_recv(struct eth_device *dev);
 162 static void inca_switch_halt(struct eth_device *dev);
 163 static void inca_init_switch_chip(void);
 164 static void inca_dma_init(void);
 165 static int inca_amdix(void);
 166
 167
 168 int inca_switch_initialize(bd_t * bis)
 169 {
 170         struct eth_device *dev;
 171
 172 #if 0
 173         printf("Entered inca_switch_initialize()\n");
 174 #endif
 175
 176         if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
 177                 printf("Failed to allocate memory\n");
 178                 return 0;
 179         }
 180         memset(dev, 0, sizeof(*dev));
 181
 182         inca_dma_init();
 183
 184         inca_init_switch_chip();
 185
 186 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
 187         inca_amdix();
 188 #endif
 189
 190         sprintf(dev->name, "INCA-IP Switch");
 191         dev->init = inca_switch_init;
 192         dev->halt = inca_switch_halt;
 193         dev->send = inca_switch_send;
 194         dev->recv = inca_switch_recv;
 195
 196         eth_register(dev);
 197
 198 #if 0
 199         printf("Leaving inca_switch_initialize()\n");
 200 #endif
 201
 202         return 1;
 203 }
 204
 205
 206 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 207 {
 208         int i;
 209         u32 v, regValue;
 210         u16 wTmp;
 211
 212 #if 0
 213         printf("Entering inca_switch_init()\n");
 214 #endif
 215
 216         /* Set MAC address.
 217          */
 218         wTmp = (u16)dev->enetaddr[0];
 219         regValue = (wTmp << 8) | dev->enetaddr[1];
 220
 221         SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
 222
 223         wTmp = (u16)dev->enetaddr[2];
 224         regValue = (wTmp << 8) | dev->enetaddr[3];
 225         regValue = regValue << 16;
 226         wTmp = (u16)dev->enetaddr[4];
 227         regValue |= (wTmp<<8) | dev->enetaddr[5];
 228
 229         SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
 230
 231         /* Initialize the descriptor rings.
 232          */
 233         for (i = 0; i < NUM_RX_DESC; i++) {
 234                 inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
 235                 memset(rx_desc, 0, sizeof(rx_ring[i]));
 236
 237                 /* Set maximum size of receive buffer.
 238                  */
 239                 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
 240
 241                 /* Set the offset of the receive buffer. Zero means
 242                  * that the offset mechanism is not used.
 243                  */
 244                 rx_desc->params.field.offset = 0;
 245
 246                 /* Check if it is the last descriptor.
 247                  */
 248                 if (i == (NUM_RX_DESC - 1)) {
 249                         /* Let the last descriptor point to the first
 250                          * one.
 251                          */
 252                         rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
 253                 } else {
 254                         /* Set the address of the next descriptor.
 255                          */
 256                         rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
 257                 }
 258
 259                 rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
 260         }
 261
 262 #if 0
 263         printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
 264         printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
 265 #endif
 266
 267         for (i = 0; i < NUM_TX_DESC; i++) {
 268                 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
 269
 270                 memset(tx_desc, 0, sizeof(tx_ring[i]));
 271
 272                 tx_desc->params.word       = 0;
 273                 tx_desc->params.field.HOLD = 1;
 274                 tx_desc->C                 = 1;
 275
 276                         /* Check if it is the last descriptor.
 277                          */
 278                 if (i == (NUM_TX_DESC - 1)) {
 279                                 /* Let the last descriptor point to the
 280                                  * first one.
 281                                  */
 282                         tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
 283                 } else {
 284                                 /* Set the address of the next descriptor.
 285                                  */
 286                         tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
 287                 }
 288         }
 289
 290         /* Initialize RxDMA.
 291          */
 292         DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
 293 #if 0
 294         printf("RX status = 0x%08X\n", v);
 295 #endif
 296
 297         /* Writing to the FRDA of CHANNEL.
 298          */
 299         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
 300
 301         /* Writing to the COMMAND REG.
 302          */
 303         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
 304
 305         /* Initialize TxDMA.
 306          */
 307         DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
 308 #if 0
 309         printf("TX status = 0x%08X\n", v);
 310 #endif
 311
 312         /* Writing to the FRDA of CHANNEL.
 313          */
 314         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
 315
 316         tx_new = rx_new = 0;
 317
 318         tx_hold = NUM_TX_DESC - 1;
 319         rx_hold = NUM_RX_DESC - 1;
 320
 321 #if 0
 322         rx_ring[rx_hold].params.field.HOLD = 1;
 323 #endif
 324         /* enable spanning tree forwarding, enable the CPU port */
 325         /* ST_PT:
 326          *      CPS (CPU port status)   0x3 (forwarding)
 327          *      LPS (LAN port status)   0x3 (forwarding)
 328          *      PPS (PC port status)    0x3 (forwarding)
 329          */
 330         SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
 331
 332 #if 0
 333         printf("Leaving inca_switch_init()\n");
 334 #endif
 335
 336         return 0;
 337 }
 338
 339
 340 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
 341 {
 342         int                    i;
 343         int                    res      = -1;
 344         u32                    command;
 345         u32                    regValue;
 346         inca_tx_descriptor_t * tx_desc  = KSEG1ADDR(&tx_ring[tx_new]);
 347
 348 #if 0
 349         printf("Entered inca_switch_send()\n");
 350 #endif
 351
 352         if (length <= 0) {
 353                 printf ("%s: bad packet size: %d\n", dev->name, length);
 354                 goto Done;
 355         }
 356
 357         for(i = 0; tx_desc->C == 0; i++) {
 358                 if (i >= TOUT_LOOP) {
 359                         printf("%s: tx error buffer not ready\n", dev->name);
 360                         goto Done;
 361                 }
 362         }
 363
 364         if (tx_old_hold >= 0) {
 365                 KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
 366         }
 367         tx_old_hold = tx_hold;
 368
 369         tx_desc->params.word =
 370                         (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
 371
 372         tx_desc->C = 0;
 373         tx_desc->TxDataPtr = (u32)packet;
 374         tx_desc->params.field.NBA = length;
 375
 376         KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
 377
 378         tx_hold = tx_new;
 379         tx_new  = (tx_new + 1) % NUM_TX_DESC;
 380
 381
 382         if (! initialized) {
 383                 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
 384                 initialized = 1;
 385         } else {
 386                 command = INCA_IP_DMA_DMA_TXCCR0_HR;
 387         }
 388
 389         DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
 390         regValue |= command;
 391 #if 0
 392         printf("regValue = 0x%x\n", regValue);
 393 #endif
 394         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
 395
 396 #if 1
 397         for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
 398                 if (i >= TOUT_LOOP) {
 399                         printf("%s: tx buffer not ready\n", dev->name);
 400                         goto Done;
 401                 }
 402         }
 403 #endif
 404         res = length;
 405 Done:
 406 #if 0
 407         printf("Leaving inca_switch_send()\n");
 408 #endif
 409         return res;
 410 }
 411
 412
 413 static int inca_switch_recv(struct eth_device *dev)
 414 {
 415         int                    length  = 0;
 416         inca_rx_descriptor_t * rx_desc;
 417
 418 #if 0
 419         printf("Entered inca_switch_recv()\n");
 420 #endif
 421
 422         for (;;) {
 423                 rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
 424
 425                 if (rx_desc->status.field.C == 0) {
 426                         break;
 427                 }
 428
 429 #if 0
 430                 rx_ring[rx_new].params.field.HOLD = 1;
 431 #endif
 432
 433                 if (! rx_desc->status.field.Eop) {
 434                         printf("Partly received packet!!!\n");
 435                         break;
 436                 }
 437
 438                 length = rx_desc->status.field.NBT;
 439                 rx_desc->status.word &=
 440                          ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
 441 #if 0
 442 {
 443   int i;
 444   for (i=0;i<length - 4;i++) {
 445     if (i % 16 == 0) printf("\n%04x: ", i);
 446     printf("%02X ", NetRxPackets[rx_new][i]);
 447   }
 448   printf("\n");
 449 }
 450 #endif
 451
 452                 if (length) {
 453 #if 0
 454                         printf("Received %d bytes\n", length);
 455 #endif
 456                         NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
 457                 } else {
 458 #if 1
 459                         printf("Zero length!!!\n");
 460 #endif
 461                 }
 462
 463
 464                 KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
 465
 466                 rx_hold = rx_new;
 467
 468                 rx_new = (rx_new + 1) % NUM_RX_DESC;
 469         }
 470
 471 #if 0
 472         printf("Leaving inca_switch_recv()\n");
 473 #endif
 474
 475         return length;
 476 }
 477
 478
 479 static void inca_switch_halt(struct eth_device *dev)
 480 {
 481 #if 0
 482         printf("Entered inca_switch_halt()\n");
 483 #endif
 484
 485 #if 1
 486         initialized = 0;
 487 #endif
 488 #if 1
 489         /* Disable forwarding to the CPU port.
 490          */
 491         SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
 492
 493         /* Close RxDMA channel.
 494          */
 495         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
 496
 497         /* Close TxDMA channel.
 498          */
 499         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
 500
 501
 502 #endif
 503 #if 0
 504         printf("Leaving inca_switch_halt()\n");
 505 #endif
 506 }
 507
 508
 509 static void inca_init_switch_chip(void)
 510 {
 511         u32 regValue;
 512
 513         /* To workaround a problem with collision counter
 514          * (see Errata sheet).
 515          */
 516         SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
 517         SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
 518
 519 #if 1
 520         /* init MDIO configuration:
 521          *      MDS (Poll speed):       0x01 (4ms)
 522          *      PHY_LAN_ADDR:           0x06
 523          *      PHY_PC_ADDR:            0x05
 524          *      UEP (Use External PHY): 0x00 (Internal PHY is used)
 525          *      PS (Port Select):       0x00 (PT/UMM for LAN)
 526          *      PT (PHY Test):          0x00 (no test mode)
 527          *      UMM (Use MDIO Mode):    0x00 (state machine is disabled)
 528          */
 529         SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
 530
 531         /* init PHY:
 532          *      SL (Auto Neg. Speed for LAN)
 533          *      SP (Auto Neg. Speed for PC)
 534          *      LL (Link Status for LAN)
 535          *      LP (Link Status for PC)
 536          *      DL (Duplex Status for LAN)
 537          *      DP (Duplex Status for PC)
 538          *      PL (Auto Neg. Pause Status for LAN)
 539          *      PP (Auto Neg. Pause Status for PC)
 540          */
 541         SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
 542
 543         /* MDIO_ACC:
 544          *      RA (Request/Ack)  0x01 (Request)
 545          *      RW (Read/Write)   0x01 (Write)
 546          *      PHY_ADDR          0x05 (PC)
 547          *      REG_ADDR          0x00 (PHY_BCR: basic control register)
 548          *      PHY_DATA          0x8000
 549          *                    Reset                   - software reset
 550          *                    LB (loop back)          - normal
 551          *                    SS (speed select)       - 10 Mbit/s
 552          *                    ANE (auto neg. enable)  - enable
 553          *                    PD (power down)         - normal
 554          *                    ISO (isolate)           - normal
 555          *                    RAN (restart auto neg.) - normal
 556          *                    DM (duplex mode)        - half duplex
 557          *                    CT (collision test)     - enable
 558          */
 559         SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
 560
 561         /* MDIO_ACC:
 562          *      RA (Request/Ack)  0x01 (Request)
 563          *      RW (Read/Write)   0x01 (Write)
 564          *      PHY_ADDR          0x06 (LAN)
 565          *      REG_ADDR          0x00 (PHY_BCR: basic control register)
 566          *      PHY_DATA          0x8000
 567          *                    Reset                   - software reset
 568          *                    LB (loop back)          - normal
 569          *                    SS (speed select)       - 10 Mbit/s
 570          *                    ANE (auto neg. enable)  - enable
 571          *                    PD (power down)         - normal
 572          *                    ISO (isolate)           - normal
 573          *                    RAN (restart auto neg.) - normal
 574          *                    DM (duplex mode)        - half duplex
 575          *                    CT (collision test)     - enable
 576          */
 577         SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
 578
 579 #endif
 580
 581         /* Make sure the CPU port is disabled for now. We
 582          * don't want packets to get stacked for us until
 583          * we enable DMA and are prepared to receive them.
 584          */
 585         SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
 586
 587         SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
 588
 589         /* CRC GEN is enabled.
 590          */
 591         regValue |= 0x00000200;
 592         SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
 593
 594         /* ADD TAG is disabled.
 595          */
 596         SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
 597         regValue &= ~0x00000002;
 598         SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
 599 }
 600
 601
 602 static void inca_dma_init(void)
 603 {
 604         /* Switch off all DMA channels.
 605          */
 606         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
 607         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
 608
 609         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
 610         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
 611         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
 612
 613         /* Setup TX channel polling time.
 614          */
 615         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
 616
 617         /* Setup RX channel polling time.
 618          */
 619         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
 620
 621         /* ERRATA: write reset value into the DMA RX IMR register.
 622          */
 623         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
 624
 625         /* Just in case: disable all transmit interrupts also.
 626          */
 627         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
 628
 629         DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
 630         DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
 631 }
 632
 633 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
 634 static int inca_amdix(void)
 635 {
 636         u32 phyReg1 = 0;
 637         u32 phyReg4 = 0;
 638         u32 phyReg5 = 0;
 639         u32 phyReg6 = 0;
 640         u32 phyReg31 = 0;
 641         u32 regEphy = 0;
 642         int mdi_flag;
 643         int retries;
 644
 645         /* Setup GPIO pins.
 646          */
 647         *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR    |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
 648         *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
 649
 650 #if 0
 651         /* Wait for signal.
 652          */
 653         retries = WAIT_SIGNAL_RETRIES;
 654         while (--retries) {
 655                 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
 656                                 (0x1 << 31) |   /* RA           */
 657                                 (0x0 << 30) |   /* Read         */
 658                                 (0x6 << 21) |   /* LAN          */
 659                                 (17  << 16));   /* PHY_MCSR     */
 660                 do {
 661                         SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
 662                 } while (phyReg1 & (1 << 31));
 663
 664                 if (phyReg1 & (1 << 1)) {
 665                         /* Signal detected */
 666                         break;
 667                 }
 668         }
 669
 670         if (!retries)
 671                 goto Fail;
 672 #endif
 673
 674         /* Set MDI mode.
 675          */
 676         *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
 677         mdi_flag = 1;
 678
 679         /* Wait for link.
 680          */
 681         retries = WAIT_LINK_RETRIES;
 682         while (--retries) {
 683                 udelay(LINK_RETRY_DELAY * 1000);
 684                 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
 685                                 (0x1 << 31) |   /* RA           */
 686                                 (0x0 << 30) |   /* Read         */
 687                                 (0x6 << 21) |   /* LAN          */
 688                                 (1   << 16));   /* PHY_BSR      */
 689                 do {
 690                         SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
 691                 } while (phyReg1 & (1 << 31));
 692
 693                 if (phyReg1 & (1 << 2)) {
 694                         /* Link is up */
 695                         break;
 696                 } else if (mdi_flag) {
 697                         /* Set MDIX mode */
 698                         *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
 699                         mdi_flag = 0;
 700                 } else {
 701                         /* Set MDI mode */
 702                         *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
 703                         mdi_flag = 1;
 704                 }
 705         }
 706
 707         if (!retries) {
 708                 goto Fail;
 709         } else {
 710                 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
 711                                 (0x1 << 31) |   /* RA           */
 712                                 (0x0 << 30) |   /* Read         */
 713                                 (0x6 << 21) |   /* LAN          */
 714                                 (1   << 16));   /* PHY_BSR      */
 715                 do {
 716                         SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
 717                 } while (phyReg1 & (1 << 31));
 718
 719                 /* Auto-negotiation / Parallel detection complete
 720                  */
 721                 if (phyReg1 & (1 << 5)) {
 722                         SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
 723                                 (0x1 << 31) |   /* RA           */
 724                                 (0x0 << 30) |   /* Read         */
 725                                 (0x6 << 21) |   /* LAN          */
 726                                 (31  << 16));   /* PHY_SCSR     */
 727                         do {
 728                                 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
 729                         } while (phyReg31 & (1 << 31));
 730
 731                         switch ((phyReg31 >> 2) & 0x7) {
 732                         case INCA_SWITCH_PHY_SPEED_10H:
 733                                 /* 10Base-T Half-duplex */
 734                                 regEphy = 0;
 735                                 break;
 736                         case INCA_SWITCH_PHY_SPEED_10F:
 737                                 /* 10Base-T Full-duplex */
 738                                 regEphy = INCA_IP_Switch_EPHY_DL;
 739                                 break;
 740                         case INCA_SWITCH_PHY_SPEED_100H:
 741                                 /* 100Base-TX Half-duplex */
 742                                 regEphy = INCA_IP_Switch_EPHY_SL;
 743                                 break;
 744                         case INCA_SWITCH_PHY_SPEED_100F:
 745                                 /* 100Base-TX Full-duplex */
 746                                 regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
 747                                 break;
 748                         }
 749
 750                         /* In case of Auto-negotiation,
 751                          * update the negotiated PAUSE support status
 752                          */
 753                         if (phyReg1 & (1 << 3)) {
 754                                 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
 755                                         (0x1 << 31) |   /* RA           */
 756                                         (0x0 << 30) |   /* Read         */
 757                                         (0x6 << 21) |   /* LAN          */
 758                                         (6   << 16));   /* PHY_ANER     */
 759                                 do {
 760                                         SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
 761                                 } while (phyReg6 & (1 << 31));
 762
 763                                 /* We are Autoneg-able.
 764                                  * Is Link partner also able to autoneg?
 765                                  */
 766                                 if (phyReg6 & (1 << 0)) {
 767                                         SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
 768                                                 (0x1 << 31) |   /* RA           */
 769                                                 (0x0 << 30) |   /* Read         */
 770                                                 (0x6 << 21) |   /* LAN          */
 771                                                 (4   << 16));   /* PHY_ANAR     */
 772                                         do {
 773                                                 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
 774                                         } while (phyReg4 & (1 << 31));
 775
 776                                         /* We advertise PAUSE capab.
 777                                          * Does link partner also advertise it?
 778                                          */
 779                                         if (phyReg4 & (1 << 10)) {
 780                                                 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
 781                                                         (0x1 << 31) |   /* RA           */
 782                                                         (0x0 << 30) |   /* Read         */
 783                                                         (0x6 << 21) |   /* LAN          */
 784                                                         (5   << 16));   /* PHY_ANLPAR   */
 785                                                 do {
 786                                                         SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
 787                                                 } while (phyReg5 & (1 << 31));
 788
 789                                                 /* Link partner is PAUSE capab.
 790                                                  */
 791                                                 if (phyReg5 & (1 << 10)) {
 792                                                         regEphy |= INCA_IP_Switch_EPHY_PL;
 793                                                 }
 794                                         }
 795                                 }
 796
 797                         }
 798
 799                         /* Link is up */
 800                         regEphy |= INCA_IP_Switch_EPHY_LL;
 801
 802                         SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
 803                 }
 804         }
 805
 806         return 0;
 807
 808 Fail:
 809         printf("No Link on LAN port\n");
 810         return -1;
 811 }
 812 #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */