drivers/net/gmac_rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
   4  *
   5  * Rockchip GMAC ethernet IP driver for U-Boot
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <clk.h>
  11 #include <log.h>
  12 #include <net.h>
  13 #include <phy.h>
  14 #include <syscon.h>
  15 #include <asm/global_data.h>
  16 #include <asm/io.h>
  17 #include <asm/arch-rockchip/periph.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/grf_px30.h>
  21 #include <asm/arch-rockchip/grf_rk322x.h>
  22 #include <asm/arch-rockchip/grf_rk3288.h>
  23 #include <asm/arch-rk3308/grf_rk3308.h>
  24 #include <asm/arch-rockchip/grf_rk3328.h>
  25 #include <asm/arch-rockchip/grf_rk3368.h>
  26 #include <asm/arch-rockchip/grf_rk3399.h>
  27 #include <asm/arch-rockchip/grf_rv1108.h>
  28 #include <dm/pinctrl.h>
  29 #include <dt-bindings/clock/rk3288-cru.h>
  30 #include <linux/bitops.h>
  31 #include "designware.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34 #define DELAY_ENABLE(soc, tx, rx) \
  35         (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
  36         ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
  37
  38 /*
  39  * Platform data for the gmac
  40  *
  41  * dw_eth_pdata: Required platform data for designware driver (must be first)
  42  */
  43 struct gmac_rockchip_plat {
  44         struct dw_eth_pdata dw_eth_pdata;
  45         bool clock_input;
  46         int tx_delay;
  47         int rx_delay;
  48 };
  49
  50 struct rk_gmac_ops {
  51         int (*fix_mac_speed)(struct dw_eth_dev *priv);
  52         void (*set_to_rmii)(struct gmac_rockchip_plat *pdata);
  53         void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
  54 };
  55
  56
  57 static int gmac_rockchip_of_to_plat(struct udevice *dev)
  58 {
  59         struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
  60         const char *string;
  61
  62         string = dev_read_string(dev, "clock_in_out");
  63         if (!strcmp(string, "input"))
  64                 pdata->clock_input = true;
  65         else
  66                 pdata->clock_input = false;
  67
  68         /* Check the new naming-style first... */
  69         pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
  70         pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
  71
  72         /* ... and fall back to the old naming style or default, if necessary */
  73         if (pdata->tx_delay == -ENOENT)
  74                 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
  75         if (pdata->rx_delay == -ENOENT)
  76                 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
  77
  78         return designware_eth_of_to_plat(dev);
  79 }
  80
  81 static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  82 {
  83         struct px30_grf *grf;
  84         struct clk clk_speed;
  85         int speed, ret;
  86         enum {
  87                 PX30_GMAC_SPEED_SHIFT = 0x2,
  88                 PX30_GMAC_SPEED_MASK  = BIT(2),
  89                 PX30_GMAC_SPEED_10M   = 0,
  90                 PX30_GMAC_SPEED_100M  = BIT(2),
  91         };
  92
  93         ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
  94                               &clk_speed);
  95         if (ret)
  96                 return ret;
  97
  98         switch (priv->phydev->speed) {
  99         case 10:
 100                 speed = PX30_GMAC_SPEED_10M;
 101                 ret = clk_set_rate(&clk_speed, 2500000);
 102                 if (ret)
 103                         return ret;
 104                 break;
 105         case 100:
 106                 speed = PX30_GMAC_SPEED_100M;
 107                 ret = clk_set_rate(&clk_speed, 25000000);
 108                 if (ret)
 109                         return ret;
 110                 break;
 111         default:
 112                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 113                 return -EINVAL;
 114         }
 115
 116         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 117         rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
 118
 119         return 0;
 120 }
 121
 122 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 123 {
 124         struct rk322x_grf *grf;
 125         int clk;
 126         enum {
 127                 RK3228_GMAC_CLK_SEL_SHIFT = 8,
 128                 RK3228_GMAC_CLK_SEL_MASK  = GENMASK(9, 8),
 129                 RK3228_GMAC_CLK_SEL_125M  = 0 << 8,
 130                 RK3228_GMAC_CLK_SEL_25M   = 3 << 8,
 131                 RK3228_GMAC_CLK_SEL_2_5M  = 2 << 8,
 132         };
 133
 134         switch (priv->phydev->speed) {
 135         case 10:
 136                 clk = RK3228_GMAC_CLK_SEL_2_5M;
 137                 break;
 138         case 100:
 139                 clk = RK3228_GMAC_CLK_SEL_25M;
 140                 break;
 141         case 1000:
 142                 clk = RK3228_GMAC_CLK_SEL_125M;
 143                 break;
 144         default:
 145                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 146                 return -EINVAL;
 147         }
 148
 149         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 150         rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
 151
 152         return 0;
 153 }
 154
 155 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 156 {
 157         struct rk3288_grf *grf;
 158         int clk;
 159
 160         switch (priv->phydev->speed) {
 161         case 10:
 162                 clk = RK3288_GMAC_CLK_SEL_2_5M;
 163                 break;
 164         case 100:
 165                 clk = RK3288_GMAC_CLK_SEL_25M;
 166                 break;
 167         case 1000:
 168                 clk = RK3288_GMAC_CLK_SEL_125M;
 169                 break;
 170         default:
 171                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 172                 return -EINVAL;
 173         }
 174
 175         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 176         rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
 177
 178         return 0;
 179 }
 180
 181 static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 182 {
 183         struct rk3308_grf *grf;
 184         struct clk clk_speed;
 185         int speed, ret;
 186         enum {
 187                 RK3308_GMAC_SPEED_SHIFT = 0x0,
 188                 RK3308_GMAC_SPEED_MASK  = BIT(0),
 189                 RK3308_GMAC_SPEED_10M   = 0,
 190                 RK3308_GMAC_SPEED_100M  = BIT(0),
 191         };
 192
 193         ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
 194                               &clk_speed);
 195         if (ret)
 196                 return ret;
 197
 198         switch (priv->phydev->speed) {
 199         case 10:
 200                 speed = RK3308_GMAC_SPEED_10M;
 201                 ret = clk_set_rate(&clk_speed, 2500000);
 202                 if (ret)
 203                         return ret;
 204                 break;
 205         case 100:
 206                 speed = RK3308_GMAC_SPEED_100M;
 207                 ret = clk_set_rate(&clk_speed, 25000000);
 208                 if (ret)
 209                         return ret;
 210                 break;
 211         default:
 212                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 213                 return -EINVAL;
 214         }
 215
 216         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 217         rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
 218
 219         return 0;
 220 }
 221
 222 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 223 {
 224         struct rk3328_grf_regs *grf;
 225         int clk;
 226         enum {
 227                 RK3328_GMAC_CLK_SEL_SHIFT = 11,
 228                 RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
 229                 RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
 230                 RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
 231                 RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
 232         };
 233
 234         switch (priv->phydev->speed) {
 235         case 10:
 236                 clk = RK3328_GMAC_CLK_SEL_2_5M;
 237                 break;
 238         case 100:
 239                 clk = RK3328_GMAC_CLK_SEL_25M;
 240                 break;
 241         case 1000:
 242                 clk = RK3328_GMAC_CLK_SEL_125M;
 243                 break;
 244         default:
 245                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 246                 return -EINVAL;
 247         }
 248
 249         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 250         rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
 251
 252         return 0;
 253 }
 254
 255 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 256 {
 257         struct rk3368_grf *grf;
 258         int clk;
 259         enum {
 260                 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
 261                 RK3368_GMAC_CLK_SEL_25M = 3 << 4,
 262                 RK3368_GMAC_CLK_SEL_125M = 0 << 4,
 263                 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
 264         };
 265
 266         switch (priv->phydev->speed) {
 267         case 10:
 268                 clk = RK3368_GMAC_CLK_SEL_2_5M;
 269                 break;
 270         case 100:
 271                 clk = RK3368_GMAC_CLK_SEL_25M;
 272                 break;
 273         case 1000:
 274                 clk = RK3368_GMAC_CLK_SEL_125M;
 275                 break;
 276         default:
 277                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 278                 return -EINVAL;
 279         }
 280
 281         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 282         rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
 283
 284         return 0;
 285 }
 286
 287 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 288 {
 289         struct rk3399_grf_regs *grf;
 290         int clk;
 291
 292         switch (priv->phydev->speed) {
 293         case 10:
 294                 clk = RK3399_GMAC_CLK_SEL_2_5M;
 295                 break;
 296         case 100:
 297                 clk = RK3399_GMAC_CLK_SEL_25M;
 298                 break;
 299         case 1000:
 300                 clk = RK3399_GMAC_CLK_SEL_125M;
 301                 break;
 302         default:
 303                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 304                 return -EINVAL;
 305         }
 306
 307         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 308         rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
 309
 310         return 0;
 311 }
 312
 313 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
 314 {
 315         struct rv1108_grf *grf;
 316         int clk, speed;
 317         enum {
 318                 RV1108_GMAC_SPEED_MASK          = BIT(2),
 319                 RV1108_GMAC_SPEED_10M           = 0 << 2,
 320                 RV1108_GMAC_SPEED_100M          = 1 << 2,
 321                 RV1108_GMAC_CLK_SEL_MASK        = BIT(7),
 322                 RV1108_GMAC_CLK_SEL_2_5M        = 0 << 7,
 323                 RV1108_GMAC_CLK_SEL_25M         = 1 << 7,
 324         };
 325
 326         switch (priv->phydev->speed) {
 327         case 10:
 328                 clk = RV1108_GMAC_CLK_SEL_2_5M;
 329                 speed = RV1108_GMAC_SPEED_10M;
 330                 break;
 331         case 100:
 332                 clk = RV1108_GMAC_CLK_SEL_25M;
 333                 speed = RV1108_GMAC_SPEED_100M;
 334                 break;
 335         default:
 336                 debug("Unknown phy speed: %d\n", priv->phydev->speed);
 337                 return -EINVAL;
 338         }
 339
 340         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 341         rk_clrsetreg(&grf->gmac_con0,
 342                      RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
 343                      clk | speed);
 344
 345         return 0;
 346 }
 347
 348 static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 349 {
 350         struct px30_grf *grf;
 351         enum {
 352                 PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
 353                 PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
 354                 PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
 355         };
 356
 357         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 358
 359         rk_clrsetreg(&grf->mac_con1,
 360                      PX30_GMAC_PHY_INTF_SEL_MASK,
 361                      PX30_GMAC_PHY_INTF_SEL_RMII);
 362 }
 363
 364 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 365 {
 366         struct rk322x_grf *grf;
 367         enum {
 368                 RK3228_RMII_MODE_SHIFT = 10,
 369                 RK3228_RMII_MODE_MASK  = BIT(10),
 370
 371                 RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
 372                 RK3228_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 373                 RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
 374
 375                 RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
 376                 RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 377                 RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
 378
 379                 RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
 380                 RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 381                 RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
 382         };
 383         enum {
 384                 RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
 385                 RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
 386
 387                 RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
 388                 RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 389         };
 390
 391         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 392         rk_clrsetreg(&grf->mac_con[1],
 393                      RK3228_RMII_MODE_MASK |
 394                      RK3228_GMAC_PHY_INTF_SEL_MASK |
 395                      RK3228_RXCLK_DLY_ENA_GMAC_MASK |
 396                      RK3228_TXCLK_DLY_ENA_GMAC_MASK,
 397                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 398                      DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
 399
 400         rk_clrsetreg(&grf->mac_con[0],
 401                      RK3228_CLK_RX_DL_CFG_GMAC_MASK |
 402                      RK3228_CLK_TX_DL_CFG_GMAC_MASK,
 403                      pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
 404                      pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
 405 }
 406
 407 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 408 {
 409         struct rk3288_grf *grf;
 410
 411         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 412         rk_clrsetreg(&grf->soc_con1,
 413                      RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
 414                      RK3288_GMAC_PHY_INTF_SEL_RGMII);
 415
 416         rk_clrsetreg(&grf->soc_con3,
 417                      RK3288_RXCLK_DLY_ENA_GMAC_MASK |
 418                      RK3288_TXCLK_DLY_ENA_GMAC_MASK |
 419                      RK3288_CLK_RX_DL_CFG_GMAC_MASK |
 420                      RK3288_CLK_TX_DL_CFG_GMAC_MASK,
 421                      DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
 422                      pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
 423                      pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 424 }
 425
 426 static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 427 {
 428         struct rk3308_grf *grf;
 429         enum {
 430                 RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
 431                 RK3308_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 2),
 432                 RK3308_GMAC_PHY_INTF_SEL_RMII  = BIT(4),
 433         };
 434
 435         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 436
 437         rk_clrsetreg(&grf->mac_con0,
 438                      RK3308_GMAC_PHY_INTF_SEL_MASK,
 439                      RK3308_GMAC_PHY_INTF_SEL_RMII);
 440 }
 441
 442 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 443 {
 444         struct rk3328_grf_regs *grf;
 445         enum {
 446                 RK3328_RMII_MODE_SHIFT = 9,
 447                 RK3328_RMII_MODE_MASK  = BIT(9),
 448
 449                 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
 450                 RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 451                 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
 452
 453                 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
 454                 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 455                 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
 456
 457                 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
 458                 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 459                 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
 460         };
 461         enum {
 462                 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
 463                 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
 464
 465                 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
 466                 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 467         };
 468
 469         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 470         rk_clrsetreg(&grf->mac_con[1],
 471                      RK3328_RMII_MODE_MASK |
 472                      RK3328_GMAC_PHY_INTF_SEL_MASK |
 473                      RK3328_RXCLK_DLY_ENA_GMAC_MASK |
 474                      RK3328_TXCLK_DLY_ENA_GMAC_MASK,
 475                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 476                      DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
 477
 478         rk_clrsetreg(&grf->mac_con[0],
 479                      RK3328_CLK_RX_DL_CFG_GMAC_MASK |
 480                      RK3328_CLK_TX_DL_CFG_GMAC_MASK,
 481                      pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
 482                      pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
 483 }
 484
 485 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 486 {
 487         struct rk3368_grf *grf;
 488         enum {
 489                 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
 490                 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
 491                 RK3368_RMII_MODE_MASK  = BIT(6),
 492                 RK3368_RMII_MODE       = BIT(6),
 493         };
 494         enum {
 495                 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
 496                 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 497                 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
 498                 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
 499                 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 500                 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
 501                 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
 502                 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
 503                 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
 504                 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
 505         };
 506
 507         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 508         rk_clrsetreg(&grf->soc_con15,
 509                      RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
 510                      RK3368_GMAC_PHY_INTF_SEL_RGMII);
 511
 512         rk_clrsetreg(&grf->soc_con16,
 513                      RK3368_RXCLK_DLY_ENA_GMAC_MASK |
 514                      RK3368_TXCLK_DLY_ENA_GMAC_MASK |
 515                      RK3368_CLK_RX_DL_CFG_GMAC_MASK |
 516                      RK3368_CLK_TX_DL_CFG_GMAC_MASK,
 517                      DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
 518                      pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
 519                      pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
 520 }
 521
 522 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 523 {
 524         struct rk3399_grf_regs *grf;
 525
 526         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 527
 528         rk_clrsetreg(&grf->soc_con5,
 529                      RK3399_GMAC_PHY_INTF_SEL_MASK,
 530                      RK3399_GMAC_PHY_INTF_SEL_RGMII);
 531
 532         rk_clrsetreg(&grf->soc_con6,
 533                      RK3399_RXCLK_DLY_ENA_GMAC_MASK |
 534                      RK3399_TXCLK_DLY_ENA_GMAC_MASK |
 535                      RK3399_CLK_RX_DL_CFG_GMAC_MASK |
 536                      RK3399_CLK_TX_DL_CFG_GMAC_MASK,
 537                      DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
 538                      pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
 539                      pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
 540 }
 541
 542 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 543 {
 544         struct rv1108_grf *grf;
 545
 546         enum {
 547                 RV1108_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
 548                 RV1108_GMAC_PHY_INTF_SEL_RMII  = 4 << 4,
 549         };
 550
 551         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 552         rk_clrsetreg(&grf->gmac_con0,
 553                      RV1108_GMAC_PHY_INTF_SEL_MASK,
 554                      RV1108_GMAC_PHY_INTF_SEL_RMII);
 555 }
 556
 557 static int gmac_rockchip_probe(struct udevice *dev)
 558 {
 559         struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
 560         struct rk_gmac_ops *ops =
 561                 (struct rk_gmac_ops *)dev_get_driver_data(dev);
 562         struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
 563         struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
 564         struct clk clk;
 565         ulong rate;
 566         int ret;
 567
 568         ret = clk_set_defaults(dev, CLK_DEFAULTS_PRE);
 569         if (ret)
 570                 debug("%s clk_set_defaults failed %d\n", __func__, ret);
 571
 572         ret = clk_get_by_index(dev, 0, &clk);
 573         if (ret)
 574                 return ret;
 575
 576         switch (eth_pdata->phy_interface) {
 577         case PHY_INTERFACE_MODE_RGMII:
 578                 /* Set to RGMII mode */
 579                 if (ops->set_to_rgmii)
 580                         ops->set_to_rgmii(pdata);
 581                 else
 582                         return -EPERM;
 583
 584                 /*
 585                  * If the gmac clock is from internal pll, need to set and
 586                  * check the return value for gmac clock at RGMII mode. If
 587                  * the gmac clock is from external source, the clock rate
 588                  * is not set, because of it is bypassed.
 589                  */
 590
 591                 if (!pdata->clock_input) {
 592                         rate = clk_set_rate(&clk, 125000000);
 593                         if (rate != 125000000)
 594                                 return -EINVAL;
 595                 }
 596                 break;
 597
 598         case PHY_INTERFACE_MODE_RGMII_ID:
 599                 /* Set to RGMII mode */
 600                 if (ops->set_to_rgmii) {
 601                         pdata->tx_delay = 0;
 602                         pdata->rx_delay = 0;
 603                         ops->set_to_rgmii(pdata);
 604                 } else
 605                         return -EPERM;
 606
 607                 if (!pdata->clock_input) {
 608                         rate = clk_set_rate(&clk, 125000000);
 609                         if (rate != 125000000)
 610                                 return -EINVAL;
 611                 }
 612                 break;
 613
 614         case PHY_INTERFACE_MODE_RMII:
 615                 /* Set to RMII mode */
 616                 if (ops->set_to_rmii)
 617                         ops->set_to_rmii(pdata);
 618                 else
 619                         return -EPERM;
 620
 621                 if (!pdata->clock_input) {
 622                         rate = clk_set_rate(&clk, 50000000);
 623                         if (rate != 50000000)
 624                                 return -EINVAL;
 625                 }
 626                 break;
 627
 628         case PHY_INTERFACE_MODE_RGMII_RXID:
 629                  /* Set to RGMII_RXID mode */
 630                 if (ops->set_to_rgmii) {
 631                         pdata->tx_delay = 0;
 632                         ops->set_to_rgmii(pdata);
 633                 } else
 634                         return -EPERM;
 635
 636                 if (!pdata->clock_input) {
 637                         rate = clk_set_rate(&clk, 125000000);
 638                         if (rate != 125000000)
 639                                 return -EINVAL;
 640                 }
 641                 break;
 642
 643         case PHY_INTERFACE_MODE_RGMII_TXID:
 644                 /* Set to RGMII_TXID mode */
 645                 if (ops->set_to_rgmii) {
 646                         pdata->rx_delay = 0;
 647                         ops->set_to_rgmii(pdata);
 648                 } else
 649                         return -EPERM;
 650
 651                 if (!pdata->clock_input) {
 652                         rate = clk_set_rate(&clk, 125000000);
 653                         if (rate != 125000000)
 654                                 return -EINVAL;
 655                 }
 656                 break;
 657
 658         default:
 659                 debug("NO interface defined!\n");
 660                 return -ENXIO;
 661         }
 662
 663         return designware_eth_probe(dev);
 664 }
 665
 666 static int gmac_rockchip_eth_start(struct udevice *dev)
 667 {
 668         struct eth_pdata *pdata = dev_get_plat(dev);
 669         struct dw_eth_dev *priv = dev_get_priv(dev);
 670         struct rk_gmac_ops *ops =
 671                 (struct rk_gmac_ops *)dev_get_driver_data(dev);
 672         int ret;
 673
 674         ret = designware_eth_init(priv, pdata->enetaddr);
 675         if (ret)
 676                 return ret;
 677         ret = ops->fix_mac_speed(priv);
 678         if (ret)
 679                 return ret;
 680         ret = designware_eth_enable(priv);
 681         if (ret)
 682                 return ret;
 683
 684         return 0;
 685 }
 686
 687 const struct eth_ops gmac_rockchip_eth_ops = {
 688         .start                  = gmac_rockchip_eth_start,
 689         .send                   = designware_eth_send,
 690         .recv                   = designware_eth_recv,
 691         .free_pkt               = designware_eth_free_pkt,
 692         .stop                   = designware_eth_stop,
 693         .write_hwaddr           = designware_eth_write_hwaddr,
 694 };
 695
 696 const struct rk_gmac_ops px30_gmac_ops = {
 697         .fix_mac_speed = px30_gmac_fix_mac_speed,
 698         .set_to_rmii = px30_gmac_set_to_rmii,
 699 };
 700
 701 const struct rk_gmac_ops rk3228_gmac_ops = {
 702         .fix_mac_speed = rk3228_gmac_fix_mac_speed,
 703         .set_to_rgmii = rk3228_gmac_set_to_rgmii,
 704 };
 705
 706 const struct rk_gmac_ops rk3288_gmac_ops = {
 707         .fix_mac_speed = rk3288_gmac_fix_mac_speed,
 708         .set_to_rgmii = rk3288_gmac_set_to_rgmii,
 709 };
 710
 711 const struct rk_gmac_ops rk3308_gmac_ops = {
 712         .fix_mac_speed = rk3308_gmac_fix_mac_speed,
 713         .set_to_rmii = rk3308_gmac_set_to_rmii,
 714 };
 715
 716 const struct rk_gmac_ops rk3328_gmac_ops = {
 717         .fix_mac_speed = rk3328_gmac_fix_mac_speed,
 718         .set_to_rgmii = rk3328_gmac_set_to_rgmii,
 719 };
 720
 721 const struct rk_gmac_ops rk3368_gmac_ops = {
 722         .fix_mac_speed = rk3368_gmac_fix_mac_speed,
 723         .set_to_rgmii = rk3368_gmac_set_to_rgmii,
 724 };
 725
 726 const struct rk_gmac_ops rk3399_gmac_ops = {
 727         .fix_mac_speed = rk3399_gmac_fix_mac_speed,
 728         .set_to_rgmii = rk3399_gmac_set_to_rgmii,
 729 };
 730
 731 const struct rk_gmac_ops rv1108_gmac_ops = {
 732         .fix_mac_speed = rv1108_set_rmii_speed,
 733         .set_to_rmii = rv1108_gmac_set_to_rmii,
 734 };
 735
 736 static const struct udevice_id rockchip_gmac_ids[] = {
 737         { .compatible = "rockchip,px30-gmac",
 738           .data = (ulong)&px30_gmac_ops },
 739         { .compatible = "rockchip,rk3228-gmac",
 740           .data = (ulong)&rk3228_gmac_ops },
 741         { .compatible = "rockchip,rk3288-gmac",
 742           .data = (ulong)&rk3288_gmac_ops },
 743         { .compatible = "rockchip,rk3308-mac",
 744           .data = (ulong)&rk3308_gmac_ops },
 745         { .compatible = "rockchip,rk3328-gmac",
 746           .data = (ulong)&rk3328_gmac_ops },
 747         { .compatible = "rockchip,rk3368-gmac",
 748           .data = (ulong)&rk3368_gmac_ops },
 749         { .compatible = "rockchip,rk3399-gmac",
 750           .data = (ulong)&rk3399_gmac_ops },
 751         { .compatible = "rockchip,rv1108-gmac",
 752           .data = (ulong)&rv1108_gmac_ops },
 753         { }
 754 };
 755
 756 U_BOOT_DRIVER(eth_gmac_rockchip) = {
 757         .name   = "gmac_rockchip",
 758         .id     = UCLASS_ETH,
 759         .of_match = rockchip_gmac_ids,
 760         .of_to_plat = gmac_rockchip_of_to_plat,
 761         .probe  = gmac_rockchip_probe,
 762         .ops    = &gmac_rockchip_eth_ops,
 763         .priv_auto      = sizeof(struct dw_eth_dev),
 764         .plat_auto      = sizeof(struct gmac_rockchip_plat),
 765         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 766 };