2 * drivers/net/gianfar.h
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
20 * -Add support for module parameters
21 * -Add patch for ethtool phys id
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/string.h>
29 #include <linux/errno.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
39 #include <linux/mii.h>
40 #include <linux/phy.h>
44 #include <asm/uaccess.h>
45 #include <linux/module.h>
46 #include <linux/crc32.h>
47 #include <linux/workqueue.h>
48 #include <linux/ethtool.h>
50 /* The maximum number of packets to be handled in one call of gfar_poll */
51 #define GFAR_DEV_WEIGHT 64
54 #define GMAC_FCB_LEN 8
56 /* Default padding amount */
57 #define DEFAULT_PADDING 2
59 /* Number of bytes to align the rx bufs to */
60 #define RXBUF_ALIGNMENT 64
62 /* The number of bytes which composes a unit for the purpose of
63 * allocating data buffers. ie-for any given MTU, the data buffer
64 * will be the next highest multiple of 512 bytes. */
65 #define INCREMENTAL_BUFFER_SIZE 512
68 #define MAC_ADDR_LEN 6
70 #define PHY_INIT_TIMEOUT 100000
71 #define GFAR_PHY_CHANGE_TIME 2
73 #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
74 #define DRV_NAME "gfar-enet"
75 extern const char gfar_driver_name[];
76 extern const char gfar_driver_version[];
78 /* MAXIMUM NUMBER OF QUEUES SUPPORTED */
82 /* These need to be powers of 2 for this driver */
83 #define DEFAULT_TX_RING_SIZE 256
84 #define DEFAULT_RX_RING_SIZE 256
86 #define GFAR_RX_MAX_RING_SIZE 256
87 #define GFAR_TX_MAX_RING_SIZE 256
89 #define GFAR_MAX_FIFO_THRESHOLD 511
90 #define GFAR_MAX_FIFO_STARVE 511
91 #define GFAR_MAX_FIFO_STARVE_OFF 511
93 #define DEFAULT_RX_BUFFER_SIZE 1536
94 #define TX_RING_MOD_MASK(size) (size-1)
95 #define RX_RING_MOD_MASK(size) (size-1)
96 #define JUMBO_BUFFER_SIZE 9728
97 #define JUMBO_FRAME_SIZE 9600
99 #define DEFAULT_FIFO_TX_THR 0x100
100 #define DEFAULT_FIFO_TX_STARVE 0x40
101 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
102 #define DEFAULT_BD_STASH 1
103 #define DEFAULT_STASH_LENGTH 96
104 #define DEFAULT_STASH_INDEX 0
106 /* The number of Exact Match registers */
107 #define GFAR_EM_NUM 15
109 /* Latency of interface clock in nanoseconds */
110 /* Interface clock latency , in this case, means the
111 * time described by a value of 1 in the interrupt
112 * coalescing registers' time fields. Since those fields
113 * refer to the time it takes for 64 clocks to pass, the
114 * latencies are as such:
115 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
116 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
117 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
119 #define GFAR_GBIT_TIME 512
120 #define GFAR_100_TIME 2560
121 #define GFAR_10_TIME 25600
123 #define DEFAULT_TX_COALESCE 1
124 #define DEFAULT_TXCOUNT 16
125 #define DEFAULT_TXTIME 21
127 #define DEFAULT_RXTIME 21
129 #define DEFAULT_RX_COALESCE 0
130 #define DEFAULT_RXCOUNT 0
132 #define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
133 | SUPPORTED_10baseT_Full \
134 | SUPPORTED_100baseT_Half \
135 | SUPPORTED_100baseT_Full \
136 | SUPPORTED_Autoneg \
139 /* TBI register addresses */
140 #define MII_TBICON 0x11
142 /* TBICON register bit fields */
143 #define TBICON_CLK_SELECT 0x0020
145 /* MAC register bits */
146 #define MACCFG1_SOFT_RESET 0x80000000
147 #define MACCFG1_RESET_RX_MC 0x00080000
148 #define MACCFG1_RESET_TX_MC 0x00040000
149 #define MACCFG1_RESET_RX_FUN 0x00020000
150 #define MACCFG1_RESET_TX_FUN 0x00010000
151 #define MACCFG1_LOOPBACK 0x00000100
152 #define MACCFG1_RX_FLOW 0x00000020
153 #define MACCFG1_TX_FLOW 0x00000010
154 #define MACCFG1_SYNCD_RX_EN 0x00000008
155 #define MACCFG1_RX_EN 0x00000004
156 #define MACCFG1_SYNCD_TX_EN 0x00000002
157 #define MACCFG1_TX_EN 0x00000001
159 #define MACCFG2_INIT_SETTINGS 0x00007205
160 #define MACCFG2_FULL_DUPLEX 0x00000001
161 #define MACCFG2_IF 0x00000300
162 #define MACCFG2_MII 0x00000100
163 #define MACCFG2_GMII 0x00000200
164 #define MACCFG2_HUGEFRAME 0x00000020
165 #define MACCFG2_LENGTHCHECK 0x00000010
166 #define MACCFG2_MPEN 0x00000008
168 #define ECNTRL_INIT_SETTINGS 0x00001000
169 #define ECNTRL_TBI_MODE 0x00000020
170 #define ECNTRL_REDUCED_MODE 0x00000010
171 #define ECNTRL_R100 0x00000008
172 #define ECNTRL_REDUCED_MII_MODE 0x00000004
173 #define ECNTRL_SGMII_MODE 0x00000002
175 #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
177 #define MINFLR_INIT_SETTINGS 0x00000040
180 #define TQUEUE_EN0 0x00008000
181 #define TQUEUE_EN1 0x00004000
182 #define TQUEUE_EN2 0x00002000
183 #define TQUEUE_EN3 0x00001000
184 #define TQUEUE_EN4 0x00000800
185 #define TQUEUE_EN5 0x00000400
186 #define TQUEUE_EN6 0x00000200
187 #define TQUEUE_EN7 0x00000100
188 #define TQUEUE_EN_ALL 0x0000FF00
190 #define TR03WT_WT0_MASK 0xFF000000
191 #define TR03WT_WT1_MASK 0x00FF0000
192 #define TR03WT_WT2_MASK 0x0000FF00
193 #define TR03WT_WT3_MASK 0x000000FF
195 #define TR47WT_WT4_MASK 0xFF000000
196 #define TR47WT_WT5_MASK 0x00FF0000
197 #define TR47WT_WT6_MASK 0x0000FF00
198 #define TR47WT_WT7_MASK 0x000000FF
201 #define RQUEUE_EX0 0x00800000
202 #define RQUEUE_EX1 0x00400000
203 #define RQUEUE_EX2 0x00200000
204 #define RQUEUE_EX3 0x00100000
205 #define RQUEUE_EX4 0x00080000
206 #define RQUEUE_EX5 0x00040000
207 #define RQUEUE_EX6 0x00020000
208 #define RQUEUE_EX7 0x00010000
209 #define RQUEUE_EX_ALL 0x00FF0000
211 #define RQUEUE_EN0 0x00000080
212 #define RQUEUE_EN1 0x00000040
213 #define RQUEUE_EN2 0x00000020
214 #define RQUEUE_EN3 0x00000010
215 #define RQUEUE_EN4 0x00000008
216 #define RQUEUE_EN5 0x00000004
217 #define RQUEUE_EN6 0x00000002
218 #define RQUEUE_EN7 0x00000001
219 #define RQUEUE_EN_ALL 0x000000FF
221 /* Init to do tx snooping for buffers and descriptors */
222 #define DMACTRL_INIT_SETTINGS 0x000000c3
223 #define DMACTRL_GRS 0x00000010
224 #define DMACTRL_GTS 0x00000008
226 #define TSTAT_CLEAR_THALT_ALL 0xFF000000
227 #define TSTAT_CLEAR_THALT 0x80000000
228 #define TSTAT_CLEAR_THALT0 0x80000000
229 #define TSTAT_CLEAR_THALT1 0x40000000
230 #define TSTAT_CLEAR_THALT2 0x20000000
231 #define TSTAT_CLEAR_THALT3 0x10000000
232 #define TSTAT_CLEAR_THALT4 0x08000000
233 #define TSTAT_CLEAR_THALT5 0x04000000
234 #define TSTAT_CLEAR_THALT6 0x02000000
235 #define TSTAT_CLEAR_THALT7 0x01000000
237 /* Interrupt coalescing macros */
238 #define IC_ICEN 0x80000000
239 #define IC_ICFT_MASK 0x1fe00000
240 #define IC_ICFT_SHIFT 21
241 #define mk_ic_icft(x) \
242 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
243 #define IC_ICTT_MASK 0x0000ffff
244 #define mk_ic_ictt(x) (x&IC_ICTT_MASK)
246 #define mk_ic_value(count, time) (IC_ICEN | \
247 mk_ic_icft(count) | \
249 #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
251 #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
253 #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
254 #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
256 #define skip_bd(bdp, stride, base, ring_size) ({ \
257 typeof(bdp) new_bd = (bdp) + (stride); \
258 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
260 #define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
262 #define RCTRL_PAL_MASK 0x001f0000
263 #define RCTRL_VLEX 0x00002000
264 #define RCTRL_FILREN 0x00001000
265 #define RCTRL_GHTX 0x00000400
266 #define RCTRL_IPCSEN 0x00000200
267 #define RCTRL_TUCSEN 0x00000100
268 #define RCTRL_PRSDEP_MASK 0x000000c0
269 #define RCTRL_PRSDEP_INIT 0x000000c0
270 #define RCTRL_PROM 0x00000008
271 #define RCTRL_EMEN 0x00000002
272 #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
274 #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
276 #define RCTRL_EXTHASH (RCTRL_GHTX)
277 #define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
278 #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
281 #define RSTAT_CLEAR_RHALT 0x00800000
283 #define TCTRL_IPCSEN 0x00004000
284 #define TCTRL_TUCSEN 0x00002000
285 #define TCTRL_VLINS 0x00001000
286 #define TCTRL_THDF 0x00000800
287 #define TCTRL_RFCPAUSE 0x00000010
288 #define TCTRL_TFCPAUSE 0x00000008
289 #define TCTRL_TXSCHED_MASK 0x00000006
290 #define TCTRL_TXSCHED_INIT 0x00000000
291 #define TCTRL_TXSCHED_PRIO 0x00000002
292 #define TCTRL_TXSCHED_WRRS 0x00000004
293 #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
295 #define IEVENT_INIT_CLEAR 0xffffffff
296 #define IEVENT_BABR 0x80000000
297 #define IEVENT_RXC 0x40000000
298 #define IEVENT_BSY 0x20000000
299 #define IEVENT_EBERR 0x10000000
300 #define IEVENT_MSRO 0x04000000
301 #define IEVENT_GTSC 0x02000000
302 #define IEVENT_BABT 0x01000000
303 #define IEVENT_TXC 0x00800000
304 #define IEVENT_TXE 0x00400000
305 #define IEVENT_TXB 0x00200000
306 #define IEVENT_TXF 0x00100000
307 #define IEVENT_LC 0x00040000
308 #define IEVENT_CRL 0x00020000
309 #define IEVENT_XFUN 0x00010000
310 #define IEVENT_RXB0 0x00008000
311 #define IEVENT_MAG 0x00000800
312 #define IEVENT_GRSC 0x00000100
313 #define IEVENT_RXF0 0x00000080
314 #define IEVENT_FIR 0x00000008
315 #define IEVENT_FIQ 0x00000004
316 #define IEVENT_DPE 0x00000002
317 #define IEVENT_PERR 0x00000001
318 #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
319 #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
320 #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
321 #define IEVENT_ERR_MASK \
322 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
323 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
324 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
325 | IEVENT_MAG | IEVENT_BABR)
327 #define IMASK_INIT_CLEAR 0x00000000
328 #define IMASK_BABR 0x80000000
329 #define IMASK_RXC 0x40000000
330 #define IMASK_BSY 0x20000000
331 #define IMASK_EBERR 0x10000000
332 #define IMASK_MSRO 0x04000000
333 #define IMASK_GRSC 0x02000000
334 #define IMASK_BABT 0x01000000
335 #define IMASK_TXC 0x00800000
336 #define IMASK_TXEEN 0x00400000
337 #define IMASK_TXBEN 0x00200000
338 #define IMASK_TXFEN 0x00100000
339 #define IMASK_LC 0x00040000
340 #define IMASK_CRL 0x00020000
341 #define IMASK_XFUN 0x00010000
342 #define IMASK_RXB0 0x00008000
343 #define IMASK_MAG 0x00000800
344 #define IMASK_GTSC 0x00000100
345 #define IMASK_RXFEN0 0x00000080
346 #define IMASK_FIR 0x00000008
347 #define IMASK_FIQ 0x00000004
348 #define IMASK_DPE 0x00000002
349 #define IMASK_PERR 0x00000001
350 #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
351 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
352 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
354 #define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
357 /* Fifo management */
358 #define FIFO_TX_THR_MASK 0x01ff
359 #define FIFO_TX_STARVE_MASK 0x01ff
360 #define FIFO_TX_STARVE_OFF_MASK 0x01ff
362 /* Attribute fields */
364 /* This enables rx snooping for buffers and descriptors */
365 #define ATTR_BDSTASH 0x00000800
367 #define ATTR_BUFSTASH 0x00004000
369 #define ATTR_SNOOPING 0x000000c0
370 #define ATTR_INIT_SETTINGS ATTR_SNOOPING
372 #define ATTRELI_INIT_SETTINGS 0x0
373 #define ATTRELI_EL_MASK 0x3fff0000
374 #define ATTRELI_EL(x) (x << 16)
375 #define ATTRELI_EI_MASK 0x00003fff
376 #define ATTRELI_EI(x) (x)
378 #define BD_LFLAG(flags) ((flags) << 16)
379 #define BD_LENGTH_MASK 0x0000ffff
381 /* TxBD status field bits */
382 #define TXBD_READY 0x8000
383 #define TXBD_PADCRC 0x4000
384 #define TXBD_WRAP 0x2000
385 #define TXBD_INTERRUPT 0x1000
386 #define TXBD_LAST 0x0800
387 #define TXBD_CRC 0x0400
388 #define TXBD_DEF 0x0200
389 #define TXBD_HUGEFRAME 0x0080
390 #define TXBD_LATECOLLISION 0x0080
391 #define TXBD_RETRYLIMIT 0x0040
392 #define TXBD_RETRYCOUNTMASK 0x003c
393 #define TXBD_UNDERRUN 0x0002
394 #define TXBD_TOE 0x0002
396 /* Tx FCB param bits */
397 #define TXFCB_VLN 0x80
398 #define TXFCB_IP 0x40
399 #define TXFCB_IP6 0x20
400 #define TXFCB_TUP 0x10
401 #define TXFCB_UDP 0x08
402 #define TXFCB_CIP 0x04
403 #define TXFCB_CTU 0x02
404 #define TXFCB_NPH 0x01
405 #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
407 /* RxBD status field bits */
408 #define RXBD_EMPTY 0x8000
409 #define RXBD_RO1 0x4000
410 #define RXBD_WRAP 0x2000
411 #define RXBD_INTERRUPT 0x1000
412 #define RXBD_LAST 0x0800
413 #define RXBD_FIRST 0x0400
414 #define RXBD_MISS 0x0100
415 #define RXBD_BROADCAST 0x0080
416 #define RXBD_MULTICAST 0x0040
417 #define RXBD_LARGE 0x0020
418 #define RXBD_NONOCTET 0x0010
419 #define RXBD_SHORT 0x0008
420 #define RXBD_CRCERR 0x0004
421 #define RXBD_OVERRUN 0x0002
422 #define RXBD_TRUNCATED 0x0001
423 #define RXBD_STATS 0x01ff
424 #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
425 | RXBD_CRCERR | RXBD_OVERRUN \
428 /* Rx FCB status field bits */
429 #define RXFCB_VLN 0x8000
430 #define RXFCB_IP 0x4000
431 #define RXFCB_IP6 0x2000
432 #define RXFCB_TUP 0x1000
433 #define RXFCB_CIP 0x0800
434 #define RXFCB_CTU 0x0400
435 #define RXFCB_EIP 0x0200
436 #define RXFCB_ETU 0x0100
437 #define RXFCB_CSUM_MASK 0x0f00
438 #define RXFCB_PERR_MASK 0x000c
439 #define RXFCB_PERR_BADL3 0x0008
441 #define GFAR_INT_NAME_MAX IFNAMSIZ + 4
447 u16 status; /* Status Fields */
448 u16 length; /* Buffer length */
452 u32 bufPtr; /* Buffer Pointer */
458 u8 l4os; /* Level 4 Header Offset */
459 u8 l3os; /* Level 3 Header Offset */
460 u16 phcs; /* Pseudo-header Checksum */
461 u16 vlctl; /* VLAN control word */
468 u16 status; /* Status Fields */
469 u16 length; /* Buffer Length */
473 u32 bufPtr; /* Buffer Pointer */
478 u8 rq; /* Receive Queue index */
479 u8 pro; /* Layer 4 Protocol */
481 u16 vlctl; /* VLAN control word */
486 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
487 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
488 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
489 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
490 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
491 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
492 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
493 u32 rbyt; /* 0x.69c - Receive Byte Counter */
494 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
495 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
496 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
497 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
498 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
499 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
500 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
501 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
502 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
503 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
504 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
505 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
506 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
507 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
508 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
509 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
510 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
511 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
512 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
513 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
514 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
515 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
516 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
517 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
518 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
519 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
520 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
521 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
523 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
524 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
525 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
526 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
527 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
528 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
529 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
530 u32 car1; /* 0x.730 - Carry Register One */
531 u32 car2; /* 0x.734 - Carry Register Two */
532 u32 cam1; /* 0x.738 - Carry Mask Register One */
533 u32 cam2; /* 0x.73c - Carry Mask Register Two */
536 struct gfar_extra_stats {
553 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
554 #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
556 /* Number of stats in the stats structure (ignore car and cam regs)*/
557 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
559 #define GFAR_INFOSTR_LEN 32
562 u64 extra[GFAR_EXTRA_STATS_LEN];
563 u64 rmon[GFAR_RMON_LEN];
568 u32 tsec_id; /* 0x.000 - Controller ID register */
570 u32 ievent; /* 0x.010 - Interrupt Event Register */
571 u32 imask; /* 0x.014 - Interrupt Mask Register */
572 u32 edis; /* 0x.018 - Error Disabled Register */
574 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
575 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
576 u32 ptv; /* 0x.028 - Pause Time Value Register */
577 u32 dmactrl; /* 0x.02c - DMA Control Register */
578 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
580 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
582 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
583 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
585 u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
586 u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
588 u32 tctrl; /* 0x.100 - Transmit Control Register */
589 u32 tstat; /* 0x.104 - Transmit Status Register */
590 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
591 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
592 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
593 u32 tqueue; /* 0x.114 - Transmit queue control register */
595 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
596 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
598 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
600 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
602 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
604 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
606 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
608 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
610 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
612 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
614 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
616 u32 tbaseh; /* 0x.200 - TxBD base address high */
617 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
619 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
621 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
623 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
625 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
627 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
629 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
631 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
633 u32 rctrl; /* 0x.300 - Receive Control Register */
634 u32 rstat; /* 0x.304 - Receive Status Register */
636 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
637 u32 rqueue; /* 0x.314 - Receive queue control register */
639 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
640 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
641 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
642 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
643 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
645 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
647 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
649 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
651 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
653 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
655 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
657 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
659 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
661 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
663 u32 rbaseh; /* 0x.400 - RxBD base address high */
664 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
666 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
668 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
670 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
672 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
674 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
676 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
678 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
680 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
681 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
682 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
683 u32 hafdup; /* 0x.50c - Half Duplex Register */
684 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
686 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
688 u32 ifstat; /* 0x.53c - Interface Status Register */
689 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
690 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
691 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
692 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
693 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
694 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
695 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
696 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
697 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
698 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
699 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
700 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
701 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
702 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
703 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
704 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
705 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
706 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
707 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
708 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
709 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
710 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
711 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
712 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
713 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
714 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
715 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
716 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
717 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
718 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
719 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
720 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
722 struct rmon_mib rmon; /* 0x.680-0x.73c */
723 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
725 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
726 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
727 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
728 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
729 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
730 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
731 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
732 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
734 u32 gaddr0; /* 0x.880 - Group address register 0 */
735 u32 gaddr1; /* 0x.884 - Group address register 1 */
736 u32 gaddr2; /* 0x.888 - Group address register 2 */
737 u32 gaddr3; /* 0x.88c - Group address register 3 */
738 u32 gaddr4; /* 0x.890 - Group address register 4 */
739 u32 gaddr5; /* 0x.894 - Group address register 5 */
740 u32 gaddr6; /* 0x.898 - Group address register 6 */
741 u32 gaddr7; /* 0x.89c - Group address register 7 */
743 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
746 u32 attr; /* 0x.bf8 - Attributes Register */
747 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
752 /* Flags related to gianfar device features */
753 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
754 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
755 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
756 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
757 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
758 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
759 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
760 #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
761 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
762 #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
763 #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
765 #define DEFAULT_MAPPING 0xFF
768 * struct gfar_priv_tx_q - per tx queue structure
769 * @txlock: per queue tx spin lock
770 * @tx_skbuff:skb pointers
771 * @skb_curtx: to be used skb pointer
772 * @skb_dirtytx:the last used skb pointer
773 * @qindex: index of this queue
774 * @dev: back pointer to the dev structure
775 * @grp: back pointer to the group to which this queue belongs
776 * @tx_bd_base: First tx buffer descriptor
777 * @cur_tx: Next free ring entry
778 * @dirty_tx: First buffer in line to be transmitted
779 * @tx_ring_size: Tx ring size
780 * @num_txbdfree: number of free TxBds
781 * @txcoalescing: enable/disable tx coalescing
782 * @txic: transmit interrupt coalescing value
783 * @txcount: coalescing value if based on tx frame count
784 * @txtime: coalescing value if based on time
786 struct gfar_priv_tx_q {
787 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
788 struct sk_buff ** tx_skbuff;
789 /* Buffer descriptor pointers */
790 dma_addr_t tx_bd_dma_base;
791 struct txbd8 *tx_bd_base;
792 struct txbd8 *cur_tx;
793 struct txbd8 *dirty_tx;
794 struct net_device *dev;
798 unsigned int tx_ring_size;
799 unsigned int num_txbdfree;
800 /* Configuration info for the coalescing features */
801 unsigned char txcoalescing;
803 unsigned short txcount;
804 unsigned short txtime;
808 * struct gfar_priv_rx_q - per rx queue structure
809 * @rxlock: per queue rx spin lock
810 * @rx_skbuff: skb pointers
811 * @skb_currx: currently use skb pointer
812 * @rx_bd_base: First rx buffer descriptor
813 * @cur_rx: Next free rx ring entry
814 * @qindex: index of this queue
815 * @dev: back pointer to the dev structure
816 * @rx_ring_size: Rx ring size
817 * @rxcoalescing: enable/disable rx-coalescing
818 * @rxic: receive interrupt coalescing vlaue
821 struct gfar_priv_rx_q {
822 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
823 struct sk_buff ** rx_skbuff;
824 dma_addr_t rx_bd_dma_base;
825 struct rxbd8 *rx_bd_base;
826 struct rxbd8 *cur_rx;
827 struct net_device *dev;
830 unsigned int rx_ring_size;
831 /* RX Coalescing values */
832 unsigned char rxcoalescing;
837 * struct gfar_priv_grp - per group structure
838 * @napi: the napi poll function
839 * @priv: back pointer to the priv structure
840 * @regs: the ioremapped register space for this group
841 * @grp_id: group id for this group
842 * @interruptTransmit: The TX interrupt number for this group
843 * @interruptReceive: The RX interrupt number for this group
844 * @interruptError: The ERROR interrupt number for this group
845 * @int_name_tx: tx interrupt name for this group
846 * @int_name_rx: rx interrupt name for this group
847 * @int_name_er: er interrupt name for this group
850 struct gfar_priv_grp {
851 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
852 struct napi_struct napi;
853 struct gfar_private *priv;
854 struct gfar __iomem *regs;
855 unsigned int rx_bit_map;
856 unsigned int tx_bit_map;
857 unsigned int num_tx_queues;
858 unsigned int num_rx_queues;
863 unsigned int interruptTransmit;
864 unsigned int interruptReceive;
865 unsigned int interruptError;
867 char int_name_tx[GFAR_INT_NAME_MAX];
868 char int_name_rx[GFAR_INT_NAME_MAX];
869 char int_name_er[GFAR_INT_NAME_MAX];
872 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
873 * (Ok, that's not so true anymore, but there is a family resemblence)
874 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
875 * and tx_bd_base always point to the currently available buffer.
876 * The dirty_tx tracks the current buffer that is being sent by the
877 * controller. The cur_tx and dirty_tx are equal under both completely
878 * empty and completely full conditions. The empty/ready indicator in
879 * the buffer descriptor determines the actual condition.
881 struct gfar_private {
883 /* Indicates how many tx, rx queues are enabled */
884 unsigned int num_tx_queues;
885 unsigned int num_rx_queues;
887 /* The total tx and rx ring size for the enabled queues */
888 unsigned int total_tx_ring_size;
889 unsigned int total_rx_ring_size;
891 struct device_node *node;
892 struct net_device *ndev;
893 struct of_device *ofdev;
895 struct gfar_priv_grp gfargrp;
896 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
897 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
899 /* RX per device parameters */
900 unsigned int rx_buffer_size;
901 unsigned int rx_stash_size;
902 unsigned int rx_stash_index;
904 struct sk_buff_head rx_recycle;
906 struct vlan_group *vlgrp;
909 /* Hash registers and their width */
910 u32 __iomem *hash_regs[16];
913 /* global parameters */
914 unsigned int fifo_threshold;
915 unsigned int fifo_starve;
916 unsigned int fifo_starve_off;
918 /* Bitfield update lock */
921 phy_interface_t interface;
922 struct device_node *phy_node;
923 struct device_node *tbi_node;
925 unsigned char rx_csum_enable:1,
929 wol_en:1; /* Wake-on-LAN enabled */
930 unsigned short padding;
933 struct phy_device *phydev;
934 struct mii_bus *mii_bus;
941 struct work_struct reset_task;
943 /* Network Statistics */
944 struct gfar_extra_stats extra_stats;
947 static inline u32 gfar_read(volatile unsigned __iomem *addr)
954 static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
959 extern void lock_rx_qs(struct gfar_private *priv);
960 extern void lock_tx_qs(struct gfar_private *priv);
961 extern void unlock_rx_qs(struct gfar_private *priv);
962 extern void unlock_tx_qs(struct gfar_private *priv);
963 extern irqreturn_t gfar_receive(int irq, void *dev_id);
964 extern int startup_gfar(struct net_device *dev);
965 extern void stop_gfar(struct net_device *dev);
966 extern void gfar_halt(struct net_device *dev);
967 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
968 int enable, u32 regnum, u32 read);
969 void gfar_init_sysfs(struct net_device *dev);
971 extern const struct ethtool_ops gfar_ethtool_ops;
973 #endif /* __GIANFAR_H */