drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #include <linux/kernel.h>
  66 #include <linux/string.h>
  67 #include <linux/errno.h>
  68 #include <linux/unistd.h>
  69 #include <linux/slab.h>
  70 #include <linux/interrupt.h>
  71 #include <linux/init.h>
  72 #include <linux/delay.h>
  73 #include <linux/netdevice.h>
  74 #include <linux/etherdevice.h>
  75 #include <linux/skbuff.h>
  76 #include <linux/if_vlan.h>
  77 #include <linux/spinlock.h>
  78 #include <linux/mm.h>
  79 #include <linux/of_mdio.h>
  80 #include <linux/of_platform.h>
  81 #include <linux/ip.h>
  82 #include <linux/tcp.h>
  83 #include <linux/udp.h>
  84 #include <linux/in.h>
  85 #include <linux/net_tstamp.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/reg.h>
  89 #include <asm/irq.h>
  90 #include <asm/uaccess.h>
  91 #include <linux/module.h>
  92 #include <linux/dma-mapping.h>
  93 #include <linux/crc32.h>
  94 #include <linux/mii.h>
  95 #include <linux/phy.h>
  96 #include <linux/phy_fixed.h>
  97 #include <linux/of.h>
  98 #include <linux/of_net.h>
  99
 100 #include "gianfar.h"
 101 #include "fsl_pq_mdio.h"
 102
 103 #define TX_TIMEOUT      (1*HZ)
 104 #undef BRIEF_GFAR_ERRORS
 105 #undef VERBOSE_GFAR_ERRORS
 106
 107 const char gfar_driver_name[] = "Gianfar Ethernet";
 108 const char gfar_driver_version[] = "1.3";
 109
 110 static int gfar_enet_open(struct net_device *dev);
 111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 112 static void gfar_reset_task(struct work_struct *work);
 113 static void gfar_timeout(struct net_device *dev);
 114 static int gfar_close(struct net_device *dev);
 115 struct sk_buff *gfar_new_skb(struct net_device *dev);
 116 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 117                 struct sk_buff *skb);
 118 static int gfar_set_mac_address(struct net_device *dev);
 119 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 120 static irqreturn_t gfar_error(int irq, void *dev_id);
 121 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 122 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 123 static void adjust_link(struct net_device *dev);
 124 static void init_registers(struct net_device *dev);
 125 static int init_phy(struct net_device *dev);
 126 static int gfar_probe(struct platform_device *ofdev);
 127 static int gfar_remove(struct platform_device *ofdev);
 128 static void free_skb_resources(struct gfar_private *priv);
 129 static void gfar_set_multi(struct net_device *dev);
 130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 131 static void gfar_configure_serdes(struct net_device *dev);
 132 static int gfar_poll(struct napi_struct *napi, int budget);
 133 #ifdef CONFIG_NET_POLL_CONTROLLER
 134 static void gfar_netpoll(struct net_device *dev);
 135 #endif
 136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 137 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 139                               int amount_pull);
 140 static void gfar_vlan_rx_register(struct net_device *netdev,
 141                                 struct vlan_group *grp);
 142 void gfar_halt(struct net_device *dev);
 143 static void gfar_halt_nodisable(struct net_device *dev);
 144 void gfar_start(struct net_device *dev);
 145 static void gfar_clear_exact_match(struct net_device *dev);
 146 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 147                                   const u8 *addr);
 148 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 149
 150 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 151 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 152 MODULE_LICENSE("GPL");
 153
 154 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 155                             dma_addr_t buf)
 156 {
 157         u32 lstatus;
 158
 159         bdp->bufPtr = buf;
 160
 161         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 162         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 163                 lstatus |= BD_LFLAG(RXBD_WRAP);
 164
 165         eieio();
 166
 167         bdp->lstatus = lstatus;
 168 }
 169
 170 static int gfar_init_bds(struct net_device *ndev)
 171 {
 172         struct gfar_private *priv = netdev_priv(ndev);
 173         struct gfar_priv_tx_q *tx_queue = NULL;
 174         struct gfar_priv_rx_q *rx_queue = NULL;
 175         struct txbd8 *txbdp;
 176         struct rxbd8 *rxbdp;
 177         int i, j;
 178
 179         for (i = 0; i < priv->num_tx_queues; i++) {
 180                 tx_queue = priv->tx_queue[i];
 181                 /* Initialize some variables in our dev structure */
 182                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 183                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 184                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 185                 tx_queue->skb_curtx = 0;
 186                 tx_queue->skb_dirtytx = 0;
 187
 188                 /* Initialize Transmit Descriptor Ring */
 189                 txbdp = tx_queue->tx_bd_base;
 190                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 191                         txbdp->lstatus = 0;
 192                         txbdp->bufPtr = 0;
 193                         txbdp++;
 194                 }
 195
 196                 /* Set the last descriptor in the ring to indicate wrap */
 197                 txbdp--;
 198                 txbdp->status |= TXBD_WRAP;
 199         }
 200
 201         for (i = 0; i < priv->num_rx_queues; i++) {
 202                 rx_queue = priv->rx_queue[i];
 203                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 204                 rx_queue->skb_currx = 0;
 205                 rxbdp = rx_queue->rx_bd_base;
 206
 207                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 208                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 209
 210                         if (skb) {
 211                                 gfar_init_rxbdp(rx_queue, rxbdp,
 212                                                 rxbdp->bufPtr);
 213                         } else {
 214                                 skb = gfar_new_skb(ndev);
 215                                 if (!skb) {
 216                                         pr_err("%s: Can't allocate RX buffers\n",
 217                                                         ndev->name);
 218                                         goto err_rxalloc_fail;
 219                                 }
 220                                 rx_queue->rx_skbuff[j] = skb;
 221
 222                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 223                         }
 224
 225                         rxbdp++;
 226                 }
 227
 228         }
 229
 230         return 0;
 231
 232 err_rxalloc_fail:
 233         free_skb_resources(priv);
 234         return -ENOMEM;
 235 }
 236
 237 static int gfar_alloc_skb_resources(struct net_device *ndev)
 238 {
 239         void *vaddr;
 240         dma_addr_t addr;
 241         int i, j, k;
 242         struct gfar_private *priv = netdev_priv(ndev);
 243         struct device *dev = &priv->ofdev->dev;
 244         struct gfar_priv_tx_q *tx_queue = NULL;
 245         struct gfar_priv_rx_q *rx_queue = NULL;
 246
 247         priv->total_tx_ring_size = 0;
 248         for (i = 0; i < priv->num_tx_queues; i++)
 249                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 250
 251         priv->total_rx_ring_size = 0;
 252         for (i = 0; i < priv->num_rx_queues; i++)
 253                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 254
 255         /* Allocate memory for the buffer descriptors */
 256         vaddr = dma_alloc_coherent(dev,
 257                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 258                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 259                         &addr, GFP_KERNEL);
 260         if (!vaddr) {
 261                 if (netif_msg_ifup(priv))
 262                         pr_err("%s: Could not allocate buffer descriptors!\n",
 263                                ndev->name);
 264                 return -ENOMEM;
 265         }
 266
 267         for (i = 0; i < priv->num_tx_queues; i++) {
 268                 tx_queue = priv->tx_queue[i];
 269                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 270                 tx_queue->tx_bd_dma_base = addr;
 271                 tx_queue->dev = ndev;
 272                 /* enet DMA only understands physical addresses */
 273                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 274                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 275         }
 276
 277         /* Start the rx descriptor ring where the tx ring leaves off */
 278         for (i = 0; i < priv->num_rx_queues; i++) {
 279                 rx_queue = priv->rx_queue[i];
 280                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 281                 rx_queue->rx_bd_dma_base = addr;
 282                 rx_queue->dev = ndev;
 283                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 284                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 285         }
 286
 287         /* Setup the skbuff rings */
 288         for (i = 0; i < priv->num_tx_queues; i++) {
 289                 tx_queue = priv->tx_queue[i];
 290                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 291                                   tx_queue->tx_ring_size, GFP_KERNEL);
 292                 if (!tx_queue->tx_skbuff) {
 293                         if (netif_msg_ifup(priv))
 294                                 pr_err("%s: Could not allocate tx_skbuff\n",
 295                                                 ndev->name);
 296                         goto cleanup;
 297                 }
 298
 299                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 300                         tx_queue->tx_skbuff[k] = NULL;
 301         }
 302
 303         for (i = 0; i < priv->num_rx_queues; i++) {
 304                 rx_queue = priv->rx_queue[i];
 305                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 306                                   rx_queue->rx_ring_size, GFP_KERNEL);
 307
 308                 if (!rx_queue->rx_skbuff) {
 309                         if (netif_msg_ifup(priv))
 310                                 pr_err("%s: Could not allocate rx_skbuff\n",
 311                                        ndev->name);
 312                         goto cleanup;
 313                 }
 314
 315                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 316                         rx_queue->rx_skbuff[j] = NULL;
 317         }
 318
 319         if (gfar_init_bds(ndev))
 320                 goto cleanup;
 321
 322         return 0;
 323
 324 cleanup:
 325         free_skb_resources(priv);
 326         return -ENOMEM;
 327 }
 328
 329 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 330 {
 331         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 332         u32 __iomem *baddr;
 333         int i;
 334
 335         baddr = &regs->tbase0;
 336         for(i = 0; i < priv->num_tx_queues; i++) {
 337                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 338                 baddr   += 2;
 339         }
 340
 341         baddr = &regs->rbase0;
 342         for(i = 0; i < priv->num_rx_queues; i++) {
 343                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 344                 baddr   += 2;
 345         }
 346 }
 347
 348 static void gfar_init_mac(struct net_device *ndev)
 349 {
 350         struct gfar_private *priv = netdev_priv(ndev);
 351         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 352         u32 rctrl = 0;
 353         u32 tctrl = 0;
 354         u32 attrs = 0;
 355
 356         /* write the tx/rx base registers */
 357         gfar_init_tx_rx_base(priv);
 358
 359         /* Configure the coalescing support */
 360         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 361
 362         if (priv->rx_filer_enable) {
 363                 rctrl |= RCTRL_FILREN;
 364                 /* Program the RIR0 reg with the required distribution */
 365                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 366         }
 367
 368         if (priv->rx_csum_enable)
 369                 rctrl |= RCTRL_CHECKSUMMING;
 370
 371         if (priv->extended_hash) {
 372                 rctrl |= RCTRL_EXTHASH;
 373
 374                 gfar_clear_exact_match(ndev);
 375                 rctrl |= RCTRL_EMEN;
 376         }
 377
 378         if (priv->padding) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(priv->padding);
 381         }
 382
 383         /* Insert receive time stamps into padding alignment bytes */
 384         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 385                 rctrl &= ~RCTRL_PAL_MASK;
 386                 rctrl |= RCTRL_PADDING(8);
 387                 priv->padding = 8;
 388         }
 389
 390         /* Enable HW time stamping if requested from user space */
 391         if (priv->hwts_rx_en)
 392                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 393
 394         /* keep vlan related bits if it's enabled */
 395         if (priv->vlgrp) {
 396                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 397                 tctrl |= TCTRL_VLINS;
 398         }
 399
 400         /* Init rctrl based on our settings */
 401         gfar_write(&regs->rctrl, rctrl);
 402
 403         if (ndev->features & NETIF_F_IP_CSUM)
 404                 tctrl |= TCTRL_INIT_CSUM;
 405
 406         tctrl |= TCTRL_TXSCHED_PRIO;
 407
 408         gfar_write(&regs->tctrl, tctrl);
 409
 410         /* Set the extraction length and index */
 411         attrs = ATTRELI_EL(priv->rx_stash_size) |
 412                 ATTRELI_EI(priv->rx_stash_index);
 413
 414         gfar_write(&regs->attreli, attrs);
 415
 416         /* Start with defaults, and add stashing or locking
 417          * depending on the approprate variables */
 418         attrs = ATTR_INIT_SETTINGS;
 419
 420         if (priv->bd_stash_en)
 421                 attrs |= ATTR_BDSTASH;
 422
 423         if (priv->rx_stash_size != 0)
 424                 attrs |= ATTR_BUFSTASH;
 425
 426         gfar_write(&regs->attr, attrs);
 427
 428         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 429         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 430         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 431 }
 432
 433 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 434 {
 435         struct gfar_private *priv = netdev_priv(dev);
 436         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 437         unsigned long tx_packets = 0, tx_bytes = 0;
 438         int i = 0;
 439
 440         for (i = 0; i < priv->num_rx_queues; i++) {
 441                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 442                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
 443                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 444         }
 445
 446         dev->stats.rx_packets = rx_packets;
 447         dev->stats.rx_bytes = rx_bytes;
 448         dev->stats.rx_dropped = rx_dropped;
 449
 450         for (i = 0; i < priv->num_tx_queues; i++) {
 451                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 452                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 453         }
 454
 455         dev->stats.tx_bytes = tx_bytes;
 456         dev->stats.tx_packets = tx_packets;
 457
 458         return &dev->stats;
 459 }
 460
 461 static const struct net_device_ops gfar_netdev_ops = {
 462         .ndo_open = gfar_enet_open,
 463         .ndo_start_xmit = gfar_start_xmit,
 464         .ndo_stop = gfar_close,
 465         .ndo_change_mtu = gfar_change_mtu,
 466         .ndo_set_multicast_list = gfar_set_multi,
 467         .ndo_tx_timeout = gfar_timeout,
 468         .ndo_do_ioctl = gfar_ioctl,
 469         .ndo_get_stats = gfar_get_stats,
 470         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 471         .ndo_set_mac_address = eth_mac_addr,
 472         .ndo_validate_addr = eth_validate_addr,
 473 #ifdef CONFIG_NET_POLL_CONTROLLER
 474         .ndo_poll_controller = gfar_netpoll,
 475 #endif
 476 };
 477
 478 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 479 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 480
 481 void lock_rx_qs(struct gfar_private *priv)
 482 {
 483         int i = 0x0;
 484
 485         for (i = 0; i < priv->num_rx_queues; i++)
 486                 spin_lock(&priv->rx_queue[i]->rxlock);
 487 }
 488
 489 void lock_tx_qs(struct gfar_private *priv)
 490 {
 491         int i = 0x0;
 492
 493         for (i = 0; i < priv->num_tx_queues; i++)
 494                 spin_lock(&priv->tx_queue[i]->txlock);
 495 }
 496
 497 void unlock_rx_qs(struct gfar_private *priv)
 498 {
 499         int i = 0x0;
 500
 501         for (i = 0; i < priv->num_rx_queues; i++)
 502                 spin_unlock(&priv->rx_queue[i]->rxlock);
 503 }
 504
 505 void unlock_tx_qs(struct gfar_private *priv)
 506 {
 507         int i = 0x0;
 508
 509         for (i = 0; i < priv->num_tx_queues; i++)
 510                 spin_unlock(&priv->tx_queue[i]->txlock);
 511 }
 512
 513 /* Returns 1 if incoming frames use an FCB */
 514 static inline int gfar_uses_fcb(struct gfar_private *priv)
 515 {
 516         return priv->vlgrp || priv->rx_csum_enable ||
 517                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 518 }
 519
 520 static void free_tx_pointers(struct gfar_private *priv)
 521 {
 522         int i = 0;
 523
 524         for (i = 0; i < priv->num_tx_queues; i++)
 525                 kfree(priv->tx_queue[i]);
 526 }
 527
 528 static void free_rx_pointers(struct gfar_private *priv)
 529 {
 530         int i = 0;
 531
 532         for (i = 0; i < priv->num_rx_queues; i++)
 533                 kfree(priv->rx_queue[i]);
 534 }
 535
 536 static void unmap_group_regs(struct gfar_private *priv)
 537 {
 538         int i = 0;
 539
 540         for (i = 0; i < MAXGROUPS; i++)
 541                 if (priv->gfargrp[i].regs)
 542                         iounmap(priv->gfargrp[i].regs);
 543 }
 544
 545 static void disable_napi(struct gfar_private *priv)
 546 {
 547         int i = 0;
 548
 549         for (i = 0; i < priv->num_grps; i++)
 550                 napi_disable(&priv->gfargrp[i].napi);
 551 }
 552
 553 static void enable_napi(struct gfar_private *priv)
 554 {
 555         int i = 0;
 556
 557         for (i = 0; i < priv->num_grps; i++)
 558                 napi_enable(&priv->gfargrp[i].napi);
 559 }
 560
 561 static int gfar_parse_group(struct device_node *np,
 562                 struct gfar_private *priv, const char *model)
 563 {
 564         u32 *queue_mask;
 565
 566         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 567         if (!priv->gfargrp[priv->num_grps].regs)
 568                 return -ENOMEM;
 569
 570         priv->gfargrp[priv->num_grps].interruptTransmit =
 571                         irq_of_parse_and_map(np, 0);
 572
 573         /* If we aren't the FEC we have multiple interrupts */
 574         if (model && strcasecmp(model, "FEC")) {
 575                 priv->gfargrp[priv->num_grps].interruptReceive =
 576                         irq_of_parse_and_map(np, 1);
 577                 priv->gfargrp[priv->num_grps].interruptError =
 578                         irq_of_parse_and_map(np,2);
 579                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 580                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 581                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 582                         return -EINVAL;
 583         }
 584
 585         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 586         priv->gfargrp[priv->num_grps].priv = priv;
 587         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 588         if(priv->mode == MQ_MG_MODE) {
 589                 queue_mask = (u32 *)of_get_property(np,
 590                                         "fsl,rx-bit-map", NULL);
 591                 priv->gfargrp[priv->num_grps].rx_bit_map =
 592                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 593                 queue_mask = (u32 *)of_get_property(np,
 594                                         "fsl,tx-bit-map", NULL);
 595                 priv->gfargrp[priv->num_grps].tx_bit_map =
 596                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 597         } else {
 598                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 599                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 600         }
 601         priv->num_grps++;
 602
 603         return 0;
 604 }
 605
 606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 607 {
 608         const char *model;
 609         const char *ctype;
 610         const void *mac_addr;
 611         int err = 0, i;
 612         struct net_device *dev = NULL;
 613         struct gfar_private *priv = NULL;
 614         struct device_node *np = ofdev->dev.of_node;
 615         struct device_node *child = NULL;
 616         const u32 *stash;
 617         const u32 *stash_len;
 618         const u32 *stash_idx;
 619         unsigned int num_tx_qs, num_rx_qs;
 620         u32 *tx_queues, *rx_queues;
 621
 622         if (!np || !of_device_is_available(np))
 623                 return -ENODEV;
 624
 625         /* parse the num of tx and rx queues */
 626         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 627         num_tx_qs = tx_queues ? *tx_queues : 1;
 628
 629         if (num_tx_qs > MAX_TX_QS) {
 630                 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 631                                 num_tx_qs, MAX_TX_QS);
 632                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 633                 return -EINVAL;
 634         }
 635
 636         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 637         num_rx_qs = rx_queues ? *rx_queues : 1;
 638
 639         if (num_rx_qs > MAX_RX_QS) {
 640                 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 641                                 num_tx_qs, MAX_TX_QS);
 642                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 643                 return -EINVAL;
 644         }
 645
 646         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 647         dev = *pdev;
 648         if (NULL == dev)
 649                 return -ENOMEM;
 650
 651         priv = netdev_priv(dev);
 652         priv->node = ofdev->dev.of_node;
 653         priv->ndev = dev;
 654
 655         priv->num_tx_queues = num_tx_qs;
 656         netif_set_real_num_rx_queues(dev, num_rx_qs);
 657         priv->num_rx_queues = num_rx_qs;
 658         priv->num_grps = 0x0;
 659
 660         model = of_get_property(np, "model", NULL);
 661
 662         for (i = 0; i < MAXGROUPS; i++)
 663                 priv->gfargrp[i].regs = NULL;
 664
 665         /* Parse and initialize group specific information */
 666         if (of_device_is_compatible(np, "fsl,etsec2")) {
 667                 priv->mode = MQ_MG_MODE;
 668                 for_each_child_of_node(np, child) {
 669                         err = gfar_parse_group(child, priv, model);
 670                         if (err)
 671                                 goto err_grp_init;
 672                 }
 673         } else {
 674                 priv->mode = SQ_SG_MODE;
 675                 err = gfar_parse_group(np, priv, model);
 676                 if(err)
 677                         goto err_grp_init;
 678         }
 679
 680         for (i = 0; i < priv->num_tx_queues; i++)
 681                priv->tx_queue[i] = NULL;
 682         for (i = 0; i < priv->num_rx_queues; i++)
 683                 priv->rx_queue[i] = NULL;
 684
 685         for (i = 0; i < priv->num_tx_queues; i++) {
 686                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 687                                             GFP_KERNEL);
 688                 if (!priv->tx_queue[i]) {
 689                         err = -ENOMEM;
 690                         goto tx_alloc_failed;
 691                 }
 692                 priv->tx_queue[i]->tx_skbuff = NULL;
 693                 priv->tx_queue[i]->qindex = i;
 694                 priv->tx_queue[i]->dev = dev;
 695                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 696         }
 697
 698         for (i = 0; i < priv->num_rx_queues; i++) {
 699                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 700                                             GFP_KERNEL);
 701                 if (!priv->rx_queue[i]) {
 702                         err = -ENOMEM;
 703                         goto rx_alloc_failed;
 704                 }
 705                 priv->rx_queue[i]->rx_skbuff = NULL;
 706                 priv->rx_queue[i]->qindex = i;
 707                 priv->rx_queue[i]->dev = dev;
 708                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 709         }
 710
 711
 712         stash = of_get_property(np, "bd-stash", NULL);
 713
 714         if (stash) {
 715                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 716                 priv->bd_stash_en = 1;
 717         }
 718
 719         stash_len = of_get_property(np, "rx-stash-len", NULL);
 720
 721         if (stash_len)
 722                 priv->rx_stash_size = *stash_len;
 723
 724         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 725
 726         if (stash_idx)
 727                 priv->rx_stash_index = *stash_idx;
 728
 729         if (stash_len || stash_idx)
 730                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 731
 732         mac_addr = of_get_mac_address(np);
 733         if (mac_addr)
 734                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 735
 736         if (model && !strcasecmp(model, "TSEC"))
 737                 priv->device_flags =
 738                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 739                         FSL_GIANFAR_DEV_HAS_COALESCE |
 740                         FSL_GIANFAR_DEV_HAS_RMON |
 741                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 742         if (model && !strcasecmp(model, "eTSEC"))
 743                 priv->device_flags =
 744                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 745                         FSL_GIANFAR_DEV_HAS_COALESCE |
 746                         FSL_GIANFAR_DEV_HAS_RMON |
 747                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 748                         FSL_GIANFAR_DEV_HAS_PADDING |
 749                         FSL_GIANFAR_DEV_HAS_CSUM |
 750                         FSL_GIANFAR_DEV_HAS_VLAN |
 751                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 752                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 753                         FSL_GIANFAR_DEV_HAS_TIMER;
 754
 755         ctype = of_get_property(np, "phy-connection-type", NULL);
 756
 757         /* We only care about rgmii-id.  The rest are autodetected */
 758         if (ctype && !strcmp(ctype, "rgmii-id"))
 759                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 760         else
 761                 priv->interface = PHY_INTERFACE_MODE_MII;
 762
 763         if (of_get_property(np, "fsl,magic-packet", NULL))
 764                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 765
 766         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 767
 768         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 769         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 770
 771         return 0;
 772
 773 rx_alloc_failed:
 774         free_rx_pointers(priv);
 775 tx_alloc_failed:
 776         free_tx_pointers(priv);
 777 err_grp_init:
 778         unmap_group_regs(priv);
 779         free_netdev(dev);
 780         return err;
 781 }
 782
 783 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 784                         struct ifreq *ifr, int cmd)
 785 {
 786         struct hwtstamp_config config;
 787         struct gfar_private *priv = netdev_priv(netdev);
 788
 789         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 790                 return -EFAULT;
 791
 792         /* reserved for future extensions */
 793         if (config.flags)
 794                 return -EINVAL;
 795
 796         switch (config.tx_type) {
 797         case HWTSTAMP_TX_OFF:
 798                 priv->hwts_tx_en = 0;
 799                 break;
 800         case HWTSTAMP_TX_ON:
 801                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 802                         return -ERANGE;
 803                 priv->hwts_tx_en = 1;
 804                 break;
 805         default:
 806                 return -ERANGE;
 807         }
 808
 809         switch (config.rx_filter) {
 810         case HWTSTAMP_FILTER_NONE:
 811                 if (priv->hwts_rx_en) {
 812                         stop_gfar(netdev);
 813                         priv->hwts_rx_en = 0;
 814                         startup_gfar(netdev);
 815                 }
 816                 break;
 817         default:
 818                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 819                         return -ERANGE;
 820                 if (!priv->hwts_rx_en) {
 821                         stop_gfar(netdev);
 822                         priv->hwts_rx_en = 1;
 823                         startup_gfar(netdev);
 824                 }
 825                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 826                 break;
 827         }
 828
 829         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 830                 -EFAULT : 0;
 831 }
 832
 833 /* Ioctl MII Interface */
 834 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 835 {
 836         struct gfar_private *priv = netdev_priv(dev);
 837
 838         if (!netif_running(dev))
 839                 return -EINVAL;
 840
 841         if (cmd == SIOCSHWTSTAMP)
 842                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 843
 844         if (!priv->phydev)
 845                 return -ENODEV;
 846
 847         return phy_mii_ioctl(priv->phydev, rq, cmd);
 848 }
 849
 850 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 851 {
 852         unsigned int new_bit_map = 0x0;
 853         int mask = 0x1 << (max_qs - 1), i;
 854         for (i = 0; i < max_qs; i++) {
 855                 if (bit_map & mask)
 856                         new_bit_map = new_bit_map + (1 << i);
 857                 mask = mask >> 0x1;
 858         }
 859         return new_bit_map;
 860 }
 861
 862 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 863                                    u32 class)
 864 {
 865         u32 rqfpr = FPR_FILER_MASK;
 866         u32 rqfcr = 0x0;
 867
 868         rqfar--;
 869         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 870         ftp_rqfpr[rqfar] = rqfpr;
 871         ftp_rqfcr[rqfar] = rqfcr;
 872         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 873
 874         rqfar--;
 875         rqfcr = RQFCR_CMP_NOMATCH;
 876         ftp_rqfpr[rqfar] = rqfpr;
 877         ftp_rqfcr[rqfar] = rqfcr;
 878         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 879
 880         rqfar--;
 881         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 882         rqfpr = class;
 883         ftp_rqfcr[rqfar] = rqfcr;
 884         ftp_rqfpr[rqfar] = rqfpr;
 885         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 886
 887         rqfar--;
 888         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 889         rqfpr = class;
 890         ftp_rqfcr[rqfar] = rqfcr;
 891         ftp_rqfpr[rqfar] = rqfpr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         return rqfar;
 895 }
 896
 897 static void gfar_init_filer_table(struct gfar_private *priv)
 898 {
 899         int i = 0x0;
 900         u32 rqfar = MAX_FILER_IDX;
 901         u32 rqfcr = 0x0;
 902         u32 rqfpr = FPR_FILER_MASK;
 903
 904         /* Default rule */
 905         rqfcr = RQFCR_CMP_MATCH;
 906         ftp_rqfcr[rqfar] = rqfcr;
 907         ftp_rqfpr[rqfar] = rqfpr;
 908         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 909
 910         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 911         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 912         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 913         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 914         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 915         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 916
 917         /* cur_filer_idx indicated the first non-masked rule */
 918         priv->cur_filer_idx = rqfar;
 919
 920         /* Rest are masked rules */
 921         rqfcr = RQFCR_CMP_NOMATCH;
 922         for (i = 0; i < rqfar; i++) {
 923                 ftp_rqfcr[i] = rqfcr;
 924                 ftp_rqfpr[i] = rqfpr;
 925                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 926         }
 927 }
 928
 929 static void gfar_detect_errata(struct gfar_private *priv)
 930 {
 931         struct device *dev = &priv->ofdev->dev;
 932         unsigned int pvr = mfspr(SPRN_PVR);
 933         unsigned int svr = mfspr(SPRN_SVR);
 934         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 935         unsigned int rev = svr & 0xffff;
 936
 937         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 938         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 939                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 940                 priv->errata |= GFAR_ERRATA_74;
 941
 942         /* MPC8313 and MPC837x all rev */
 943         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 944                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 945                 priv->errata |= GFAR_ERRATA_76;
 946
 947         /* MPC8313 and MPC837x all rev */
 948         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 949                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 950                 priv->errata |= GFAR_ERRATA_A002;
 951
 952         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 953         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 954                         (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 955                 priv->errata |= GFAR_ERRATA_12;
 956
 957         if (priv->errata)
 958                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 959                          priv->errata);
 960 }
 961
 962 /* Set up the ethernet device structure, private data,
 963  * and anything else we need before we start */
 964 static int gfar_probe(struct platform_device *ofdev)
 965 {
 966         u32 tempval;
 967         struct net_device *dev = NULL;
 968         struct gfar_private *priv = NULL;
 969         struct gfar __iomem *regs = NULL;
 970         int err = 0, i, grp_idx = 0;
 971         int len_devname;
 972         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 973         u32 isrg = 0;
 974         u32 __iomem *baddr;
 975
 976         err = gfar_of_init(ofdev, &dev);
 977
 978         if (err)
 979                 return err;
 980
 981         priv = netdev_priv(dev);
 982         priv->ndev = dev;
 983         priv->ofdev = ofdev;
 984         priv->node = ofdev->dev.of_node;
 985         SET_NETDEV_DEV(dev, &ofdev->dev);
 986
 987         spin_lock_init(&priv->bflock);
 988         INIT_WORK(&priv->reset_task, gfar_reset_task);
 989
 990         dev_set_drvdata(&ofdev->dev, priv);
 991         regs = priv->gfargrp[0].regs;
 992
 993         gfar_detect_errata(priv);
 994
 995         /* Stop the DMA engine now, in case it was running before */
 996         /* (The firmware could have used it, and left it running). */
 997         gfar_halt(dev);
 998
 999         /* Reset MAC layer */
1000         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1001
1002         /* We need to delay at least 3 TX clocks */
1003         udelay(2);
1004
1005         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1006         gfar_write(&regs->maccfg1, tempval);
1007
1008         /* Initialize MACCFG2. */
1009         tempval = MACCFG2_INIT_SETTINGS;
1010         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1011                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1012         gfar_write(&regs->maccfg2, tempval);
1013
1014         /* Initialize ECNTRL */
1015         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1016
1017         /* Set the dev->base_addr to the gfar reg region */
1018         dev->base_addr = (unsigned long) regs;
1019
1020         SET_NETDEV_DEV(dev, &ofdev->dev);
1021
1022         /* Fill in the dev structure */
1023         dev->watchdog_timeo = TX_TIMEOUT;
1024         dev->mtu = 1500;
1025         dev->netdev_ops = &gfar_netdev_ops;
1026         dev->ethtool_ops = &gfar_ethtool_ops;
1027
1028         /* Register for napi ...We are registering NAPI for each grp */
1029         for (i = 0; i < priv->num_grps; i++)
1030                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1031
1032         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1033                 priv->rx_csum_enable = 1;
1034                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
1035         } else
1036                 priv->rx_csum_enable = 0;
1037
1038         priv->vlgrp = NULL;
1039
1040         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1041                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1042
1043         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1044                 priv->extended_hash = 1;
1045                 priv->hash_width = 9;
1046
1047                 priv->hash_regs[0] = &regs->igaddr0;
1048                 priv->hash_regs[1] = &regs->igaddr1;
1049                 priv->hash_regs[2] = &regs->igaddr2;
1050                 priv->hash_regs[3] = &regs->igaddr3;
1051                 priv->hash_regs[4] = &regs->igaddr4;
1052                 priv->hash_regs[5] = &regs->igaddr5;
1053                 priv->hash_regs[6] = &regs->igaddr6;
1054                 priv->hash_regs[7] = &regs->igaddr7;
1055                 priv->hash_regs[8] = &regs->gaddr0;
1056                 priv->hash_regs[9] = &regs->gaddr1;
1057                 priv->hash_regs[10] = &regs->gaddr2;
1058                 priv->hash_regs[11] = &regs->gaddr3;
1059                 priv->hash_regs[12] = &regs->gaddr4;
1060                 priv->hash_regs[13] = &regs->gaddr5;
1061                 priv->hash_regs[14] = &regs->gaddr6;
1062                 priv->hash_regs[15] = &regs->gaddr7;
1063
1064         } else {
1065                 priv->extended_hash = 0;
1066                 priv->hash_width = 8;
1067
1068                 priv->hash_regs[0] = &regs->gaddr0;
1069                 priv->hash_regs[1] = &regs->gaddr1;
1070                 priv->hash_regs[2] = &regs->gaddr2;
1071                 priv->hash_regs[3] = &regs->gaddr3;
1072                 priv->hash_regs[4] = &regs->gaddr4;
1073                 priv->hash_regs[5] = &regs->gaddr5;
1074                 priv->hash_regs[6] = &regs->gaddr6;
1075                 priv->hash_regs[7] = &regs->gaddr7;
1076         }
1077
1078         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1079                 priv->padding = DEFAULT_PADDING;
1080         else
1081                 priv->padding = 0;
1082
1083         if (dev->features & NETIF_F_IP_CSUM ||
1084                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1085                 dev->hard_header_len += GMAC_FCB_LEN;
1086
1087         /* Program the isrg regs only if number of grps > 1 */
1088         if (priv->num_grps > 1) {
1089                 baddr = &regs->isrg0;
1090                 for (i = 0; i < priv->num_grps; i++) {
1091                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1092                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1093                         gfar_write(baddr, isrg);
1094                         baddr++;
1095                         isrg = 0x0;
1096                 }
1097         }
1098
1099         /* Need to reverse the bit maps as  bit_map's MSB is q0
1100          * but, for_each_set_bit parses from right to left, which
1101          * basically reverses the queue numbers */
1102         for (i = 0; i< priv->num_grps; i++) {
1103                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1104                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1105                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1106                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1107         }
1108
1109         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1110          * also assign queues to groups */
1111         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1112                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1113                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1114                                 priv->num_rx_queues) {
1115                         priv->gfargrp[grp_idx].num_rx_queues++;
1116                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1117                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1118                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1119                 }
1120                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1121                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1122                                 priv->num_tx_queues) {
1123                         priv->gfargrp[grp_idx].num_tx_queues++;
1124                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1125                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1126                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1127                 }
1128                 priv->gfargrp[grp_idx].rstat = rstat;
1129                 priv->gfargrp[grp_idx].tstat = tstat;
1130                 rstat = tstat =0;
1131         }
1132
1133         gfar_write(&regs->rqueue, rqueue);
1134         gfar_write(&regs->tqueue, tqueue);
1135
1136         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1137
1138         /* Initializing some of the rx/tx queue level parameters */
1139         for (i = 0; i < priv->num_tx_queues; i++) {
1140                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1141                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1142                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1143                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1144         }
1145
1146         for (i = 0; i < priv->num_rx_queues; i++) {
1147                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1148                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1149                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1150         }
1151
1152         /* enable filer if using multiple RX queues*/
1153         if(priv->num_rx_queues > 1)
1154                 priv->rx_filer_enable = 1;
1155         /* Enable most messages by default */
1156         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1157
1158         /* Carrier starts down, phylib will bring it up */
1159         netif_carrier_off(dev);
1160
1161         err = register_netdev(dev);
1162
1163         if (err) {
1164                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1165                                 dev->name);
1166                 goto register_fail;
1167         }
1168
1169         device_init_wakeup(&dev->dev,
1170                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1171
1172         /* fill out IRQ number and name fields */
1173         len_devname = strlen(dev->name);
1174         for (i = 0; i < priv->num_grps; i++) {
1175                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1176                                 len_devname);
1177                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1178                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1179                                 "_g", sizeof("_g"));
1180                         priv->gfargrp[i].int_name_tx[
1181                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1182                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1183                                 priv->gfargrp[i].int_name_tx)],
1184                                 "_tx", sizeof("_tx") + 1);
1185
1186                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1187                                         len_devname);
1188                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1189                                         "_g", sizeof("_g"));
1190                         priv->gfargrp[i].int_name_rx[
1191                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1192                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1193                                 priv->gfargrp[i].int_name_rx)],
1194                                 "_rx", sizeof("_rx") + 1);
1195
1196                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1197                                         len_devname);
1198                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1199                                 "_g", sizeof("_g"));
1200                         priv->gfargrp[i].int_name_er[strlen(
1201                                         priv->gfargrp[i].int_name_er)] = i+48;
1202                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1203                                 priv->gfargrp[i].int_name_er)],
1204                                 "_er", sizeof("_er") + 1);
1205                 } else
1206                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1207         }
1208
1209         /* Initialize the filer table */
1210         gfar_init_filer_table(priv);
1211
1212         /* Create all the sysfs files */
1213         gfar_init_sysfs(dev);
1214
1215         /* Print out the device info */
1216         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1217
1218         /* Even more device info helps when determining which kernel */
1219         /* provided which set of benchmarks. */
1220         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1221         for (i = 0; i < priv->num_rx_queues; i++)
1222                 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1223                         dev->name, i, priv->rx_queue[i]->rx_ring_size);
1224         for(i = 0; i < priv->num_tx_queues; i++)
1225                  printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1226                         dev->name, i, priv->tx_queue[i]->tx_ring_size);
1227
1228         return 0;
1229
1230 register_fail:
1231         unmap_group_regs(priv);
1232         free_tx_pointers(priv);
1233         free_rx_pointers(priv);
1234         if (priv->phy_node)
1235                 of_node_put(priv->phy_node);
1236         if (priv->tbi_node)
1237                 of_node_put(priv->tbi_node);
1238         free_netdev(dev);
1239         return err;
1240 }
1241
1242 static int gfar_remove(struct platform_device *ofdev)
1243 {
1244         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1245
1246         if (priv->phy_node)
1247                 of_node_put(priv->phy_node);
1248         if (priv->tbi_node)
1249                 of_node_put(priv->tbi_node);
1250
1251         dev_set_drvdata(&ofdev->dev, NULL);
1252
1253         unregister_netdev(priv->ndev);
1254         unmap_group_regs(priv);
1255         free_netdev(priv->ndev);
1256
1257         return 0;
1258 }
1259
1260 #ifdef CONFIG_PM
1261
1262 static int gfar_suspend(struct device *dev)
1263 {
1264         struct gfar_private *priv = dev_get_drvdata(dev);
1265         struct net_device *ndev = priv->ndev;
1266         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1267         unsigned long flags;
1268         u32 tempval;
1269
1270         int magic_packet = priv->wol_en &&
1271                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1272
1273         netif_device_detach(ndev);
1274
1275         if (netif_running(ndev)) {
1276
1277                 local_irq_save(flags);
1278                 lock_tx_qs(priv);
1279                 lock_rx_qs(priv);
1280
1281                 gfar_halt_nodisable(ndev);
1282
1283                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1284                 tempval = gfar_read(&regs->maccfg1);
1285
1286                 tempval &= ~MACCFG1_TX_EN;
1287
1288                 if (!magic_packet)
1289                         tempval &= ~MACCFG1_RX_EN;
1290
1291                 gfar_write(&regs->maccfg1, tempval);
1292
1293                 unlock_rx_qs(priv);
1294                 unlock_tx_qs(priv);
1295                 local_irq_restore(flags);
1296
1297                 disable_napi(priv);
1298
1299                 if (magic_packet) {
1300                         /* Enable interrupt on Magic Packet */
1301                         gfar_write(&regs->imask, IMASK_MAG);
1302
1303                         /* Enable Magic Packet mode */
1304                         tempval = gfar_read(&regs->maccfg2);
1305                         tempval |= MACCFG2_MPEN;
1306                         gfar_write(&regs->maccfg2, tempval);
1307                 } else {
1308                         phy_stop(priv->phydev);
1309                 }
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int gfar_resume(struct device *dev)
1316 {
1317         struct gfar_private *priv = dev_get_drvdata(dev);
1318         struct net_device *ndev = priv->ndev;
1319         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1320         unsigned long flags;
1321         u32 tempval;
1322         int magic_packet = priv->wol_en &&
1323                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1324
1325         if (!netif_running(ndev)) {
1326                 netif_device_attach(ndev);
1327                 return 0;
1328         }
1329
1330         if (!magic_packet && priv->phydev)
1331                 phy_start(priv->phydev);
1332
1333         /* Disable Magic Packet mode, in case something
1334          * else woke us up.
1335          */
1336         local_irq_save(flags);
1337         lock_tx_qs(priv);
1338         lock_rx_qs(priv);
1339
1340         tempval = gfar_read(&regs->maccfg2);
1341         tempval &= ~MACCFG2_MPEN;
1342         gfar_write(&regs->maccfg2, tempval);
1343
1344         gfar_start(ndev);
1345
1346         unlock_rx_qs(priv);
1347         unlock_tx_qs(priv);
1348         local_irq_restore(flags);
1349
1350         netif_device_attach(ndev);
1351
1352         enable_napi(priv);
1353
1354         return 0;
1355 }
1356
1357 static int gfar_restore(struct device *dev)
1358 {
1359         struct gfar_private *priv = dev_get_drvdata(dev);
1360         struct net_device *ndev = priv->ndev;
1361
1362         if (!netif_running(ndev))
1363                 return 0;
1364
1365         gfar_init_bds(ndev);
1366         init_registers(ndev);
1367         gfar_set_mac_address(ndev);
1368         gfar_init_mac(ndev);
1369         gfar_start(ndev);
1370
1371         priv->oldlink = 0;
1372         priv->oldspeed = 0;
1373         priv->oldduplex = -1;
1374
1375         if (priv->phydev)
1376                 phy_start(priv->phydev);
1377
1378         netif_device_attach(ndev);
1379         enable_napi(priv);
1380
1381         return 0;
1382 }
1383
1384 static struct dev_pm_ops gfar_pm_ops = {
1385         .suspend = gfar_suspend,
1386         .resume = gfar_resume,
1387         .freeze = gfar_suspend,
1388         .thaw = gfar_resume,
1389         .restore = gfar_restore,
1390 };
1391
1392 #define GFAR_PM_OPS (&gfar_pm_ops)
1393
1394 #else
1395
1396 #define GFAR_PM_OPS NULL
1397
1398 #endif
1399
1400 /* Reads the controller's registers to determine what interface
1401  * connects it to the PHY.
1402  */
1403 static phy_interface_t gfar_get_interface(struct net_device *dev)
1404 {
1405         struct gfar_private *priv = netdev_priv(dev);
1406         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1407         u32 ecntrl;
1408
1409         ecntrl = gfar_read(&regs->ecntrl);
1410
1411         if (ecntrl & ECNTRL_SGMII_MODE)
1412                 return PHY_INTERFACE_MODE_SGMII;
1413
1414         if (ecntrl & ECNTRL_TBI_MODE) {
1415                 if (ecntrl & ECNTRL_REDUCED_MODE)
1416                         return PHY_INTERFACE_MODE_RTBI;
1417                 else
1418                         return PHY_INTERFACE_MODE_TBI;
1419         }
1420
1421         if (ecntrl & ECNTRL_REDUCED_MODE) {
1422                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1423                         return PHY_INTERFACE_MODE_RMII;
1424                 else {
1425                         phy_interface_t interface = priv->interface;
1426
1427                         /*
1428                          * This isn't autodetected right now, so it must
1429                          * be set by the device tree or platform code.
1430                          */
1431                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1432                                 return PHY_INTERFACE_MODE_RGMII_ID;
1433
1434                         return PHY_INTERFACE_MODE_RGMII;
1435                 }
1436         }
1437
1438         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1439                 return PHY_INTERFACE_MODE_GMII;
1440
1441         return PHY_INTERFACE_MODE_MII;
1442 }
1443
1444
1445 /* Initializes driver's PHY state, and attaches to the PHY.
1446  * Returns 0 on success.
1447  */
1448 static int init_phy(struct net_device *dev)
1449 {
1450         struct gfar_private *priv = netdev_priv(dev);
1451         uint gigabit_support =
1452                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1453                 SUPPORTED_1000baseT_Full : 0;
1454         phy_interface_t interface;
1455
1456         priv->oldlink = 0;
1457         priv->oldspeed = 0;
1458         priv->oldduplex = -1;
1459
1460         interface = gfar_get_interface(dev);
1461
1462         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1463                                       interface);
1464         if (!priv->phydev)
1465                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1466                                                          interface);
1467         if (!priv->phydev) {
1468                 dev_err(&dev->dev, "could not attach to PHY\n");
1469                 return -ENODEV;
1470         }
1471
1472         if (interface == PHY_INTERFACE_MODE_SGMII)
1473                 gfar_configure_serdes(dev);
1474
1475         /* Remove any features not supported by the controller */
1476         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1477         priv->phydev->advertising = priv->phydev->supported;
1478
1479         return 0;
1480 }
1481
1482 /*
1483  * Initialize TBI PHY interface for communicating with the
1484  * SERDES lynx PHY on the chip.  We communicate with this PHY
1485  * through the MDIO bus on each controller, treating it as a
1486  * "normal" PHY at the address found in the TBIPA register.  We assume
1487  * that the TBIPA register is valid.  Either the MDIO bus code will set
1488  * it to a value that doesn't conflict with other PHYs on the bus, or the
1489  * value doesn't matter, as there are no other PHYs on the bus.
1490  */
1491 static void gfar_configure_serdes(struct net_device *dev)
1492 {
1493         struct gfar_private *priv = netdev_priv(dev);
1494         struct phy_device *tbiphy;
1495
1496         if (!priv->tbi_node) {
1497                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1498                                     "device tree specify a tbi-handle\n");
1499                 return;
1500         }
1501
1502         tbiphy = of_phy_find_device(priv->tbi_node);
1503         if (!tbiphy) {
1504                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1505                 return;
1506         }
1507
1508         /*
1509          * If the link is already up, we must already be ok, and don't need to
1510          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1511          * everything for us?  Resetting it takes the link down and requires
1512          * several seconds for it to come back.
1513          */
1514         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1515                 return;
1516
1517         /* Single clk mode, mii mode off(for serdes communication) */
1518         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1519
1520         phy_write(tbiphy, MII_ADVERTISE,
1521                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1522                         ADVERTISE_1000XPSE_ASYM);
1523
1524         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1525                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1526 }
1527
1528 static void init_registers(struct net_device *dev)
1529 {
1530         struct gfar_private *priv = netdev_priv(dev);
1531         struct gfar __iomem *regs = NULL;
1532         int i = 0;
1533
1534         for (i = 0; i < priv->num_grps; i++) {
1535                 regs = priv->gfargrp[i].regs;
1536                 /* Clear IEVENT */
1537                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1538
1539                 /* Initialize IMASK */
1540                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1541         }
1542
1543         regs = priv->gfargrp[0].regs;
1544         /* Init hash registers to zero */
1545         gfar_write(&regs->igaddr0, 0);
1546         gfar_write(&regs->igaddr1, 0);
1547         gfar_write(&regs->igaddr2, 0);
1548         gfar_write(&regs->igaddr3, 0);
1549         gfar_write(&regs->igaddr4, 0);
1550         gfar_write(&regs->igaddr5, 0);
1551         gfar_write(&regs->igaddr6, 0);
1552         gfar_write(&regs->igaddr7, 0);
1553
1554         gfar_write(&regs->gaddr0, 0);
1555         gfar_write(&regs->gaddr1, 0);
1556         gfar_write(&regs->gaddr2, 0);
1557         gfar_write(&regs->gaddr3, 0);
1558         gfar_write(&regs->gaddr4, 0);
1559         gfar_write(&regs->gaddr5, 0);
1560         gfar_write(&regs->gaddr6, 0);
1561         gfar_write(&regs->gaddr7, 0);
1562
1563         /* Zero out the rmon mib registers if it has them */
1564         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1565                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1566
1567                 /* Mask off the CAM interrupts */
1568                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1569                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1570         }
1571
1572         /* Initialize the max receive buffer length */
1573         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1574
1575         /* Initialize the Minimum Frame Length Register */
1576         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1577 }
1578
1579 static int __gfar_is_rx_idle(struct gfar_private *priv)
1580 {
1581         u32 res;
1582
1583         /*
1584          * Normaly TSEC should not hang on GRS commands, so we should
1585          * actually wait for IEVENT_GRSC flag.
1586          */
1587         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1588                 return 0;
1589
1590         /*
1591          * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1592          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1593          * and the Rx can be safely reset.
1594          */
1595         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1596         res &= 0x7f807f80;
1597         if ((res & 0xffff) == (res >> 16))
1598                 return 1;
1599
1600         return 0;
1601 }
1602
1603 /* Halt the receive and transmit queues */
1604 static void gfar_halt_nodisable(struct net_device *dev)
1605 {
1606         struct gfar_private *priv = netdev_priv(dev);
1607         struct gfar __iomem *regs = NULL;
1608         u32 tempval;
1609         int i = 0;
1610
1611         for (i = 0; i < priv->num_grps; i++) {
1612                 regs = priv->gfargrp[i].regs;
1613                 /* Mask all interrupts */
1614                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1615
1616                 /* Clear all interrupts */
1617                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1618         }
1619
1620         regs = priv->gfargrp[0].regs;
1621         /* Stop the DMA, and wait for it to stop */
1622         tempval = gfar_read(&regs->dmactrl);
1623         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1624             != (DMACTRL_GRS | DMACTRL_GTS)) {
1625                 int ret;
1626
1627                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1628                 gfar_write(&regs->dmactrl, tempval);
1629
1630                 do {
1631                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1632                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1633                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1634                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1635                                 ret = __gfar_is_rx_idle(priv);
1636                 } while (!ret);
1637         }
1638 }
1639
1640 /* Halt the receive and transmit queues */
1641 void gfar_halt(struct net_device *dev)
1642 {
1643         struct gfar_private *priv = netdev_priv(dev);
1644         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1645         u32 tempval;
1646
1647         gfar_halt_nodisable(dev);
1648
1649         /* Disable Rx and Tx */
1650         tempval = gfar_read(&regs->maccfg1);
1651         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1652         gfar_write(&regs->maccfg1, tempval);
1653 }
1654
1655 static void free_grp_irqs(struct gfar_priv_grp *grp)
1656 {
1657         free_irq(grp->interruptError, grp);
1658         free_irq(grp->interruptTransmit, grp);
1659         free_irq(grp->interruptReceive, grp);
1660 }
1661
1662 void stop_gfar(struct net_device *dev)
1663 {
1664         struct gfar_private *priv = netdev_priv(dev);
1665         unsigned long flags;
1666         int i;
1667
1668         phy_stop(priv->phydev);
1669
1670
1671         /* Lock it down */
1672         local_irq_save(flags);
1673         lock_tx_qs(priv);
1674         lock_rx_qs(priv);
1675
1676         gfar_halt(dev);
1677
1678         unlock_rx_qs(priv);
1679         unlock_tx_qs(priv);
1680         local_irq_restore(flags);
1681
1682         /* Free the IRQs */
1683         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1684                 for (i = 0; i < priv->num_grps; i++)
1685                         free_grp_irqs(&priv->gfargrp[i]);
1686         } else {
1687                 for (i = 0; i < priv->num_grps; i++)
1688                         free_irq(priv->gfargrp[i].interruptTransmit,
1689                                         &priv->gfargrp[i]);
1690         }
1691
1692         free_skb_resources(priv);
1693 }
1694
1695 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1696 {
1697         struct txbd8 *txbdp;
1698         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1699         int i, j;
1700
1701         txbdp = tx_queue->tx_bd_base;
1702
1703         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1704                 if (!tx_queue->tx_skbuff[i])
1705                         continue;
1706
1707                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1708                                 txbdp->length, DMA_TO_DEVICE);
1709                 txbdp->lstatus = 0;
1710                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1711                                 j++) {
1712                         txbdp++;
1713                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1714                                         txbdp->length, DMA_TO_DEVICE);
1715                 }
1716                 txbdp++;
1717                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1718                 tx_queue->tx_skbuff[i] = NULL;
1719         }
1720         kfree(tx_queue->tx_skbuff);
1721 }
1722
1723 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1724 {
1725         struct rxbd8 *rxbdp;
1726         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1727         int i;
1728
1729         rxbdp = rx_queue->rx_bd_base;
1730
1731         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1732                 if (rx_queue->rx_skbuff[i]) {
1733                         dma_unmap_single(&priv->ofdev->dev,
1734                                         rxbdp->bufPtr, priv->rx_buffer_size,
1735                                         DMA_FROM_DEVICE);
1736                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1737                         rx_queue->rx_skbuff[i] = NULL;
1738                 }
1739                 rxbdp->lstatus = 0;
1740                 rxbdp->bufPtr = 0;
1741                 rxbdp++;
1742         }
1743         kfree(rx_queue->rx_skbuff);
1744 }
1745
1746 /* If there are any tx skbs or rx skbs still around, free them.
1747  * Then free tx_skbuff and rx_skbuff */
1748 static void free_skb_resources(struct gfar_private *priv)
1749 {
1750         struct gfar_priv_tx_q *tx_queue = NULL;
1751         struct gfar_priv_rx_q *rx_queue = NULL;
1752         int i;
1753
1754         /* Go through all the buffer descriptors and free their data buffers */
1755         for (i = 0; i < priv->num_tx_queues; i++) {
1756                 tx_queue = priv->tx_queue[i];
1757                 if(tx_queue->tx_skbuff)
1758                         free_skb_tx_queue(tx_queue);
1759         }
1760
1761         for (i = 0; i < priv->num_rx_queues; i++) {
1762                 rx_queue = priv->rx_queue[i];
1763                 if(rx_queue->rx_skbuff)
1764                         free_skb_rx_queue(rx_queue);
1765         }
1766
1767         dma_free_coherent(&priv->ofdev->dev,
1768                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1769                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1770                         priv->tx_queue[0]->tx_bd_base,
1771                         priv->tx_queue[0]->tx_bd_dma_base);
1772         skb_queue_purge(&priv->rx_recycle);
1773 }
1774
1775 void gfar_start(struct net_device *dev)
1776 {
1777         struct gfar_private *priv = netdev_priv(dev);
1778         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1779         u32 tempval;
1780         int i = 0;
1781
1782         /* Enable Rx and Tx in MACCFG1 */
1783         tempval = gfar_read(&regs->maccfg1);
1784         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1785         gfar_write(&regs->maccfg1, tempval);
1786
1787         /* Initialize DMACTRL to have WWR and WOP */
1788         tempval = gfar_read(&regs->dmactrl);
1789         tempval |= DMACTRL_INIT_SETTINGS;
1790         gfar_write(&regs->dmactrl, tempval);
1791
1792         /* Make sure we aren't stopped */
1793         tempval = gfar_read(&regs->dmactrl);
1794         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1795         gfar_write(&regs->dmactrl, tempval);
1796
1797         for (i = 0; i < priv->num_grps; i++) {
1798                 regs = priv->gfargrp[i].regs;
1799                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1800                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1801                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1802                 /* Unmask the interrupts we look for */
1803                 gfar_write(&regs->imask, IMASK_DEFAULT);
1804         }
1805
1806         dev->trans_start = jiffies; /* prevent tx timeout */
1807 }
1808
1809 void gfar_configure_coalescing(struct gfar_private *priv,
1810         unsigned long tx_mask, unsigned long rx_mask)
1811 {
1812         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1813         u32 __iomem *baddr;
1814         int i = 0;
1815
1816         /* Backward compatible case ---- even if we enable
1817          * multiple queues, there's only single reg to program
1818          */
1819         gfar_write(&regs->txic, 0);
1820         if(likely(priv->tx_queue[0]->txcoalescing))
1821                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1822
1823         gfar_write(&regs->rxic, 0);
1824         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1825                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1826
1827         if (priv->mode == MQ_MG_MODE) {
1828                 baddr = &regs->txic0;
1829                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1830                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1831                                 gfar_write(baddr + i, 0);
1832                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1833                         }
1834                 }
1835
1836                 baddr = &regs->rxic0;
1837                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1838                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1839                                 gfar_write(baddr + i, 0);
1840                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1841                         }
1842                 }
1843         }
1844 }
1845
1846 static int register_grp_irqs(struct gfar_priv_grp *grp)
1847 {
1848         struct gfar_private *priv = grp->priv;
1849         struct net_device *dev = priv->ndev;
1850         int err;
1851
1852         /* If the device has multiple interrupts, register for
1853          * them.  Otherwise, only register for the one */
1854         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1855                 /* Install our interrupt handlers for Error,
1856                  * Transmit, and Receive */
1857                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1858                                 grp->int_name_er,grp)) < 0) {
1859                         if (netif_msg_intr(priv))
1860                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1861                                         dev->name, grp->interruptError);
1862
1863                         goto err_irq_fail;
1864                 }
1865
1866                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1867                                 0, grp->int_name_tx, grp)) < 0) {
1868                         if (netif_msg_intr(priv))
1869                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1870                                         dev->name, grp->interruptTransmit);
1871                         goto tx_irq_fail;
1872                 }
1873
1874                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1875                                 grp->int_name_rx, grp)) < 0) {
1876                         if (netif_msg_intr(priv))
1877                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1878                                         dev->name, grp->interruptReceive);
1879                         goto rx_irq_fail;
1880                 }
1881         } else {
1882                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1883                                 grp->int_name_tx, grp)) < 0) {
1884                         if (netif_msg_intr(priv))
1885                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1886                                         dev->name, grp->interruptTransmit);
1887                         goto err_irq_fail;
1888                 }
1889         }
1890
1891         return 0;
1892
1893 rx_irq_fail:
1894         free_irq(grp->interruptTransmit, grp);
1895 tx_irq_fail:
1896         free_irq(grp->interruptError, grp);
1897 err_irq_fail:
1898         return err;
1899
1900 }
1901
1902 /* Bring the controller up and running */
1903 int startup_gfar(struct net_device *ndev)
1904 {
1905         struct gfar_private *priv = netdev_priv(ndev);
1906         struct gfar __iomem *regs = NULL;
1907         int err, i, j;
1908
1909         for (i = 0; i < priv->num_grps; i++) {
1910                 regs= priv->gfargrp[i].regs;
1911                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1912         }
1913
1914         regs= priv->gfargrp[0].regs;
1915         err = gfar_alloc_skb_resources(ndev);
1916         if (err)
1917                 return err;
1918
1919         gfar_init_mac(ndev);
1920
1921         for (i = 0; i < priv->num_grps; i++) {
1922                 err = register_grp_irqs(&priv->gfargrp[i]);
1923                 if (err) {
1924                         for (j = 0; j < i; j++)
1925                                 free_grp_irqs(&priv->gfargrp[j]);
1926                         goto irq_fail;
1927                 }
1928         }
1929
1930         /* Start the controller */
1931         gfar_start(ndev);
1932
1933         phy_start(priv->phydev);
1934
1935         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1936
1937         return 0;
1938
1939 irq_fail:
1940         free_skb_resources(priv);
1941         return err;
1942 }
1943
1944 /* Called when something needs to use the ethernet device */
1945 /* Returns 0 for success. */
1946 static int gfar_enet_open(struct net_device *dev)
1947 {
1948         struct gfar_private *priv = netdev_priv(dev);
1949         int err;
1950
1951         enable_napi(priv);
1952
1953         skb_queue_head_init(&priv->rx_recycle);
1954
1955         /* Initialize a bunch of registers */
1956         init_registers(dev);
1957
1958         gfar_set_mac_address(dev);
1959
1960         err = init_phy(dev);
1961
1962         if (err) {
1963                 disable_napi(priv);
1964                 return err;
1965         }
1966
1967         err = startup_gfar(dev);
1968         if (err) {
1969                 disable_napi(priv);
1970                 return err;
1971         }
1972
1973         netif_tx_start_all_queues(dev);
1974
1975         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1976
1977         return err;
1978 }
1979
1980 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1981 {
1982         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1983
1984         memset(fcb, 0, GMAC_FCB_LEN);
1985
1986         return fcb;
1987 }
1988
1989 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1990 {
1991         u8 flags = 0;
1992
1993         /* If we're here, it's a IP packet with a TCP or UDP
1994          * payload.  We set it to checksum, using a pseudo-header
1995          * we provide
1996          */
1997         flags = TXFCB_DEFAULT;
1998
1999         /* Tell the controller what the protocol is */
2000         /* And provide the already calculated phcs */
2001         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2002                 flags |= TXFCB_UDP;
2003                 fcb->phcs = udp_hdr(skb)->check;
2004         } else
2005                 fcb->phcs = tcp_hdr(skb)->check;
2006
2007         /* l3os is the distance between the start of the
2008          * frame (skb->data) and the start of the IP hdr.
2009          * l4os is the distance between the start of the
2010          * l3 hdr and the l4 hdr */
2011         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2012         fcb->l4os = skb_network_header_len(skb);
2013
2014         fcb->flags = flags;
2015 }
2016
2017 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2018 {
2019         fcb->flags |= TXFCB_VLN;
2020         fcb->vlctl = vlan_tx_tag_get(skb);
2021 }
2022
2023 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2024                                struct txbd8 *base, int ring_size)
2025 {
2026         struct txbd8 *new_bd = bdp + stride;
2027
2028         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2029 }
2030
2031 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2032                 int ring_size)
2033 {
2034         return skip_txbd(bdp, 1, base, ring_size);
2035 }
2036
2037 /* This is called by the kernel when a frame is ready for transmission. */
2038 /* It is pointed to by the dev->hard_start_xmit function pointer */
2039 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2040 {
2041         struct gfar_private *priv = netdev_priv(dev);
2042         struct gfar_priv_tx_q *tx_queue = NULL;
2043         struct netdev_queue *txq;
2044         struct gfar __iomem *regs = NULL;
2045         struct txfcb *fcb = NULL;
2046         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2047         u32 lstatus;
2048         int i, rq = 0, do_tstamp = 0;
2049         u32 bufaddr;
2050         unsigned long flags;
2051         unsigned int nr_frags, nr_txbds, length;
2052
2053         /*
2054          * TOE=1 frames larger than 2500 bytes may see excess delays
2055          * before start of transmission.
2056          */
2057         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2058                         skb->ip_summed == CHECKSUM_PARTIAL &&
2059                         skb->len > 2500)) {
2060                 int ret;
2061
2062                 ret = skb_checksum_help(skb);
2063                 if (ret)
2064                         return ret;
2065         }
2066
2067         rq = skb->queue_mapping;
2068         tx_queue = priv->tx_queue[rq];
2069         txq = netdev_get_tx_queue(dev, rq);
2070         base = tx_queue->tx_bd_base;
2071         regs = tx_queue->grp->regs;
2072
2073         /* check if time stamp should be generated */
2074         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2075                      priv->hwts_tx_en))
2076                 do_tstamp = 1;
2077
2078         /* make space for additional header when fcb is needed */
2079         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2080                         vlan_tx_tag_present(skb) ||
2081                         unlikely(do_tstamp)) &&
2082                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
2083                 struct sk_buff *skb_new;
2084
2085                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2086                 if (!skb_new) {
2087                         dev->stats.tx_errors++;
2088                         kfree_skb(skb);
2089                         return NETDEV_TX_OK;
2090                 }
2091                 kfree_skb(skb);
2092                 skb = skb_new;
2093         }
2094
2095         /* total number of fragments in the SKB */
2096         nr_frags = skb_shinfo(skb)->nr_frags;
2097
2098         /* calculate the required number of TxBDs for this skb */
2099         if (unlikely(do_tstamp))
2100                 nr_txbds = nr_frags + 2;
2101         else
2102                 nr_txbds = nr_frags + 1;
2103
2104         /* check if there is space to queue this packet */
2105         if (nr_txbds > tx_queue->num_txbdfree) {
2106                 /* no space, stop the queue */
2107                 netif_tx_stop_queue(txq);
2108                 dev->stats.tx_fifo_errors++;
2109                 return NETDEV_TX_BUSY;
2110         }
2111
2112         /* Update transmit stats */
2113         tx_queue->stats.tx_bytes += skb->len;
2114         tx_queue->stats.tx_packets++;
2115
2116         txbdp = txbdp_start = tx_queue->cur_tx;
2117         lstatus = txbdp->lstatus;
2118
2119         /* Time stamp insertion requires one additional TxBD */
2120         if (unlikely(do_tstamp))
2121                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2122                                 tx_queue->tx_ring_size);
2123
2124         if (nr_frags == 0) {
2125                 if (unlikely(do_tstamp))
2126                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2127                                         TXBD_INTERRUPT);
2128                 else
2129                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2130         } else {
2131                 /* Place the fragment addresses and lengths into the TxBDs */
2132                 for (i = 0; i < nr_frags; i++) {
2133                         /* Point at the next BD, wrapping as needed */
2134                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2135
2136                         length = skb_shinfo(skb)->frags[i].size;
2137
2138                         lstatus = txbdp->lstatus | length |
2139                                 BD_LFLAG(TXBD_READY);
2140
2141                         /* Handle the last BD specially */
2142                         if (i == nr_frags - 1)
2143                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2144
2145                         bufaddr = dma_map_page(&priv->ofdev->dev,
2146                                         skb_shinfo(skb)->frags[i].page,
2147                                         skb_shinfo(skb)->frags[i].page_offset,
2148                                         length,
2149                                         DMA_TO_DEVICE);
2150
2151                         /* set the TxBD length and buffer pointer */
2152                         txbdp->bufPtr = bufaddr;
2153                         txbdp->lstatus = lstatus;
2154                 }
2155
2156                 lstatus = txbdp_start->lstatus;
2157         }
2158
2159         /* Set up checksumming */
2160         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2161                 fcb = gfar_add_fcb(skb);
2162                 /* as specified by errata */
2163                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2164                              && ((unsigned long)fcb % 0x20) > 0x18)) {
2165                         __skb_pull(skb, GMAC_FCB_LEN);
2166                         skb_checksum_help(skb);
2167                 } else {
2168                         lstatus |= BD_LFLAG(TXBD_TOE);
2169                         gfar_tx_checksum(skb, fcb);
2170                 }
2171         }
2172
2173         if (vlan_tx_tag_present(skb)) {
2174                 if (unlikely(NULL == fcb)) {
2175                         fcb = gfar_add_fcb(skb);
2176                         lstatus |= BD_LFLAG(TXBD_TOE);
2177                 }
2178
2179                 gfar_tx_vlan(skb, fcb);
2180         }
2181
2182         /* Setup tx hardware time stamping if requested */
2183         if (unlikely(do_tstamp)) {
2184                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2185                 if (fcb == NULL)
2186                         fcb = gfar_add_fcb(skb);
2187                 fcb->ptp = 1;
2188                 lstatus |= BD_LFLAG(TXBD_TOE);
2189         }
2190
2191         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2192                         skb_headlen(skb), DMA_TO_DEVICE);
2193
2194         /*
2195          * If time stamping is requested one additional TxBD must be set up. The
2196          * first TxBD points to the FCB and must have a data length of
2197          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2198          * the full frame length.
2199          */
2200         if (unlikely(do_tstamp)) {
2201                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2202                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2203                                 (skb_headlen(skb) - GMAC_FCB_LEN);
2204                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2205         } else {
2206                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2207         }
2208
2209         /*
2210          * We can work in parallel with gfar_clean_tx_ring(), except
2211          * when modifying num_txbdfree. Note that we didn't grab the lock
2212          * when we were reading the num_txbdfree and checking for available
2213          * space, that's because outside of this function it can only grow,
2214          * and once we've got needed space, it cannot suddenly disappear.
2215          *
2216          * The lock also protects us from gfar_error(), which can modify
2217          * regs->tstat and thus retrigger the transfers, which is why we
2218          * also must grab the lock before setting ready bit for the first
2219          * to be transmitted BD.
2220          */
2221         spin_lock_irqsave(&tx_queue->txlock, flags);
2222
2223         /*
2224          * The powerpc-specific eieio() is used, as wmb() has too strong
2225          * semantics (it requires synchronization between cacheable and
2226          * uncacheable mappings, which eieio doesn't provide and which we
2227          * don't need), thus requiring a more expensive sync instruction.  At
2228          * some point, the set of architecture-independent barrier functions
2229          * should be expanded to include weaker barriers.
2230          */
2231         eieio();
2232
2233         txbdp_start->lstatus = lstatus;
2234
2235         eieio(); /* force lstatus write before tx_skbuff */
2236
2237         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2238
2239         /* Update the current skb pointer to the next entry we will use
2240          * (wrapping if necessary) */
2241         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2242                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2243
2244         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2245
2246         /* reduce TxBD free count */
2247         tx_queue->num_txbdfree -= (nr_txbds);
2248
2249         /* If the next BD still needs to be cleaned up, then the bds
2250            are full.  We need to tell the kernel to stop sending us stuff. */
2251         if (!tx_queue->num_txbdfree) {
2252                 netif_tx_stop_queue(txq);
2253
2254                 dev->stats.tx_fifo_errors++;
2255         }
2256
2257         /* Tell the DMA to go go go */
2258         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2259
2260         /* Unlock priv */
2261         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2262
2263         return NETDEV_TX_OK;
2264 }
2265
2266 /* Stops the kernel queue, and halts the controller */
2267 static int gfar_close(struct net_device *dev)
2268 {
2269         struct gfar_private *priv = netdev_priv(dev);
2270
2271         disable_napi(priv);
2272
2273         cancel_work_sync(&priv->reset_task);
2274         stop_gfar(dev);
2275
2276         /* Disconnect from the PHY */
2277         phy_disconnect(priv->phydev);
2278         priv->phydev = NULL;
2279
2280         netif_tx_stop_all_queues(dev);
2281
2282         return 0;
2283 }
2284
2285 /* Changes the mac address if the controller is not running. */
2286 static int gfar_set_mac_address(struct net_device *dev)
2287 {
2288         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2289
2290         return 0;
2291 }
2292
2293
2294 /* Enables and disables VLAN insertion/extraction */
2295 static void gfar_vlan_rx_register(struct net_device *dev,
2296                 struct vlan_group *grp)
2297 {
2298         struct gfar_private *priv = netdev_priv(dev);
2299         struct gfar __iomem *regs = NULL;
2300         unsigned long flags;
2301         u32 tempval;
2302
2303         regs = priv->gfargrp[0].regs;
2304         local_irq_save(flags);
2305         lock_rx_qs(priv);
2306
2307         priv->vlgrp = grp;
2308
2309         if (grp) {
2310                 /* Enable VLAN tag insertion */
2311                 tempval = gfar_read(&regs->tctrl);
2312                 tempval |= TCTRL_VLINS;
2313
2314                 gfar_write(&regs->tctrl, tempval);
2315
2316                 /* Enable VLAN tag extraction */
2317                 tempval = gfar_read(&regs->rctrl);
2318                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2319                 gfar_write(&regs->rctrl, tempval);
2320         } else {
2321                 /* Disable VLAN tag insertion */
2322                 tempval = gfar_read(&regs->tctrl);
2323                 tempval &= ~TCTRL_VLINS;
2324                 gfar_write(&regs->tctrl, tempval);
2325
2326                 /* Disable VLAN tag extraction */
2327                 tempval = gfar_read(&regs->rctrl);
2328                 tempval &= ~RCTRL_VLEX;
2329                 /* If parse is no longer required, then disable parser */
2330                 if (tempval & RCTRL_REQ_PARSER)
2331                         tempval |= RCTRL_PRSDEP_INIT;
2332                 else
2333                         tempval &= ~RCTRL_PRSDEP_INIT;
2334                 gfar_write(&regs->rctrl, tempval);
2335         }
2336
2337         gfar_change_mtu(dev, dev->mtu);
2338
2339         unlock_rx_qs(priv);
2340         local_irq_restore(flags);
2341 }
2342
2343 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2344 {
2345         int tempsize, tempval;
2346         struct gfar_private *priv = netdev_priv(dev);
2347         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2348         int oldsize = priv->rx_buffer_size;
2349         int frame_size = new_mtu + ETH_HLEN;
2350
2351         if (priv->vlgrp)
2352                 frame_size += VLAN_HLEN;
2353
2354         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2355                 if (netif_msg_drv(priv))
2356                         printk(KERN_ERR "%s: Invalid MTU setting\n",
2357                                         dev->name);
2358                 return -EINVAL;
2359         }
2360
2361         if (gfar_uses_fcb(priv))
2362                 frame_size += GMAC_FCB_LEN;
2363
2364         frame_size += priv->padding;
2365
2366         tempsize =
2367             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2368             INCREMENTAL_BUFFER_SIZE;
2369
2370         /* Only stop and start the controller if it isn't already
2371          * stopped, and we changed something */
2372         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2373                 stop_gfar(dev);
2374
2375         priv->rx_buffer_size = tempsize;
2376
2377         dev->mtu = new_mtu;
2378
2379         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2380         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2381
2382         /* If the mtu is larger than the max size for standard
2383          * ethernet frames (ie, a jumbo frame), then set maccfg2
2384          * to allow huge frames, and to check the length */
2385         tempval = gfar_read(&regs->maccfg2);
2386
2387         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2388                         gfar_has_errata(priv, GFAR_ERRATA_74))
2389                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2390         else
2391                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2392
2393         gfar_write(&regs->maccfg2, tempval);
2394
2395         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2396                 startup_gfar(dev);
2397
2398         return 0;
2399 }
2400
2401 /* gfar_reset_task gets scheduled when a packet has not been
2402  * transmitted after a set amount of time.
2403  * For now, assume that clearing out all the structures, and
2404  * starting over will fix the problem.
2405  */
2406 static void gfar_reset_task(struct work_struct *work)
2407 {
2408         struct gfar_private *priv = container_of(work, struct gfar_private,
2409                         reset_task);
2410         struct net_device *dev = priv->ndev;
2411
2412         if (dev->flags & IFF_UP) {
2413                 netif_tx_stop_all_queues(dev);
2414                 stop_gfar(dev);
2415                 startup_gfar(dev);
2416                 netif_tx_start_all_queues(dev);
2417         }
2418
2419         netif_tx_schedule_all(dev);
2420 }
2421
2422 static void gfar_timeout(struct net_device *dev)
2423 {
2424         struct gfar_private *priv = netdev_priv(dev);
2425
2426         dev->stats.tx_errors++;
2427         schedule_work(&priv->reset_task);
2428 }
2429
2430 static void gfar_align_skb(struct sk_buff *skb)
2431 {
2432         /* We need the data buffer to be aligned properly.  We will reserve
2433          * as many bytes as needed to align the data properly
2434          */
2435         skb_reserve(skb, RXBUF_ALIGNMENT -
2436                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2437 }
2438
2439 /* Interrupt Handler for Transmit complete */
2440 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2441 {
2442         struct net_device *dev = tx_queue->dev;
2443         struct gfar_private *priv = netdev_priv(dev);
2444         struct gfar_priv_rx_q *rx_queue = NULL;
2445         struct txbd8 *bdp, *next = NULL;
2446         struct txbd8 *lbdp = NULL;
2447         struct txbd8 *base = tx_queue->tx_bd_base;
2448         struct sk_buff *skb;
2449         int skb_dirtytx;
2450         int tx_ring_size = tx_queue->tx_ring_size;
2451         int frags = 0, nr_txbds = 0;
2452         int i;
2453         int howmany = 0;
2454         u32 lstatus;
2455         size_t buflen;
2456
2457         rx_queue = priv->rx_queue[tx_queue->qindex];
2458         bdp = tx_queue->dirty_tx;
2459         skb_dirtytx = tx_queue->skb_dirtytx;
2460
2461         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2462                 unsigned long flags;
2463
2464                 frags = skb_shinfo(skb)->nr_frags;
2465
2466                 /*
2467                  * When time stamping, one additional TxBD must be freed.
2468                  * Also, we need to dma_unmap_single() the TxPAL.
2469                  */
2470                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2471                         nr_txbds = frags + 2;
2472                 else
2473                         nr_txbds = frags + 1;
2474
2475                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2476
2477                 lstatus = lbdp->lstatus;
2478
2479                 /* Only clean completed frames */
2480                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2481                                 (lstatus & BD_LENGTH_MASK))
2482                         break;
2483
2484                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2485                         next = next_txbd(bdp, base, tx_ring_size);
2486                         buflen = next->length + GMAC_FCB_LEN;
2487                 } else
2488                         buflen = bdp->length;
2489
2490                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2491                                 buflen, DMA_TO_DEVICE);
2492
2493                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2494                         struct skb_shared_hwtstamps shhwtstamps;
2495                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2496                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2497                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2498                         skb_tstamp_tx(skb, &shhwtstamps);
2499                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2500                         bdp = next;
2501                 }
2502
2503                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2504                 bdp = next_txbd(bdp, base, tx_ring_size);
2505
2506                 for (i = 0; i < frags; i++) {
2507                         dma_unmap_page(&priv->ofdev->dev,
2508                                         bdp->bufPtr,
2509                                         bdp->length,
2510                                         DMA_TO_DEVICE);
2511                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2512                         bdp = next_txbd(bdp, base, tx_ring_size);
2513                 }
2514
2515                 /*
2516                  * If there's room in the queue (limit it to rx_buffer_size)
2517                  * we add this skb back into the pool, if it's the right size
2518                  */
2519                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2520                                 skb_recycle_check(skb, priv->rx_buffer_size +
2521                                         RXBUF_ALIGNMENT)) {
2522                         gfar_align_skb(skb);
2523                         skb_queue_head(&priv->rx_recycle, skb);
2524                 } else
2525                         dev_kfree_skb_any(skb);
2526
2527                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2528
2529                 skb_dirtytx = (skb_dirtytx + 1) &
2530                         TX_RING_MOD_MASK(tx_ring_size);
2531
2532                 howmany++;
2533                 spin_lock_irqsave(&tx_queue->txlock, flags);
2534                 tx_queue->num_txbdfree += nr_txbds;
2535                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2536         }
2537
2538         /* If we freed a buffer, we can restart transmission, if necessary */
2539         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2540                 netif_wake_subqueue(dev, tx_queue->qindex);
2541
2542         /* Update dirty indicators */
2543         tx_queue->skb_dirtytx = skb_dirtytx;
2544         tx_queue->dirty_tx = bdp;
2545
2546         return howmany;
2547 }
2548
2549 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2550 {
2551         unsigned long flags;
2552
2553         spin_lock_irqsave(&gfargrp->grplock, flags);
2554         if (napi_schedule_prep(&gfargrp->napi)) {
2555                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2556                 __napi_schedule(&gfargrp->napi);
2557         } else {
2558                 /*
2559                  * Clear IEVENT, so interrupts aren't called again
2560                  * because of the packets that have already arrived.
2561                  */
2562                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2563         }
2564         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2565
2566 }
2567
2568 /* Interrupt Handler for Transmit complete */
2569 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2570 {
2571         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2572         return IRQ_HANDLED;
2573 }
2574
2575 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2576                 struct sk_buff *skb)
2577 {
2578         struct net_device *dev = rx_queue->dev;
2579         struct gfar_private *priv = netdev_priv(dev);
2580         dma_addr_t buf;
2581
2582         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2583                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2584         gfar_init_rxbdp(rx_queue, bdp, buf);
2585 }
2586
2587 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2588 {
2589         struct gfar_private *priv = netdev_priv(dev);
2590         struct sk_buff *skb = NULL;
2591
2592         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2593         if (!skb)
2594                 return NULL;
2595
2596         gfar_align_skb(skb);
2597
2598         return skb;
2599 }
2600
2601 struct sk_buff * gfar_new_skb(struct net_device *dev)
2602 {
2603         struct gfar_private *priv = netdev_priv(dev);
2604         struct sk_buff *skb = NULL;
2605
2606         skb = skb_dequeue(&priv->rx_recycle);
2607         if (!skb)
2608                 skb = gfar_alloc_skb(dev);
2609
2610         return skb;
2611 }
2612
2613 static inline void count_errors(unsigned short status, struct net_device *dev)
2614 {
2615         struct gfar_private *priv = netdev_priv(dev);
2616         struct net_device_stats *stats = &dev->stats;
2617         struct gfar_extra_stats *estats = &priv->extra_stats;
2618
2619         /* If the packet was truncated, none of the other errors
2620          * matter */
2621         if (status & RXBD_TRUNCATED) {
2622                 stats->rx_length_errors++;
2623
2624                 estats->rx_trunc++;
2625
2626                 return;
2627         }
2628         /* Count the errors, if there were any */
2629         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2630                 stats->rx_length_errors++;
2631
2632                 if (status & RXBD_LARGE)
2633                         estats->rx_large++;
2634                 else
2635                         estats->rx_short++;
2636         }
2637         if (status & RXBD_NONOCTET) {
2638                 stats->rx_frame_errors++;
2639                 estats->rx_nonoctet++;
2640         }
2641         if (status & RXBD_CRCERR) {
2642                 estats->rx_crcerr++;
2643                 stats->rx_crc_errors++;
2644         }
2645         if (status & RXBD_OVERRUN) {
2646                 estats->rx_overrun++;
2647                 stats->rx_crc_errors++;
2648         }
2649 }
2650
2651 irqreturn_t gfar_receive(int irq, void *grp_id)
2652 {
2653         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2654         return IRQ_HANDLED;
2655 }
2656
2657 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2658 {
2659         /* If valid headers were found, and valid sums
2660          * were verified, then we tell the kernel that no
2661          * checksumming is necessary.  Otherwise, it is */
2662         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2663                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2664         else
2665                 skb_checksum_none_assert(skb);
2666 }
2667
2668
2669 /* gfar_process_frame() -- handle one incoming packet if skb
2670  * isn't NULL.  */
2671 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2672                               int amount_pull)
2673 {
2674         struct gfar_private *priv = netdev_priv(dev);
2675         struct rxfcb *fcb = NULL;
2676
2677         int ret;
2678
2679         /* fcb is at the beginning if exists */
2680         fcb = (struct rxfcb *)skb->data;
2681
2682         /* Remove the FCB from the skb */
2683         /* Remove the padded bytes, if there are any */
2684         if (amount_pull) {
2685                 skb_record_rx_queue(skb, fcb->rq);
2686                 skb_pull(skb, amount_pull);
2687         }
2688
2689         /* Get receive timestamp from the skb */
2690         if (priv->hwts_rx_en) {
2691                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2692                 u64 *ns = (u64 *) skb->data;
2693                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2694                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2695         }
2696
2697         if (priv->padding)
2698                 skb_pull(skb, priv->padding);
2699
2700         if (priv->rx_csum_enable)
2701                 gfar_rx_checksum(skb, fcb);
2702
2703         /* Tell the skb what kind of packet this is */
2704         skb->protocol = eth_type_trans(skb, dev);
2705
2706         /* Send the packet up the stack */
2707         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2708                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2709         else
2710                 ret = netif_receive_skb(skb);
2711
2712         if (NET_RX_DROP == ret)
2713                 priv->extra_stats.kernel_dropped++;
2714
2715         return 0;
2716 }
2717
2718 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2719  *   until the budget/quota has been reached. Returns the number
2720  *   of frames handled
2721  */
2722 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2723 {
2724         struct net_device *dev = rx_queue->dev;
2725         struct rxbd8 *bdp, *base;
2726         struct sk_buff *skb;
2727         int pkt_len;
2728         int amount_pull;
2729         int howmany = 0;
2730         struct gfar_private *priv = netdev_priv(dev);
2731
2732         /* Get the first full descriptor */
2733         bdp = rx_queue->cur_rx;
2734         base = rx_queue->rx_bd_base;
2735
2736         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2737
2738         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2739                 struct sk_buff *newskb;
2740                 rmb();
2741
2742                 /* Add another skb for the future */
2743                 newskb = gfar_new_skb(dev);
2744
2745                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2746
2747                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2748                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2749
2750                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2751                                 bdp->length > priv->rx_buffer_size))
2752                         bdp->status = RXBD_LARGE;
2753
2754                 /* We drop the frame if we failed to allocate a new buffer */
2755                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2756                                  bdp->status & RXBD_ERR)) {
2757                         count_errors(bdp->status, dev);
2758
2759                         if (unlikely(!newskb))
2760                                 newskb = skb;
2761                         else if (skb)
2762                                 skb_queue_head(&priv->rx_recycle, skb);
2763                 } else {
2764                         /* Increment the number of packets */
2765                         rx_queue->stats.rx_packets++;
2766                         howmany++;
2767
2768                         if (likely(skb)) {
2769                                 pkt_len = bdp->length - ETH_FCS_LEN;
2770                                 /* Remove the FCS from the packet length */
2771                                 skb_put(skb, pkt_len);
2772                                 rx_queue->stats.rx_bytes += pkt_len;
2773                                 skb_record_rx_queue(skb, rx_queue->qindex);
2774                                 gfar_process_frame(dev, skb, amount_pull);
2775
2776                         } else {
2777                                 if (netif_msg_rx_err(priv))
2778                                         printk(KERN_WARNING
2779                                                "%s: Missing skb!\n", dev->name);
2780                                 rx_queue->stats.rx_dropped++;
2781                                 priv->extra_stats.rx_skbmissing++;
2782                         }
2783
2784                 }
2785
2786                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2787
2788                 /* Setup the new bdp */
2789                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2790
2791                 /* Update to the next pointer */
2792                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2793
2794                 /* update to point at the next skb */
2795                 rx_queue->skb_currx =
2796                     (rx_queue->skb_currx + 1) &
2797                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2798         }
2799
2800         /* Update the current rxbd pointer to be the next one */
2801         rx_queue->cur_rx = bdp;
2802
2803         return howmany;
2804 }
2805
2806 static int gfar_poll(struct napi_struct *napi, int budget)
2807 {
2808         struct gfar_priv_grp *gfargrp = container_of(napi,
2809                         struct gfar_priv_grp, napi);
2810         struct gfar_private *priv = gfargrp->priv;
2811         struct gfar __iomem *regs = gfargrp->regs;
2812         struct gfar_priv_tx_q *tx_queue = NULL;
2813         struct gfar_priv_rx_q *rx_queue = NULL;
2814         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2815         int tx_cleaned = 0, i, left_over_budget = budget;
2816         unsigned long serviced_queues = 0;
2817         int num_queues = 0;
2818
2819         num_queues = gfargrp->num_rx_queues;
2820         budget_per_queue = budget/num_queues;
2821
2822         /* Clear IEVENT, so interrupts aren't called again
2823          * because of the packets that have already arrived */
2824         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2825
2826         while (num_queues && left_over_budget) {
2827
2828                 budget_per_queue = left_over_budget/num_queues;
2829                 left_over_budget = 0;
2830
2831                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2832                         if (test_bit(i, &serviced_queues))
2833                                 continue;
2834                         rx_queue = priv->rx_queue[i];
2835                         tx_queue = priv->tx_queue[rx_queue->qindex];
2836
2837                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2838                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2839                                                         budget_per_queue);
2840                         rx_cleaned += rx_cleaned_per_queue;
2841                         if(rx_cleaned_per_queue < budget_per_queue) {
2842                                 left_over_budget = left_over_budget +
2843                                         (budget_per_queue - rx_cleaned_per_queue);
2844                                 set_bit(i, &serviced_queues);
2845                                 num_queues--;
2846                         }
2847                 }
2848         }
2849
2850         if (tx_cleaned)
2851                 return budget;
2852
2853         if (rx_cleaned < budget) {
2854                 napi_complete(napi);
2855
2856                 /* Clear the halt bit in RSTAT */
2857                 gfar_write(&regs->rstat, gfargrp->rstat);
2858
2859                 gfar_write(&regs->imask, IMASK_DEFAULT);
2860
2861                 /* If we are coalescing interrupts, update the timer */
2862                 /* Otherwise, clear it */
2863                 gfar_configure_coalescing(priv,
2864                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2865         }
2866
2867         return rx_cleaned;
2868 }
2869
2870 #ifdef CONFIG_NET_POLL_CONTROLLER
2871 /*
2872  * Polling 'interrupt' - used by things like netconsole to send skbs
2873  * without having to re-enable interrupts. It's not called while
2874  * the interrupt routine is executing.
2875  */
2876 static void gfar_netpoll(struct net_device *dev)
2877 {
2878         struct gfar_private *priv = netdev_priv(dev);
2879         int i = 0;
2880
2881         /* If the device has multiple interrupts, run tx/rx */
2882         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2883                 for (i = 0; i < priv->num_grps; i++) {
2884                         disable_irq(priv->gfargrp[i].interruptTransmit);
2885                         disable_irq(priv->gfargrp[i].interruptReceive);
2886                         disable_irq(priv->gfargrp[i].interruptError);
2887                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2888                                                 &priv->gfargrp[i]);
2889                         enable_irq(priv->gfargrp[i].interruptError);
2890                         enable_irq(priv->gfargrp[i].interruptReceive);
2891                         enable_irq(priv->gfargrp[i].interruptTransmit);
2892                 }
2893         } else {
2894                 for (i = 0; i < priv->num_grps; i++) {
2895                         disable_irq(priv->gfargrp[i].interruptTransmit);
2896                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2897                                                 &priv->gfargrp[i]);
2898                         enable_irq(priv->gfargrp[i].interruptTransmit);
2899                 }
2900         }
2901 }
2902 #endif
2903
2904 /* The interrupt handler for devices with one interrupt */
2905 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2906 {
2907         struct gfar_priv_grp *gfargrp = grp_id;
2908
2909         /* Save ievent for future reference */
2910         u32 events = gfar_read(&gfargrp->regs->ievent);
2911
2912         /* Check for reception */
2913         if (events & IEVENT_RX_MASK)
2914                 gfar_receive(irq, grp_id);
2915
2916         /* Check for transmit completion */
2917         if (events & IEVENT_TX_MASK)
2918                 gfar_transmit(irq, grp_id);
2919
2920         /* Check for errors */
2921         if (events & IEVENT_ERR_MASK)
2922                 gfar_error(irq, grp_id);
2923
2924         return IRQ_HANDLED;
2925 }
2926
2927 /* Called every time the controller might need to be made
2928  * aware of new link state.  The PHY code conveys this
2929  * information through variables in the phydev structure, and this
2930  * function converts those variables into the appropriate
2931  * register values, and can bring down the device if needed.
2932  */
2933 static void adjust_link(struct net_device *dev)
2934 {
2935         struct gfar_private *priv = netdev_priv(dev);
2936         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2937         unsigned long flags;
2938         struct phy_device *phydev = priv->phydev;
2939         int new_state = 0;
2940
2941         local_irq_save(flags);
2942         lock_tx_qs(priv);
2943
2944         if (phydev->link) {
2945                 u32 tempval = gfar_read(&regs->maccfg2);
2946                 u32 ecntrl = gfar_read(&regs->ecntrl);
2947
2948                 /* Now we make sure that we can be in full duplex mode.
2949                  * If not, we operate in half-duplex mode. */
2950                 if (phydev->duplex != priv->oldduplex) {
2951                         new_state = 1;
2952                         if (!(phydev->duplex))
2953                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2954                         else
2955                                 tempval |= MACCFG2_FULL_DUPLEX;
2956
2957                         priv->oldduplex = phydev->duplex;
2958                 }
2959
2960                 if (phydev->speed != priv->oldspeed) {
2961                         new_state = 1;
2962                         switch (phydev->speed) {
2963                         case 1000:
2964                                 tempval =
2965                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2966
2967                                 ecntrl &= ~(ECNTRL_R100);
2968                                 break;
2969                         case 100:
2970                         case 10:
2971                                 tempval =
2972                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2973
2974                                 /* Reduced mode distinguishes
2975                                  * between 10 and 100 */
2976                                 if (phydev->speed == SPEED_100)
2977                                         ecntrl |= ECNTRL_R100;
2978                                 else
2979                                         ecntrl &= ~(ECNTRL_R100);
2980                                 break;
2981                         default:
2982                                 if (netif_msg_link(priv))
2983                                         printk(KERN_WARNING
2984                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2985                                                 dev->name, phydev->speed);
2986                                 break;
2987                         }
2988
2989                         priv->oldspeed = phydev->speed;
2990                 }
2991
2992                 gfar_write(&regs->maccfg2, tempval);
2993                 gfar_write(&regs->ecntrl, ecntrl);
2994
2995                 if (!priv->oldlink) {
2996                         new_state = 1;
2997                         priv->oldlink = 1;
2998                 }
2999         } else if (priv->oldlink) {
3000                 new_state = 1;
3001                 priv->oldlink = 0;
3002                 priv->oldspeed = 0;
3003                 priv->oldduplex = -1;
3004         }
3005
3006         if (new_state && netif_msg_link(priv))
3007                 phy_print_status(phydev);
3008         unlock_tx_qs(priv);
3009         local_irq_restore(flags);
3010 }
3011
3012 /* Update the hash table based on the current list of multicast
3013  * addresses we subscribe to.  Also, change the promiscuity of
3014  * the device based on the flags (this function is called
3015  * whenever dev->flags is changed */
3016 static void gfar_set_multi(struct net_device *dev)
3017 {
3018         struct netdev_hw_addr *ha;
3019         struct gfar_private *priv = netdev_priv(dev);
3020         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3021         u32 tempval;
3022
3023         if (dev->flags & IFF_PROMISC) {
3024                 /* Set RCTRL to PROM */
3025                 tempval = gfar_read(&regs->rctrl);
3026                 tempval |= RCTRL_PROM;
3027                 gfar_write(&regs->rctrl, tempval);
3028         } else {
3029                 /* Set RCTRL to not PROM */
3030                 tempval = gfar_read(&regs->rctrl);
3031                 tempval &= ~(RCTRL_PROM);
3032                 gfar_write(&regs->rctrl, tempval);
3033         }
3034
3035         if (dev->flags & IFF_ALLMULTI) {
3036                 /* Set the hash to rx all multicast frames */
3037                 gfar_write(&regs->igaddr0, 0xffffffff);
3038                 gfar_write(&regs->igaddr1, 0xffffffff);
3039                 gfar_write(&regs->igaddr2, 0xffffffff);
3040                 gfar_write(&regs->igaddr3, 0xffffffff);
3041                 gfar_write(&regs->igaddr4, 0xffffffff);
3042                 gfar_write(&regs->igaddr5, 0xffffffff);
3043                 gfar_write(&regs->igaddr6, 0xffffffff);
3044                 gfar_write(&regs->igaddr7, 0xffffffff);
3045                 gfar_write(&regs->gaddr0, 0xffffffff);
3046                 gfar_write(&regs->gaddr1, 0xffffffff);
3047                 gfar_write(&regs->gaddr2, 0xffffffff);
3048                 gfar_write(&regs->gaddr3, 0xffffffff);
3049                 gfar_write(&regs->gaddr4, 0xffffffff);
3050                 gfar_write(&regs->gaddr5, 0xffffffff);
3051                 gfar_write(&regs->gaddr6, 0xffffffff);
3052                 gfar_write(&regs->gaddr7, 0xffffffff);
3053         } else {
3054                 int em_num;
3055                 int idx;
3056
3057                 /* zero out the hash */
3058                 gfar_write(&regs->igaddr0, 0x0);
3059                 gfar_write(&regs->igaddr1, 0x0);
3060                 gfar_write(&regs->igaddr2, 0x0);
3061                 gfar_write(&regs->igaddr3, 0x0);
3062                 gfar_write(&regs->igaddr4, 0x0);
3063                 gfar_write(&regs->igaddr5, 0x0);
3064                 gfar_write(&regs->igaddr6, 0x0);
3065                 gfar_write(&regs->igaddr7, 0x0);
3066                 gfar_write(&regs->gaddr0, 0x0);
3067                 gfar_write(&regs->gaddr1, 0x0);
3068                 gfar_write(&regs->gaddr2, 0x0);
3069                 gfar_write(&regs->gaddr3, 0x0);
3070                 gfar_write(&regs->gaddr4, 0x0);
3071                 gfar_write(&regs->gaddr5, 0x0);
3072                 gfar_write(&regs->gaddr6, 0x0);
3073                 gfar_write(&regs->gaddr7, 0x0);
3074
3075                 /* If we have extended hash tables, we need to
3076                  * clear the exact match registers to prepare for
3077                  * setting them */
3078                 if (priv->extended_hash) {
3079                         em_num = GFAR_EM_NUM + 1;
3080                         gfar_clear_exact_match(dev);
3081                         idx = 1;
3082                 } else {
3083                         idx = 0;
3084                         em_num = 0;
3085                 }
3086
3087                 if (netdev_mc_empty(dev))
3088                         return;
3089
3090                 /* Parse the list, and set the appropriate bits */
3091                 netdev_for_each_mc_addr(ha, dev) {
3092                         if (idx < em_num) {
3093                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3094                                 idx++;
3095                         } else
3096                                 gfar_set_hash_for_addr(dev, ha->addr);
3097                 }
3098         }
3099 }
3100
3101
3102 /* Clears each of the exact match registers to zero, so they
3103  * don't interfere with normal reception */
3104 static void gfar_clear_exact_match(struct net_device *dev)
3105 {
3106         int idx;
3107         static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3108
3109         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3110                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3111 }
3112
3113 /* Set the appropriate hash bit for the given addr */
3114 /* The algorithm works like so:
3115  * 1) Take the Destination Address (ie the multicast address), and
3116  * do a CRC on it (little endian), and reverse the bits of the
3117  * result.
3118  * 2) Use the 8 most significant bits as a hash into a 256-entry
3119  * table.  The table is controlled through 8 32-bit registers:
3120  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3121  * gaddr7.  This means that the 3 most significant bits in the
3122  * hash index which gaddr register to use, and the 5 other bits
3123  * indicate which bit (assuming an IBM numbering scheme, which
3124  * for PowerPC (tm) is usually the case) in the register holds
3125  * the entry. */
3126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3127 {
3128         u32 tempval;
3129         struct gfar_private *priv = netdev_priv(dev);
3130         u32 result = ether_crc(MAC_ADDR_LEN, addr);
3131         int width = priv->hash_width;
3132         u8 whichbit = (result >> (32 - width)) & 0x1f;
3133         u8 whichreg = result >> (32 - width + 5);
3134         u32 value = (1 << (31-whichbit));
3135
3136         tempval = gfar_read(priv->hash_regs[whichreg]);
3137         tempval |= value;
3138         gfar_write(priv->hash_regs[whichreg], tempval);
3139 }
3140
3141
3142 /* There are multiple MAC Address register pairs on some controllers
3143  * This function sets the numth pair to a given address
3144  */
3145 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3146                                   const u8 *addr)
3147 {
3148         struct gfar_private *priv = netdev_priv(dev);
3149         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3150         int idx;
3151         char tmpbuf[MAC_ADDR_LEN];
3152         u32 tempval;
3153         u32 __iomem *macptr = &regs->macstnaddr1;
3154
3155         macptr += num*2;
3156
3157         /* Now copy it into the mac registers backwards, cuz */
3158         /* little endian is silly */
3159         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3160                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3161
3162         gfar_write(macptr, *((u32 *) (tmpbuf)));
3163
3164         tempval = *((u32 *) (tmpbuf + 4));
3165
3166         gfar_write(macptr+1, tempval);
3167 }
3168
3169 /* GFAR error interrupt handler */
3170 static irqreturn_t gfar_error(int irq, void *grp_id)
3171 {
3172         struct gfar_priv_grp *gfargrp = grp_id;
3173         struct gfar __iomem *regs = gfargrp->regs;
3174         struct gfar_private *priv= gfargrp->priv;
3175         struct net_device *dev = priv->ndev;
3176
3177         /* Save ievent for future reference */
3178         u32 events = gfar_read(&regs->ievent);
3179
3180         /* Clear IEVENT */
3181         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3182
3183         /* Magic Packet is not an error. */
3184         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3185             (events & IEVENT_MAG))
3186                 events &= ~IEVENT_MAG;
3187
3188         /* Hmm... */
3189         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3190                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3191                        dev->name, events, gfar_read(&regs->imask));
3192
3193         /* Update the error counters */
3194         if (events & IEVENT_TXE) {
3195                 dev->stats.tx_errors++;
3196
3197                 if (events & IEVENT_LC)
3198                         dev->stats.tx_window_errors++;
3199                 if (events & IEVENT_CRL)
3200                         dev->stats.tx_aborted_errors++;
3201                 if (events & IEVENT_XFUN) {
3202                         unsigned long flags;
3203
3204                         if (netif_msg_tx_err(priv))
3205                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3206                                        "packet dropped.\n", dev->name);
3207                         dev->stats.tx_dropped++;
3208                         priv->extra_stats.tx_underrun++;
3209
3210                         local_irq_save(flags);
3211                         lock_tx_qs(priv);
3212
3213                         /* Reactivate the Tx Queues */
3214                         gfar_write(&regs->tstat, gfargrp->tstat);
3215
3216                         unlock_tx_qs(priv);
3217                         local_irq_restore(flags);
3218                 }
3219                 if (netif_msg_tx_err(priv))
3220                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3221         }
3222         if (events & IEVENT_BSY) {
3223                 dev->stats.rx_errors++;
3224                 priv->extra_stats.rx_bsy++;
3225
3226                 gfar_receive(irq, grp_id);
3227
3228                 if (netif_msg_rx_err(priv))
3229                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3230                                dev->name, gfar_read(&regs->rstat));
3231         }
3232         if (events & IEVENT_BABR) {
3233                 dev->stats.rx_errors++;
3234                 priv->extra_stats.rx_babr++;
3235
3236                 if (netif_msg_rx_err(priv))
3237                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3238         }
3239         if (events & IEVENT_EBERR) {
3240                 priv->extra_stats.eberr++;
3241                 if (netif_msg_rx_err(priv))
3242                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
3243         }
3244         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3245                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3246
3247         if (events & IEVENT_BABT) {
3248                 priv->extra_stats.tx_babt++;
3249                 if (netif_msg_tx_err(priv))
3250                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3251         }
3252         return IRQ_HANDLED;
3253 }
3254
3255 static struct of_device_id gfar_match[] =
3256 {
3257         {
3258                 .type = "network",
3259                 .compatible = "gianfar",
3260         },
3261         {
3262                 .compatible = "fsl,etsec2",
3263         },
3264         {},
3265 };
3266 MODULE_DEVICE_TABLE(of, gfar_match);
3267
3268 /* Structure for a device driver */
3269 static struct platform_driver gfar_driver = {
3270         .driver = {
3271                 .name = "fsl-gianfar",
3272                 .owner = THIS_MODULE,
3273                 .pm = GFAR_PM_OPS,
3274                 .of_match_table = gfar_match,
3275         },
3276         .probe = gfar_probe,
3277         .remove = gfar_remove,
3278 };
3279
3280 static int __init gfar_init(void)
3281 {
3282         return platform_driver_register(&gfar_driver);
3283 }
3284
3285 static void __exit gfar_exit(void)
3286 {
3287         platform_driver_unregister(&gfar_driver);
3288 }
3289
3290 module_init(gfar_init);
3291 module_exit(gfar_exit);
3292