1 // SPDX-License-Identifier: GPL-2.0+
3 * Faraday 10/100Mbps Ethernet Controller
5 * (C) Copyright 2013 Faraday Technology
6 * Dante Su <dantesu@faraday-tech.com>
14 #include <asm/cache.h>
15 #include <linux/errno.h>
17 #include <linux/dma-mapping.h>
19 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
25 #define CFG_RXDES_NUM 8
26 #define CFG_TXDES_NUM 2
27 #define CFG_XBUF_SIZE 1536
29 #define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
30 #define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
31 #define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
34 * FTMAC110 DMA design issue
36 * Its DMA engine has a weird restriction that its Rx DMA engine
37 * accepts only 16-bits aligned address, 32-bits aligned is not
38 * acceptable. However this restriction does not apply to Tx DMA.
41 * (1) Tx DMA Buffer Address:
42 * 1 bytes aligned: Invalid
43 * 2 bytes aligned: O.K
44 * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
45 * (2) Rx DMA Buffer Address:
46 * 1 bytes aligned: Invalid
47 * 2 bytes aligned: O.K
48 * 4 bytes aligned: Invalid
51 struct ftmac110_chip {
58 struct ftmac110_desc *rxd;
62 struct ftmac110_desc *txd;
67 static int ftmac110_reset(struct eth_device *dev);
69 static uint16_t mdio_read(struct eth_device *dev,
70 uint8_t phyaddr, uint8_t phyreg)
72 struct ftmac110_chip *chip = dev->priv;
73 struct ftmac110_regs *regs = chip->regs;
75 uint16_t ret = 0xffff;
78 | (phyaddr << PHYCR_ADDR_SHIFT)
79 | (phyreg << PHYCR_REG_SHIFT);
81 writel(tmp, ®s->phycr);
83 for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
84 tmp = readl(®s->phycr);
91 printf("ftmac110: mdio read timeout\n");
93 ret = (uint16_t)(tmp & 0xffff);
98 static void mdio_write(struct eth_device *dev,
99 uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
101 struct ftmac110_chip *chip = dev->priv;
102 struct ftmac110_regs *regs = chip->regs;
106 | (phyaddr << PHYCR_ADDR_SHIFT)
107 | (phyreg << PHYCR_REG_SHIFT);
109 writel(phydata, ®s->phydr);
110 writel(tmp, ®s->phycr);
112 for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
113 if (readl(®s->phycr) & PHYCR_WRITE)
118 if (readl(®s->phycr) & PHYCR_WRITE)
119 printf("ftmac110: mdio write timeout\n");
122 static uint32_t ftmac110_phyqry(struct eth_device *dev)
126 uint16_t pa, tmp, bmsr, bmcr;
127 struct ftmac110_chip *chip = dev->priv;
129 /* Default = 100Mbps Full */
130 maccr = MACCR_100M | MACCR_FD;
132 /* 1. find the phy device */
133 for (pa = 0; pa < 32; ++pa) {
134 tmp = mdio_read(dev, pa, MII_PHYSID1);
135 if (tmp == 0xFFFF || tmp == 0x0000)
141 puts("ftmac110: phy device not found!\n");
145 /* 2. wait until link-up & auto-negotiation complete */
147 bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
150 bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
151 chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
154 if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
156 } while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
158 puts("ftmac110: link down\n");
161 if (!(bmcr & BMCR_ANENABLE))
162 puts("ftmac110: auto negotiation disabled\n");
163 else if (!(bmsr & BMSR_ANEGCOMPLETE))
164 puts("ftmac110: auto negotiation timeout\n");
166 /* 3. derive MACCR */
167 if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
168 tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
169 tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
170 if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
171 maccr = MACCR_100M | MACCR_FD;
172 else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
174 else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
176 else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
179 if (bmcr & BMCR_SPEED100)
183 if (bmcr & BMCR_FULLDPLX)
188 printf("ftmac110: %d Mbps, %s\n",
189 (maccr & MACCR_100M) ? 100 : 10,
190 (maccr & MACCR_FD) ? "Full" : "half");
194 static int ftmac110_reset(struct eth_device *dev)
198 struct ftmac110_chip *chip = dev->priv;
199 struct ftmac110_regs *regs = chip->regs;
202 writel(MACCR_RESET, ®s->maccr);
203 for (i = get_timer(0); get_timer(i) < 1000; ) {
204 if (readl(®s->maccr) & MACCR_RESET)
208 if (readl(®s->maccr) & MACCR_RESET) {
209 printf("ftmac110: reset failed\n");
213 /* 1-1. Init tx ring */
214 for (i = 0; i < CFG_TXDES_NUM; ++i) {
216 chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
220 /* 1-2. Init rx ring */
221 for (i = 0; i < CFG_RXDES_NUM; ++i) {
223 chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
224 chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
228 /* 2. PHY status query */
229 maccr = ftmac110_phyqry(dev);
231 /* 3. Fix up the MACCR value */
232 chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
233 | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
235 /* 4. MAC address setup */
237 writel(a[1] | (a[0] << 8), ®s->mac[0]);
238 writel(a[5] | (a[4] << 8) | (a[3] << 16)
239 | (a[2] << 24), ®s->mac[1]);
241 /* 5. MAC registers setup */
242 writel(chip->rxd_dma, ®s->rxba);
243 writel(chip->txd_dma, ®s->txba);
244 /* interrupt at each tx/rx */
245 writel(ITC_DEFAULT, ®s->itc);
246 /* no tx pool, rx poll = 1 normal cycle */
247 writel(APTC_DEFAULT, ®s->aptc);
248 /* rx threshold = [6/8 fifo, 2/8 fifo] */
249 writel(DBLAC_DEFAULT, ®s->dblac);
250 /* disable & clear all interrupt status */
252 writel(ISR_ALL, ®s->isr);
253 writel(chip->imr, ®s->imr);
255 writel(chip->maccr, ®s->maccr);
260 static int ftmac110_probe(struct eth_device *dev, bd_t *bis)
262 debug("ftmac110: probe\n");
264 if (ftmac110_reset(dev))
270 static void ftmac110_halt(struct eth_device *dev)
272 struct ftmac110_chip *chip = dev->priv;
273 struct ftmac110_regs *regs = chip->regs;
275 writel(0, ®s->imr);
276 writel(0, ®s->maccr);
278 debug("ftmac110: halt\n");
281 static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
283 struct ftmac110_chip *chip = dev->priv;
284 struct ftmac110_regs *regs = chip->regs;
285 struct ftmac110_desc *txd;
291 if (len <= 0 || len > CFG_XBUF_SIZE) {
292 printf("ftmac110: bad tx pkt len(%d)\n", len);
298 txd = &chip->txd[chip->txd_idx];
299 ctrl = le64_to_cpu(txd->ctrl);
300 if (ctrl & FTMAC110_TXD_OWNER) {
301 /* kick-off Tx DMA */
302 writel(0xffffffff, ®s->txpd);
303 printf("ftmac110: out of txd\n");
307 memcpy(txd->vbuf, (void *)pkt, len);
308 dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
310 /* clear control bits */
311 ctrl &= FTMAC110_TXD_CLRMASK;
312 /* set len, fts and lts */
313 ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
315 ctrl |= FTMAC110_TXD_OWNER;
316 /* write back to descriptor */
317 txd->ctrl = cpu_to_le64(ctrl);
319 /* kick-off Tx DMA */
320 writel(0xffffffff, ®s->txpd);
322 chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
327 static int ftmac110_recv(struct eth_device *dev)
329 struct ftmac110_chip *chip = dev->priv;
330 struct ftmac110_desc *rxd;
331 uint32_t len, rlen = 0;
339 rxd = &chip->rxd[chip->rxd_idx];
340 ctrl = le64_to_cpu(rxd->ctrl);
341 if (ctrl & FTMAC110_RXD_OWNER)
344 len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
347 if (ctrl & FTMAC110_RXD_ERRMASK) {
348 printf("ftmac110: rx error\n");
350 dma_map_single(buf, len, DMA_FROM_DEVICE);
351 net_process_received_packet(buf, len);
355 /* owned by hardware */
356 ctrl &= FTMAC110_RXD_CLRMASK;
357 ctrl |= FTMAC110_RXD_OWNER;
358 rxd->ctrl |= cpu_to_le64(ctrl);
360 chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
366 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
368 static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
373 struct eth_device *dev;
375 dev = eth_get_dev_by_name(bus->name);
377 printf("%s: no such device\n", bus->name);
380 value = mdio_read(dev, addr, reg);
388 static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
392 struct eth_device *dev;
394 dev = eth_get_dev_by_name(bus->name);
396 printf("%s: no such device\n", bus->name);
399 mdio_write(dev, addr, reg, value);
405 #endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
407 int ftmac110_initialize(bd_t *bis)
410 struct eth_device *dev;
411 struct ftmac110_chip *chip;
413 dev = malloc(sizeof(*dev) + sizeof(*chip));
415 panic("ftmac110: out of memory 1\n");
418 chip = (struct ftmac110_chip *)(dev + 1);
419 memset(dev, 0, sizeof(*dev) + sizeof(*chip));
421 sprintf(dev->name, "FTMAC110#%d", card_nr);
423 dev->iobase = CONFIG_FTMAC110_BASE;
424 chip->regs = (void __iomem *)dev->iobase;
426 dev->init = ftmac110_probe;
427 dev->halt = ftmac110_halt;
428 dev->send = ftmac110_send;
429 dev->recv = ftmac110_recv;
431 /* allocate tx descriptors (it must be 16 bytes aligned) */
432 chip->txd = dma_alloc_coherent(
433 sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
435 panic("ftmac110: out of memory 3\n");
437 sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
438 for (i = 0; i < CFG_TXDES_NUM; ++i) {
439 void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
442 panic("ftmac110: out of memory 4\n");
443 chip->txd[i].vbuf = va;
444 chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
445 chip->txd[i].ctrl = 0; /* owned by SW */
447 chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
450 /* allocate rx descriptors (it must be 16 bytes aligned) */
451 chip->rxd = dma_alloc_coherent(
452 sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
454 panic("ftmac110: out of memory 4\n");
455 memset((void *)chip->rxd, 0,
456 sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
457 for (i = 0; i < CFG_RXDES_NUM; ++i) {
458 void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
461 panic("ftmac110: out of memory 5\n");
462 /* it needs to be exactly 2 bytes aligned */
463 va = ((uint8_t *)va + 2);
464 chip->rxd[i].vbuf = va;
465 chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
466 chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
467 | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
469 chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
474 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
476 struct mii_dev *mdiodev = mdio_alloc();
479 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
480 mdiodev->read = ftmac110_mdio_read;
481 mdiodev->write = ftmac110_mdio_write;
483 retval = mdio_register(mdiodev);