1 // SPDX-License-Identifier: GPL-2.0+
3 * Faraday 10/100Mbps Ethernet Controller
5 * (C) Copyright 2013 Faraday Technology
6 * Dante Su <dantesu@faraday-tech.com>
13 #include <linux/errno.h>
15 #include <asm/dma-mapping.h>
17 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
23 #define CFG_RXDES_NUM 8
24 #define CFG_TXDES_NUM 2
25 #define CFG_XBUF_SIZE 1536
27 #define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
28 #define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
29 #define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
32 * FTMAC110 DMA design issue
34 * Its DMA engine has a weird restriction that its Rx DMA engine
35 * accepts only 16-bits aligned address, 32-bits aligned is not
36 * acceptable. However this restriction does not apply to Tx DMA.
39 * (1) Tx DMA Buffer Address:
40 * 1 bytes aligned: Invalid
41 * 2 bytes aligned: O.K
42 * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
43 * (2) Rx DMA Buffer Address:
44 * 1 bytes aligned: Invalid
45 * 2 bytes aligned: O.K
46 * 4 bytes aligned: Invalid
49 struct ftmac110_chip {
56 struct ftmac110_desc *rxd;
60 struct ftmac110_desc *txd;
65 static int ftmac110_reset(struct eth_device *dev);
67 static uint16_t mdio_read(struct eth_device *dev,
68 uint8_t phyaddr, uint8_t phyreg)
70 struct ftmac110_chip *chip = dev->priv;
71 struct ftmac110_regs *regs = chip->regs;
73 uint16_t ret = 0xffff;
76 | (phyaddr << PHYCR_ADDR_SHIFT)
77 | (phyreg << PHYCR_REG_SHIFT);
79 writel(tmp, ®s->phycr);
81 for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
82 tmp = readl(®s->phycr);
89 printf("ftmac110: mdio read timeout\n");
91 ret = (uint16_t)(tmp & 0xffff);
96 static void mdio_write(struct eth_device *dev,
97 uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
99 struct ftmac110_chip *chip = dev->priv;
100 struct ftmac110_regs *regs = chip->regs;
104 | (phyaddr << PHYCR_ADDR_SHIFT)
105 | (phyreg << PHYCR_REG_SHIFT);
107 writel(phydata, ®s->phydr);
108 writel(tmp, ®s->phycr);
110 for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
111 if (readl(®s->phycr) & PHYCR_WRITE)
116 if (readl(®s->phycr) & PHYCR_WRITE)
117 printf("ftmac110: mdio write timeout\n");
120 static uint32_t ftmac110_phyqry(struct eth_device *dev)
124 uint16_t pa, tmp, bmsr, bmcr;
125 struct ftmac110_chip *chip = dev->priv;
127 /* Default = 100Mbps Full */
128 maccr = MACCR_100M | MACCR_FD;
130 /* 1. find the phy device */
131 for (pa = 0; pa < 32; ++pa) {
132 tmp = mdio_read(dev, pa, MII_PHYSID1);
133 if (tmp == 0xFFFF || tmp == 0x0000)
139 puts("ftmac110: phy device not found!\n");
143 /* 2. wait until link-up & auto-negotiation complete */
145 bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
148 bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
149 chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
152 if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
154 } while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
156 puts("ftmac110: link down\n");
159 if (!(bmcr & BMCR_ANENABLE))
160 puts("ftmac110: auto negotiation disabled\n");
161 else if (!(bmsr & BMSR_ANEGCOMPLETE))
162 puts("ftmac110: auto negotiation timeout\n");
164 /* 3. derive MACCR */
165 if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
166 tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
167 tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
168 if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
169 maccr = MACCR_100M | MACCR_FD;
170 else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
172 else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
174 else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
177 if (bmcr & BMCR_SPEED100)
181 if (bmcr & BMCR_FULLDPLX)
186 printf("ftmac110: %d Mbps, %s\n",
187 (maccr & MACCR_100M) ? 100 : 10,
188 (maccr & MACCR_FD) ? "Full" : "half");
192 static int ftmac110_reset(struct eth_device *dev)
196 struct ftmac110_chip *chip = dev->priv;
197 struct ftmac110_regs *regs = chip->regs;
200 writel(MACCR_RESET, ®s->maccr);
201 for (i = get_timer(0); get_timer(i) < 1000; ) {
202 if (readl(®s->maccr) & MACCR_RESET)
206 if (readl(®s->maccr) & MACCR_RESET) {
207 printf("ftmac110: reset failed\n");
211 /* 1-1. Init tx ring */
212 for (i = 0; i < CFG_TXDES_NUM; ++i) {
214 chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
218 /* 1-2. Init rx ring */
219 for (i = 0; i < CFG_RXDES_NUM; ++i) {
221 chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
222 chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
226 /* 2. PHY status query */
227 maccr = ftmac110_phyqry(dev);
229 /* 3. Fix up the MACCR value */
230 chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
231 | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
233 /* 4. MAC address setup */
235 writel(a[1] | (a[0] << 8), ®s->mac[0]);
236 writel(a[5] | (a[4] << 8) | (a[3] << 16)
237 | (a[2] << 24), ®s->mac[1]);
239 /* 5. MAC registers setup */
240 writel(chip->rxd_dma, ®s->rxba);
241 writel(chip->txd_dma, ®s->txba);
242 /* interrupt at each tx/rx */
243 writel(ITC_DEFAULT, ®s->itc);
244 /* no tx pool, rx poll = 1 normal cycle */
245 writel(APTC_DEFAULT, ®s->aptc);
246 /* rx threshold = [6/8 fifo, 2/8 fifo] */
247 writel(DBLAC_DEFAULT, ®s->dblac);
248 /* disable & clear all interrupt status */
250 writel(ISR_ALL, ®s->isr);
251 writel(chip->imr, ®s->imr);
253 writel(chip->maccr, ®s->maccr);
258 static int ftmac110_probe(struct eth_device *dev, bd_t *bis)
260 debug("ftmac110: probe\n");
262 if (ftmac110_reset(dev))
268 static void ftmac110_halt(struct eth_device *dev)
270 struct ftmac110_chip *chip = dev->priv;
271 struct ftmac110_regs *regs = chip->regs;
273 writel(0, ®s->imr);
274 writel(0, ®s->maccr);
276 debug("ftmac110: halt\n");
279 static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
281 struct ftmac110_chip *chip = dev->priv;
282 struct ftmac110_regs *regs = chip->regs;
283 struct ftmac110_desc *txd;
289 if (len <= 0 || len > CFG_XBUF_SIZE) {
290 printf("ftmac110: bad tx pkt len(%d)\n", len);
296 txd = &chip->txd[chip->txd_idx];
297 ctrl = le64_to_cpu(txd->ctrl);
298 if (ctrl & FTMAC110_TXD_OWNER) {
299 /* kick-off Tx DMA */
300 writel(0xffffffff, ®s->txpd);
301 printf("ftmac110: out of txd\n");
305 memcpy(txd->vbuf, (void *)pkt, len);
306 dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
308 /* clear control bits */
309 ctrl &= FTMAC110_TXD_CLRMASK;
310 /* set len, fts and lts */
311 ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
313 ctrl |= FTMAC110_TXD_OWNER;
314 /* write back to descriptor */
315 txd->ctrl = cpu_to_le64(ctrl);
317 /* kick-off Tx DMA */
318 writel(0xffffffff, ®s->txpd);
320 chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
325 static int ftmac110_recv(struct eth_device *dev)
327 struct ftmac110_chip *chip = dev->priv;
328 struct ftmac110_desc *rxd;
329 uint32_t len, rlen = 0;
337 rxd = &chip->rxd[chip->rxd_idx];
338 ctrl = le64_to_cpu(rxd->ctrl);
339 if (ctrl & FTMAC110_RXD_OWNER)
342 len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
345 if (ctrl & FTMAC110_RXD_ERRMASK) {
346 printf("ftmac110: rx error\n");
348 dma_map_single(buf, len, DMA_FROM_DEVICE);
349 net_process_received_packet(buf, len);
353 /* owned by hardware */
354 ctrl &= FTMAC110_RXD_CLRMASK;
355 ctrl |= FTMAC110_RXD_OWNER;
356 rxd->ctrl |= cpu_to_le64(ctrl);
358 chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
364 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
366 static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
371 struct eth_device *dev;
373 dev = eth_get_dev_by_name(bus->name);
375 printf("%s: no such device\n", bus->name);
378 value = mdio_read(dev, addr, reg);
386 static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
390 struct eth_device *dev;
392 dev = eth_get_dev_by_name(bus->name);
394 printf("%s: no such device\n", bus->name);
397 mdio_write(dev, addr, reg, value);
403 #endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
405 int ftmac110_initialize(bd_t *bis)
408 struct eth_device *dev;
409 struct ftmac110_chip *chip;
411 dev = malloc(sizeof(*dev) + sizeof(*chip));
413 panic("ftmac110: out of memory 1\n");
416 chip = (struct ftmac110_chip *)(dev + 1);
417 memset(dev, 0, sizeof(*dev) + sizeof(*chip));
419 sprintf(dev->name, "FTMAC110#%d", card_nr);
421 dev->iobase = CONFIG_FTMAC110_BASE;
422 chip->regs = (void __iomem *)dev->iobase;
424 dev->init = ftmac110_probe;
425 dev->halt = ftmac110_halt;
426 dev->send = ftmac110_send;
427 dev->recv = ftmac110_recv;
429 /* allocate tx descriptors (it must be 16 bytes aligned) */
430 chip->txd = dma_alloc_coherent(
431 sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
433 panic("ftmac110: out of memory 3\n");
435 sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
436 for (i = 0; i < CFG_TXDES_NUM; ++i) {
437 void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
440 panic("ftmac110: out of memory 4\n");
441 chip->txd[i].vbuf = va;
442 chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
443 chip->txd[i].ctrl = 0; /* owned by SW */
445 chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
448 /* allocate rx descriptors (it must be 16 bytes aligned) */
449 chip->rxd = dma_alloc_coherent(
450 sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
452 panic("ftmac110: out of memory 4\n");
453 memset((void *)chip->rxd, 0,
454 sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
455 for (i = 0; i < CFG_RXDES_NUM; ++i) {
456 void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
459 panic("ftmac110: out of memory 5\n");
460 /* it needs to be exactly 2 bytes aligned */
461 va = ((uint8_t *)va + 2);
462 chip->rxd[i].vbuf = va;
463 chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
464 chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
465 | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
467 chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
472 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
474 struct mii_dev *mdiodev = mdio_alloc();
477 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
478 mdiodev->read = ftmac110_mdio_read;
479 mdiodev->write = ftmac110_mdio_write;
481 retval = mdio_register(mdiodev);