1 // SPDX-License-Identifier: GPL-2.0+
3 * Faraday FTGMAC100 Ethernet
5 * (C) Copyright 2009 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
8 * (C) Copyright 2010 Andes Technology
9 * Macpaul Lin <macpaul@andestech.com>
11 * Copyright (C) 2018, IBM Corporation.
23 #include <asm/cache.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
27 #include <linux/iopoll.h>
29 #include "ftgmac100.h"
31 /* Min frame ethernet frame size without FCS */
34 /* Receive Buffer Size Register - HW default is 0x640 */
35 #define FTGMAC100_RBSR_DEFAULT 0x640
37 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
38 #define PKTBUFSTX 4 /* must be power of 2 */
40 /* Timeout for transmit */
41 #define FTGMAC100_TX_TIMEOUT_MS 1000
43 /* Timeout for a mdio read/write operation */
44 #define FTGMAC100_MDIO_TIMEOUT_USEC 10000
47 * MDC clock cycle threshold
49 * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
51 #define MDC_CYCTHR 0x34
54 * ftgmac100 model variants
56 enum ftgmac100_model {
57 FTGMAC100_MODEL_FARADAY,
58 FTGMAC100_MODEL_ASPEED,
62 * struct ftgmac100_data - private data for the FTGMAC100 driver
64 * @iobase: The base address of the hardware registers
65 * @txdes: The array of transmit descriptors
66 * @rxdes: The array of receive descriptors
67 * @tx_index: Transmit descriptor index in @txdes
68 * @rx_index: Receive descriptor index in @rxdes
69 * @phy_addr: The PHY interface address to use
70 * @phydev: The PHY device backing the MAC
72 * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
73 * @max_speed: Maximum speed of Ethernet connection supported by MAC
74 * @clks: The bulk of clocks assigned to the device in the DT
75 * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
76 * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
78 struct ftgmac100_data {
79 struct ftgmac100 *iobase;
81 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
82 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
87 struct phy_device *phydev;
94 /* End of RX/TX ring buffer bits. Depend on model */
95 u32 rxdes0_edorr_mask;
96 u32 txdes0_edotr_mask;
100 * struct mii_bus functions
102 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
105 struct ftgmac100_data *priv = bus->priv;
106 struct ftgmac100 *ftgmac100 = priv->iobase;
111 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
112 FTGMAC100_PHYCR_PHYAD(phy_addr) |
113 FTGMAC100_PHYCR_REGAD(reg_addr) |
114 FTGMAC100_PHYCR_MIIRD;
115 writel(phycr, &ftgmac100->phycr);
117 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
118 !(phycr & FTGMAC100_PHYCR_MIIRD),
119 FTGMAC100_MDIO_TIMEOUT_USEC);
121 pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
122 bus->name, phy_addr, reg_addr);
126 data = readl(&ftgmac100->phydata);
128 return FTGMAC100_PHYDATA_MIIRDATA(data);
131 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
132 int reg_addr, u16 value)
134 struct ftgmac100_data *priv = bus->priv;
135 struct ftgmac100 *ftgmac100 = priv->iobase;
140 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
141 FTGMAC100_PHYCR_PHYAD(phy_addr) |
142 FTGMAC100_PHYCR_REGAD(reg_addr) |
143 FTGMAC100_PHYCR_MIIWR;
144 data = FTGMAC100_PHYDATA_MIIWDATA(value);
146 writel(data, &ftgmac100->phydata);
147 writel(phycr, &ftgmac100->phycr);
149 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
150 !(phycr & FTGMAC100_PHYCR_MIIWR),
151 FTGMAC100_MDIO_TIMEOUT_USEC);
153 pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
154 bus->name, phy_addr, reg_addr);
160 static int ftgmac100_mdio_init(struct udevice *dev)
162 struct ftgmac100_data *priv = dev_get_priv(dev);
170 bus->read = ftgmac100_mdio_read;
171 bus->write = ftgmac100_mdio_write;
174 ret = mdio_register_seq(bus, dev_seq(dev));
185 static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
187 struct ftgmac100 *ftgmac100 = priv->iobase;
188 struct phy_device *phydev = priv->phydev;
191 if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) {
192 dev_err(phydev->dev, "No link\n");
196 /* read MAC control register and clear related bits */
197 maccr = readl(&ftgmac100->maccr) &
198 ~(FTGMAC100_MACCR_GIGA_MODE |
199 FTGMAC100_MACCR_FAST_MODE |
200 FTGMAC100_MACCR_FULLDUP);
202 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
203 maccr |= FTGMAC100_MACCR_GIGA_MODE;
205 if (phydev->speed == 100)
206 maccr |= FTGMAC100_MACCR_FAST_MODE;
209 maccr |= FTGMAC100_MACCR_FULLDUP;
211 /* update MII config into maccr */
212 writel(maccr, &ftgmac100->maccr);
217 static int ftgmac100_phy_init(struct udevice *dev)
219 struct ftgmac100_data *priv = dev_get_priv(dev);
220 struct phy_device *phydev;
223 if (IS_ENABLED(CONFIG_DM_MDIO))
224 phydev = dm_eth_phy_connect(dev);
226 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
231 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
232 phydev->supported &= PHY_GBIT_FEATURES;
233 if (priv->max_speed) {
234 ret = phy_set_supported(phydev, priv->max_speed);
238 phydev->advertising = phydev->supported;
239 priv->phydev = phydev;
248 static void ftgmac100_reset(struct ftgmac100_data *priv)
250 struct ftgmac100 *ftgmac100 = priv->iobase;
252 debug("%s()\n", __func__);
254 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
256 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
263 static int ftgmac100_set_mac(struct ftgmac100_data *priv,
264 const unsigned char *mac)
266 struct ftgmac100 *ftgmac100 = priv->iobase;
267 unsigned int maddr = mac[0] << 8 | mac[1];
268 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
270 debug("%s(%x %x)\n", __func__, maddr, laddr);
272 writel(maddr, &ftgmac100->mac_madr);
273 writel(laddr, &ftgmac100->mac_ladr);
281 static int ftgmac100_get_mac(struct ftgmac100_data *priv,
284 struct ftgmac100 *ftgmac100 = priv->iobase;
285 unsigned int maddr = readl(&ftgmac100->mac_madr);
286 unsigned int laddr = readl(&ftgmac100->mac_ladr);
288 debug("%s(%x %x)\n", __func__, maddr, laddr);
290 mac[0] = (maddr >> 8) & 0xff;
291 mac[1] = maddr & 0xff;
292 mac[2] = (laddr >> 24) & 0xff;
293 mac[3] = (laddr >> 16) & 0xff;
294 mac[4] = (laddr >> 8) & 0xff;
295 mac[5] = laddr & 0xff;
301 * disable transmitter, receiver
303 static void ftgmac100_stop(struct udevice *dev)
305 struct ftgmac100_data *priv = dev_get_priv(dev);
306 struct ftgmac100 *ftgmac100 = priv->iobase;
308 debug("%s()\n", __func__);
310 writel(0, &ftgmac100->maccr);
312 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
313 phy_shutdown(priv->phydev);
316 static int ftgmac100_start(struct udevice *dev)
318 struct eth_pdata *plat = dev_get_plat(dev);
319 struct ftgmac100_data *priv = dev_get_priv(dev);
320 struct ftgmac100 *ftgmac100 = priv->iobase;
321 struct phy_device *phydev = priv->phydev;
327 debug("%s()\n", __func__);
329 ftgmac100_reset(priv);
331 /* set the ethernet address */
332 ftgmac100_set_mac(priv, plat->enetaddr);
334 /* disable all interrupts */
335 writel(0, &ftgmac100->ier);
337 /* initialize descriptors */
341 for (i = 0; i < PKTBUFSTX; i++) {
342 priv->txdes[i].txdes3 = 0;
343 priv->txdes[i].txdes0 = 0;
345 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
347 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
348 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
349 flush_dcache_range(start, end);
351 for (i = 0; i < PKTBUFSRX; i++) {
352 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
353 priv->rxdes[i].rxdes0 = 0;
355 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
357 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
358 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
359 flush_dcache_range(start, end);
362 writel((u32)priv->txdes, &ftgmac100->txr_badr);
365 writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
367 /* poll receive descriptor automatically */
368 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
370 /* config receive buffer size register */
371 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
373 /* enable transmitter, receiver */
374 maccr = FTGMAC100_MACCR_TXMAC_EN |
375 FTGMAC100_MACCR_RXMAC_EN |
376 FTGMAC100_MACCR_TXDMA_EN |
377 FTGMAC100_MACCR_RXDMA_EN |
378 FTGMAC100_MACCR_CRC_APD |
379 FTGMAC100_MACCR_FULLDUP |
380 FTGMAC100_MACCR_RX_RUNT |
381 FTGMAC100_MACCR_RX_BROADPKT;
383 writel(maccr, &ftgmac100->maccr);
385 ret = phy_startup(phydev);
387 dev_err(phydev->dev, "Could not start PHY\n");
391 ret = ftgmac100_phy_adjust_link(priv);
393 dev_err(phydev->dev, "Could not adjust link\n");
397 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
398 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
403 static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
405 struct ftgmac100_data *priv = dev_get_priv(dev);
406 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
407 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
408 ulong des_end = des_start +
409 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
411 /* Release buffer to DMA and flush descriptor */
412 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
413 flush_dcache_range(des_start, des_end);
415 /* Move to next descriptor */
416 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
422 * Get a data block via Ethernet
424 static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
426 struct ftgmac100_data *priv = dev_get_priv(dev);
427 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
428 unsigned short rxlen;
429 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
430 ulong des_end = des_start +
431 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
432 ulong data_start = curr_des->rxdes3;
435 invalidate_dcache_range(des_start, des_end);
437 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
440 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
441 FTGMAC100_RXDES0_CRC_ERR |
442 FTGMAC100_RXDES0_FTL |
443 FTGMAC100_RXDES0_RUNT |
444 FTGMAC100_RXDES0_RX_ODD_NB)) {
448 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
450 debug("%s(): RX buffer %d, %x received\n",
451 __func__, priv->rx_index, rxlen);
453 /* Invalidate received data */
454 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
455 invalidate_dcache_range(data_start, data_end);
456 *packetp = (uchar *)data_start;
461 static u32 ftgmac100_read_txdesc(const void *desc)
463 const struct ftgmac100_txdes *txdes = desc;
464 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
465 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
467 invalidate_dcache_range(des_start, des_end);
469 return txdes->txdes0;
472 BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
475 * Send a data block via Ethernet
477 static int ftgmac100_send(struct udevice *dev, void *packet, int length)
479 struct ftgmac100_data *priv = dev_get_priv(dev);
480 struct ftgmac100 *ftgmac100 = priv->iobase;
481 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
482 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
483 ulong des_end = des_start +
484 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
489 invalidate_dcache_range(des_start, des_end);
491 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
492 dev_err(dev, "no TX descriptor available\n");
496 debug("%s(%x, %x)\n", __func__, (int)packet, length);
498 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
500 curr_des->txdes3 = (unsigned int)packet;
502 /* Flush data to be sent */
503 data_start = curr_des->txdes3;
504 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
505 flush_dcache_range(data_start, data_end);
507 /* Only one segment on TXBUF */
508 curr_des->txdes0 &= priv->txdes0_edotr_mask;
509 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
510 FTGMAC100_TXDES0_LTS |
511 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
512 FTGMAC100_TXDES0_TXDMA_OWN ;
514 /* Flush modified buffer descriptor */
515 flush_dcache_range(des_start, des_end);
518 writel(1, &ftgmac100->txpd);
520 rc = wait_for_bit_ftgmac100_txdone(curr_des,
521 FTGMAC100_TXDES0_TXDMA_OWN, false,
522 FTGMAC100_TX_TIMEOUT_MS, true);
526 debug("%s(): packet sent\n", __func__);
528 /* Move to next descriptor */
529 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
534 static int ftgmac100_write_hwaddr(struct udevice *dev)
536 struct eth_pdata *pdata = dev_get_plat(dev);
537 struct ftgmac100_data *priv = dev_get_priv(dev);
539 return ftgmac100_set_mac(priv, pdata->enetaddr);
542 static int ftgmac_read_hwaddr(struct udevice *dev)
544 struct eth_pdata *pdata = dev_get_plat(dev);
545 struct ftgmac100_data *priv = dev_get_priv(dev);
547 return ftgmac100_get_mac(priv, pdata->enetaddr);
550 static int ftgmac100_of_to_plat(struct udevice *dev)
552 struct eth_pdata *pdata = dev_get_plat(dev);
553 struct ftgmac100_data *priv = dev_get_priv(dev);
555 pdata->iobase = dev_read_addr(dev);
557 pdata->phy_interface = dev_read_phy_mode(dev);
558 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
561 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
563 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
564 priv->rxdes0_edorr_mask = BIT(30);
565 priv->txdes0_edotr_mask = BIT(30);
567 priv->rxdes0_edorr_mask = BIT(15);
568 priv->txdes0_edotr_mask = BIT(15);
571 return clk_get_bulk(dev, &priv->clks);
574 static int ftgmac100_probe(struct udevice *dev)
576 struct eth_pdata *pdata = dev_get_plat(dev);
577 struct ftgmac100_data *priv = dev_get_priv(dev);
580 priv->iobase = (struct ftgmac100 *)pdata->iobase;
581 priv->phy_mode = pdata->phy_interface;
582 priv->max_speed = pdata->max_speed;
585 if (dev_read_bool(dev, "use-ncsi"))
586 priv->phy_mode = PHY_INTERFACE_MODE_NCSI;
588 #ifdef CONFIG_PHY_ADDR
589 priv->phy_addr = CONFIG_PHY_ADDR;
592 ret = clk_enable_bulk(&priv->clks);
597 * If DM MDIO is enabled, the MDIO bus will be initialized later in
600 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI &&
601 !IS_ENABLED(CONFIG_DM_MDIO)) {
602 ret = ftgmac100_mdio_init(dev);
604 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
609 ret = ftgmac100_phy_init(dev);
611 dev_err(dev, "Failed to initialize PHY: %d\n", ret);
615 ftgmac_read_hwaddr(dev);
619 clk_release_bulk(&priv->clks);
624 static int ftgmac100_remove(struct udevice *dev)
626 struct ftgmac100_data *priv = dev_get_priv(dev);
629 mdio_unregister(priv->bus);
630 mdio_free(priv->bus);
631 clk_release_bulk(&priv->clks);
636 static const struct eth_ops ftgmac100_ops = {
637 .start = ftgmac100_start,
638 .send = ftgmac100_send,
639 .recv = ftgmac100_recv,
640 .stop = ftgmac100_stop,
641 .free_pkt = ftgmac100_free_pkt,
642 .write_hwaddr = ftgmac100_write_hwaddr,
645 static const struct udevice_id ftgmac100_ids[] = {
646 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
647 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
648 { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
652 U_BOOT_DRIVER(ftgmac100) = {
655 .of_match = ftgmac100_ids,
656 .of_to_plat = ftgmac100_of_to_plat,
657 .probe = ftgmac100_probe,
658 .remove = ftgmac100_remove,
659 .ops = &ftgmac100_ops,
660 .priv_auto = sizeof(struct ftgmac100_data),
661 .plat_auto = sizeof(struct eth_pdata),
662 .flags = DM_FLAG_ALLOC_PRIV_DMA,