1 // SPDX-License-Identifier: GPL-2.0+
3 * Faraday FTGMAC100 Ethernet
5 * (C) Copyright 2009 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
8 * (C) Copyright 2010 Andes Technology
9 * Macpaul Lin <macpaul@andestech.com>
11 * Copyright (C) 2018, IBM Corporation.
23 #include <asm/cache.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
27 #include <linux/iopoll.h>
29 #include "ftgmac100.h"
31 /* Min frame ethernet frame size without FCS */
34 /* Receive Buffer Size Register - HW default is 0x640 */
35 #define FTGMAC100_RBSR_DEFAULT 0x640
37 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
38 #define PKTBUFSTX 4 /* must be power of 2 */
40 /* Timeout for transmit */
41 #define FTGMAC100_TX_TIMEOUT_MS 1000
43 /* Timeout for a mdio read/write operation */
44 #define FTGMAC100_MDIO_TIMEOUT_USEC 10000
47 * MDC clock cycle threshold
49 * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
51 #define MDC_CYCTHR 0x34
54 * ftgmac100 model variants
56 enum ftgmac100_model {
57 FTGMAC100_MODEL_FARADAY,
58 FTGMAC100_MODEL_ASPEED,
62 * struct ftgmac100_data - private data for the FTGMAC100 driver
64 * @iobase: The base address of the hardware registers
65 * @txdes: The array of transmit descriptors
66 * @rxdes: The array of receive descriptors
67 * @tx_index: Transmit descriptor index in @txdes
68 * @rx_index: Receive descriptor index in @rxdes
69 * @phy_addr: The PHY interface address to use
70 * @phydev: The PHY device backing the MAC
72 * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
73 * @max_speed: Maximum speed of Ethernet connection supported by MAC
74 * @clks: The bulk of clocks assigned to the device in the DT
75 * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
76 * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
78 struct ftgmac100_data {
79 struct ftgmac100 *iobase;
81 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
82 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
87 struct phy_device *phydev;
94 /* End of RX/TX ring buffer bits. Depend on model */
95 u32 rxdes0_edorr_mask;
96 u32 txdes0_edotr_mask;
100 * struct mii_bus functions
102 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
105 struct ftgmac100_data *priv = bus->priv;
106 struct ftgmac100 *ftgmac100 = priv->iobase;
111 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
112 FTGMAC100_PHYCR_PHYAD(phy_addr) |
113 FTGMAC100_PHYCR_REGAD(reg_addr) |
114 FTGMAC100_PHYCR_MIIRD;
115 writel(phycr, &ftgmac100->phycr);
117 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
118 !(phycr & FTGMAC100_PHYCR_MIIRD),
119 FTGMAC100_MDIO_TIMEOUT_USEC);
121 pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
122 priv->phydev->dev->name, phy_addr, reg_addr);
126 data = readl(&ftgmac100->phydata);
128 return FTGMAC100_PHYDATA_MIIRDATA(data);
131 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
132 int reg_addr, u16 value)
134 struct ftgmac100_data *priv = bus->priv;
135 struct ftgmac100 *ftgmac100 = priv->iobase;
140 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
141 FTGMAC100_PHYCR_PHYAD(phy_addr) |
142 FTGMAC100_PHYCR_REGAD(reg_addr) |
143 FTGMAC100_PHYCR_MIIWR;
144 data = FTGMAC100_PHYDATA_MIIWDATA(value);
146 writel(data, &ftgmac100->phydata);
147 writel(phycr, &ftgmac100->phycr);
149 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
150 !(phycr & FTGMAC100_PHYCR_MIIWR),
151 FTGMAC100_MDIO_TIMEOUT_USEC);
153 pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
154 priv->phydev->dev->name, phy_addr, reg_addr);
160 static int ftgmac100_mdio_init(struct udevice *dev)
162 struct ftgmac100_data *priv = dev_get_priv(dev);
170 bus->read = ftgmac100_mdio_read;
171 bus->write = ftgmac100_mdio_write;
174 ret = mdio_register_seq(bus, dev_seq(dev));
185 static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
187 struct ftgmac100 *ftgmac100 = priv->iobase;
188 struct phy_device *phydev = priv->phydev;
192 dev_err(phydev->dev, "No link\n");
196 /* read MAC control register and clear related bits */
197 maccr = readl(&ftgmac100->maccr) &
198 ~(FTGMAC100_MACCR_GIGA_MODE |
199 FTGMAC100_MACCR_FAST_MODE |
200 FTGMAC100_MACCR_FULLDUP);
202 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
203 maccr |= FTGMAC100_MACCR_GIGA_MODE;
205 if (phydev->speed == 100)
206 maccr |= FTGMAC100_MACCR_FAST_MODE;
209 maccr |= FTGMAC100_MACCR_FULLDUP;
211 /* update MII config into maccr */
212 writel(maccr, &ftgmac100->maccr);
217 static int ftgmac100_phy_init(struct udevice *dev)
219 struct ftgmac100_data *priv = dev_get_priv(dev);
220 struct phy_device *phydev;
223 if (IS_ENABLED(CONFIG_DM_MDIO))
224 phydev = dm_eth_phy_connect(dev);
226 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
231 phydev->supported &= PHY_GBIT_FEATURES;
232 if (priv->max_speed) {
233 ret = phy_set_supported(phydev, priv->max_speed);
237 phydev->advertising = phydev->supported;
238 priv->phydev = phydev;
247 static void ftgmac100_reset(struct ftgmac100_data *priv)
249 struct ftgmac100 *ftgmac100 = priv->iobase;
251 debug("%s()\n", __func__);
253 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
255 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
262 static int ftgmac100_set_mac(struct ftgmac100_data *priv,
263 const unsigned char *mac)
265 struct ftgmac100 *ftgmac100 = priv->iobase;
266 unsigned int maddr = mac[0] << 8 | mac[1];
267 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
269 debug("%s(%x %x)\n", __func__, maddr, laddr);
271 writel(maddr, &ftgmac100->mac_madr);
272 writel(laddr, &ftgmac100->mac_ladr);
280 static int ftgmac100_get_mac(struct ftgmac100_data *priv,
283 struct ftgmac100 *ftgmac100 = priv->iobase;
284 unsigned int maddr = readl(&ftgmac100->mac_madr);
285 unsigned int laddr = readl(&ftgmac100->mac_ladr);
287 debug("%s(%x %x)\n", __func__, maddr, laddr);
289 mac[0] = (maddr >> 8) & 0xff;
290 mac[1] = maddr & 0xff;
291 mac[2] = (laddr >> 24) & 0xff;
292 mac[3] = (laddr >> 16) & 0xff;
293 mac[4] = (laddr >> 8) & 0xff;
294 mac[5] = laddr & 0xff;
300 * disable transmitter, receiver
302 static void ftgmac100_stop(struct udevice *dev)
304 struct ftgmac100_data *priv = dev_get_priv(dev);
305 struct ftgmac100 *ftgmac100 = priv->iobase;
307 debug("%s()\n", __func__);
309 writel(0, &ftgmac100->maccr);
311 phy_shutdown(priv->phydev);
314 static int ftgmac100_start(struct udevice *dev)
316 struct eth_pdata *plat = dev_get_plat(dev);
317 struct ftgmac100_data *priv = dev_get_priv(dev);
318 struct ftgmac100 *ftgmac100 = priv->iobase;
319 struct phy_device *phydev = priv->phydev;
325 debug("%s()\n", __func__);
327 ftgmac100_reset(priv);
329 /* set the ethernet address */
330 ftgmac100_set_mac(priv, plat->enetaddr);
332 /* disable all interrupts */
333 writel(0, &ftgmac100->ier);
335 /* initialize descriptors */
339 for (i = 0; i < PKTBUFSTX; i++) {
340 priv->txdes[i].txdes3 = 0;
341 priv->txdes[i].txdes0 = 0;
343 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
345 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
346 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
347 flush_dcache_range(start, end);
349 for (i = 0; i < PKTBUFSRX; i++) {
350 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
351 priv->rxdes[i].rxdes0 = 0;
353 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
355 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
356 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
357 flush_dcache_range(start, end);
360 writel((u32)priv->txdes, &ftgmac100->txr_badr);
363 writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
365 /* poll receive descriptor automatically */
366 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
368 /* config receive buffer size register */
369 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
371 /* enable transmitter, receiver */
372 maccr = FTGMAC100_MACCR_TXMAC_EN |
373 FTGMAC100_MACCR_RXMAC_EN |
374 FTGMAC100_MACCR_TXDMA_EN |
375 FTGMAC100_MACCR_RXDMA_EN |
376 FTGMAC100_MACCR_CRC_APD |
377 FTGMAC100_MACCR_FULLDUP |
378 FTGMAC100_MACCR_RX_RUNT |
379 FTGMAC100_MACCR_RX_BROADPKT;
381 writel(maccr, &ftgmac100->maccr);
383 ret = phy_startup(phydev);
385 dev_err(phydev->dev, "Could not start PHY\n");
389 ret = ftgmac100_phy_adjust_link(priv);
391 dev_err(phydev->dev, "Could not adjust link\n");
395 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
396 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
401 static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
403 struct ftgmac100_data *priv = dev_get_priv(dev);
404 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
405 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
406 ulong des_end = des_start +
407 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
409 /* Release buffer to DMA and flush descriptor */
410 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
411 flush_dcache_range(des_start, des_end);
413 /* Move to next descriptor */
414 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
420 * Get a data block via Ethernet
422 static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
424 struct ftgmac100_data *priv = dev_get_priv(dev);
425 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
426 unsigned short rxlen;
427 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
428 ulong des_end = des_start +
429 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
430 ulong data_start = curr_des->rxdes3;
433 invalidate_dcache_range(des_start, des_end);
435 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
438 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
439 FTGMAC100_RXDES0_CRC_ERR |
440 FTGMAC100_RXDES0_FTL |
441 FTGMAC100_RXDES0_RUNT |
442 FTGMAC100_RXDES0_RX_ODD_NB)) {
446 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
448 debug("%s(): RX buffer %d, %x received\n",
449 __func__, priv->rx_index, rxlen);
451 /* Invalidate received data */
452 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
453 invalidate_dcache_range(data_start, data_end);
454 *packetp = (uchar *)data_start;
459 static u32 ftgmac100_read_txdesc(const void *desc)
461 const struct ftgmac100_txdes *txdes = desc;
462 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
463 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
465 invalidate_dcache_range(des_start, des_end);
467 return txdes->txdes0;
470 BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
473 * Send a data block via Ethernet
475 static int ftgmac100_send(struct udevice *dev, void *packet, int length)
477 struct ftgmac100_data *priv = dev_get_priv(dev);
478 struct ftgmac100 *ftgmac100 = priv->iobase;
479 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
480 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
481 ulong des_end = des_start +
482 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
487 invalidate_dcache_range(des_start, des_end);
489 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
490 dev_err(dev, "no TX descriptor available\n");
494 debug("%s(%x, %x)\n", __func__, (int)packet, length);
496 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
498 curr_des->txdes3 = (unsigned int)packet;
500 /* Flush data to be sent */
501 data_start = curr_des->txdes3;
502 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
503 flush_dcache_range(data_start, data_end);
505 /* Only one segment on TXBUF */
506 curr_des->txdes0 &= priv->txdes0_edotr_mask;
507 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
508 FTGMAC100_TXDES0_LTS |
509 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
510 FTGMAC100_TXDES0_TXDMA_OWN ;
512 /* Flush modified buffer descriptor */
513 flush_dcache_range(des_start, des_end);
516 writel(1, &ftgmac100->txpd);
518 rc = wait_for_bit_ftgmac100_txdone(curr_des,
519 FTGMAC100_TXDES0_TXDMA_OWN, false,
520 FTGMAC100_TX_TIMEOUT_MS, true);
524 debug("%s(): packet sent\n", __func__);
526 /* Move to next descriptor */
527 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
532 static int ftgmac100_write_hwaddr(struct udevice *dev)
534 struct eth_pdata *pdata = dev_get_plat(dev);
535 struct ftgmac100_data *priv = dev_get_priv(dev);
537 return ftgmac100_set_mac(priv, pdata->enetaddr);
540 static int ftgmac_read_hwaddr(struct udevice *dev)
542 struct eth_pdata *pdata = dev_get_plat(dev);
543 struct ftgmac100_data *priv = dev_get_priv(dev);
545 return ftgmac100_get_mac(priv, pdata->enetaddr);
548 static int ftgmac100_of_to_plat(struct udevice *dev)
550 struct eth_pdata *pdata = dev_get_plat(dev);
551 struct ftgmac100_data *priv = dev_get_priv(dev);
553 pdata->iobase = dev_read_addr(dev);
555 pdata->phy_interface = dev_read_phy_mode(dev);
556 if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
559 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
561 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
562 priv->rxdes0_edorr_mask = BIT(30);
563 priv->txdes0_edotr_mask = BIT(30);
565 priv->rxdes0_edorr_mask = BIT(15);
566 priv->txdes0_edotr_mask = BIT(15);
569 return clk_get_bulk(dev, &priv->clks);
572 static int ftgmac100_probe(struct udevice *dev)
574 struct eth_pdata *pdata = dev_get_plat(dev);
575 struct ftgmac100_data *priv = dev_get_priv(dev);
578 priv->iobase = (struct ftgmac100 *)pdata->iobase;
579 priv->phy_mode = pdata->phy_interface;
580 priv->max_speed = pdata->max_speed;
583 #ifdef CONFIG_PHY_ADDR
584 priv->phy_addr = CONFIG_PHY_ADDR;
587 ret = clk_enable_bulk(&priv->clks);
592 * If DM MDIO is enabled, the MDIO bus will be initialized later in
595 if (!IS_ENABLED(CONFIG_DM_MDIO)) {
596 ret = ftgmac100_mdio_init(dev);
598 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
603 ret = ftgmac100_phy_init(dev);
605 dev_err(dev, "Failed to initialize PHY: %d\n", ret);
609 ftgmac_read_hwaddr(dev);
613 clk_release_bulk(&priv->clks);
618 static int ftgmac100_remove(struct udevice *dev)
620 struct ftgmac100_data *priv = dev_get_priv(dev);
623 mdio_unregister(priv->bus);
624 mdio_free(priv->bus);
625 clk_release_bulk(&priv->clks);
630 static const struct eth_ops ftgmac100_ops = {
631 .start = ftgmac100_start,
632 .send = ftgmac100_send,
633 .recv = ftgmac100_recv,
634 .stop = ftgmac100_stop,
635 .free_pkt = ftgmac100_free_pkt,
636 .write_hwaddr = ftgmac100_write_hwaddr,
639 static const struct udevice_id ftgmac100_ids[] = {
640 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
641 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
642 { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
646 U_BOOT_DRIVER(ftgmac100) = {
649 .of_match = ftgmac100_ids,
650 .of_to_plat = ftgmac100_of_to_plat,
651 .probe = ftgmac100_probe,
652 .remove = ftgmac100_remove,
653 .ops = &ftgmac100_ops,
654 .priv_auto = sizeof(struct ftgmac100_data),
655 .plat_auto = sizeof(struct eth_pdata),
656 .flags = DM_FLAG_ALLOC_PRIV_DMA,