1 // SPDX-License-Identifier: GPL-2.0+
3 * Faraday FTGMAC100 Ethernet
5 * (C) Copyright 2009 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
8 * (C) Copyright 2010 Andes Technology
9 * Macpaul Lin <macpaul@andestech.com>
11 * Copyright (C) 2018, IBM Corporation.
23 #include <asm/cache.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
27 #include <linux/iopoll.h>
29 #include "ftgmac100.h"
31 /* Min frame ethernet frame size without FCS */
34 /* Receive Buffer Size Register - HW default is 0x640 */
35 #define FTGMAC100_RBSR_DEFAULT 0x640
37 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
38 #define PKTBUFSTX 4 /* must be power of 2 */
40 /* Timeout for transmit */
41 #define FTGMAC100_TX_TIMEOUT_MS 1000
43 /* Timeout for a mdio read/write operation */
44 #define FTGMAC100_MDIO_TIMEOUT_USEC 10000
47 * MDC clock cycle threshold
49 * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
51 #define MDC_CYCTHR 0x34
54 * ftgmac100 model variants
56 enum ftgmac100_model {
57 FTGMAC100_MODEL_FARADAY,
58 FTGMAC100_MODEL_ASPEED,
62 * struct ftgmac100_data - private data for the FTGMAC100 driver
64 * @iobase: The base address of the hardware registers
65 * @txdes: The array of transmit descriptors
66 * @rxdes: The array of receive descriptors
67 * @tx_index: Transmit descriptor index in @txdes
68 * @rx_index: Receive descriptor index in @rxdes
69 * @phy_addr: The PHY interface address to use
70 * @phydev: The PHY device backing the MAC
72 * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
73 * @max_speed: Maximum speed of Ethernet connection supported by MAC
74 * @clks: The bulk of clocks assigned to the device in the DT
75 * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
76 * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
78 struct ftgmac100_data {
79 struct ftgmac100 *iobase;
81 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
82 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
87 struct phy_device *phydev;
94 /* End of RX/TX ring buffer bits. Depend on model */
95 u32 rxdes0_edorr_mask;
96 u32 txdes0_edotr_mask;
100 * struct mii_bus functions
102 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
105 struct ftgmac100_data *priv = bus->priv;
106 struct ftgmac100 *ftgmac100 = priv->iobase;
111 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
112 FTGMAC100_PHYCR_PHYAD(phy_addr) |
113 FTGMAC100_PHYCR_REGAD(reg_addr) |
114 FTGMAC100_PHYCR_MIIRD;
115 writel(phycr, &ftgmac100->phycr);
117 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
118 !(phycr & FTGMAC100_PHYCR_MIIRD),
119 FTGMAC100_MDIO_TIMEOUT_USEC);
121 pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
122 priv->phydev->dev->name, phy_addr, reg_addr);
126 data = readl(&ftgmac100->phydata);
128 return FTGMAC100_PHYDATA_MIIRDATA(data);
131 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
132 int reg_addr, u16 value)
134 struct ftgmac100_data *priv = bus->priv;
135 struct ftgmac100 *ftgmac100 = priv->iobase;
140 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
141 FTGMAC100_PHYCR_PHYAD(phy_addr) |
142 FTGMAC100_PHYCR_REGAD(reg_addr) |
143 FTGMAC100_PHYCR_MIIWR;
144 data = FTGMAC100_PHYDATA_MIIWDATA(value);
146 writel(data, &ftgmac100->phydata);
147 writel(phycr, &ftgmac100->phycr);
149 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
150 !(phycr & FTGMAC100_PHYCR_MIIWR),
151 FTGMAC100_MDIO_TIMEOUT_USEC);
153 pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
154 priv->phydev->dev->name, phy_addr, reg_addr);
160 static int ftgmac100_mdio_init(struct udevice *dev)
162 struct ftgmac100_data *priv = dev_get_priv(dev);
170 bus->read = ftgmac100_mdio_read;
171 bus->write = ftgmac100_mdio_write;
174 ret = mdio_register_seq(bus, dev->seq);
185 static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
187 struct ftgmac100 *ftgmac100 = priv->iobase;
188 struct phy_device *phydev = priv->phydev;
192 dev_err(phydev->dev, "No link\n");
196 /* read MAC control register and clear related bits */
197 maccr = readl(&ftgmac100->maccr) &
198 ~(FTGMAC100_MACCR_GIGA_MODE |
199 FTGMAC100_MACCR_FAST_MODE |
200 FTGMAC100_MACCR_FULLDUP);
202 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
203 maccr |= FTGMAC100_MACCR_GIGA_MODE;
205 if (phydev->speed == 100)
206 maccr |= FTGMAC100_MACCR_FAST_MODE;
209 maccr |= FTGMAC100_MACCR_FULLDUP;
211 /* update MII config into maccr */
212 writel(maccr, &ftgmac100->maccr);
217 static int ftgmac100_phy_init(struct udevice *dev)
219 struct ftgmac100_data *priv = dev_get_priv(dev);
220 struct phy_device *phydev;
223 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
227 phydev->supported &= PHY_GBIT_FEATURES;
228 if (priv->max_speed) {
229 ret = phy_set_supported(phydev, priv->max_speed);
233 phydev->advertising = phydev->supported;
234 priv->phydev = phydev;
243 static void ftgmac100_reset(struct ftgmac100_data *priv)
245 struct ftgmac100 *ftgmac100 = priv->iobase;
247 debug("%s()\n", __func__);
249 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
251 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
258 static int ftgmac100_set_mac(struct ftgmac100_data *priv,
259 const unsigned char *mac)
261 struct ftgmac100 *ftgmac100 = priv->iobase;
262 unsigned int maddr = mac[0] << 8 | mac[1];
263 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
265 debug("%s(%x %x)\n", __func__, maddr, laddr);
267 writel(maddr, &ftgmac100->mac_madr);
268 writel(laddr, &ftgmac100->mac_ladr);
274 * disable transmitter, receiver
276 static void ftgmac100_stop(struct udevice *dev)
278 struct ftgmac100_data *priv = dev_get_priv(dev);
279 struct ftgmac100 *ftgmac100 = priv->iobase;
281 debug("%s()\n", __func__);
283 writel(0, &ftgmac100->maccr);
285 phy_shutdown(priv->phydev);
288 static int ftgmac100_start(struct udevice *dev)
290 struct eth_pdata *plat = dev_get_platdata(dev);
291 struct ftgmac100_data *priv = dev_get_priv(dev);
292 struct ftgmac100 *ftgmac100 = priv->iobase;
293 struct phy_device *phydev = priv->phydev;
299 debug("%s()\n", __func__);
301 ftgmac100_reset(priv);
303 /* set the ethernet address */
304 ftgmac100_set_mac(priv, plat->enetaddr);
306 /* disable all interrupts */
307 writel(0, &ftgmac100->ier);
309 /* initialize descriptors */
313 for (i = 0; i < PKTBUFSTX; i++) {
314 priv->txdes[i].txdes3 = 0;
315 priv->txdes[i].txdes0 = 0;
317 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
319 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
320 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
321 flush_dcache_range(start, end);
323 for (i = 0; i < PKTBUFSRX; i++) {
324 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
325 priv->rxdes[i].rxdes0 = 0;
327 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
329 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
330 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
331 flush_dcache_range(start, end);
334 writel((u32)priv->txdes, &ftgmac100->txr_badr);
337 writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
339 /* poll receive descriptor automatically */
340 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
342 /* config receive buffer size register */
343 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
345 /* enable transmitter, receiver */
346 maccr = FTGMAC100_MACCR_TXMAC_EN |
347 FTGMAC100_MACCR_RXMAC_EN |
348 FTGMAC100_MACCR_TXDMA_EN |
349 FTGMAC100_MACCR_RXDMA_EN |
350 FTGMAC100_MACCR_CRC_APD |
351 FTGMAC100_MACCR_FULLDUP |
352 FTGMAC100_MACCR_RX_RUNT |
353 FTGMAC100_MACCR_RX_BROADPKT;
355 writel(maccr, &ftgmac100->maccr);
357 ret = phy_startup(phydev);
359 dev_err(phydev->dev, "Could not start PHY\n");
363 ret = ftgmac100_phy_adjust_link(priv);
365 dev_err(phydev->dev, "Could not adjust link\n");
369 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
370 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
375 static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
377 struct ftgmac100_data *priv = dev_get_priv(dev);
378 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
379 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
380 ulong des_end = des_start +
381 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
383 /* Release buffer to DMA and flush descriptor */
384 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
385 flush_dcache_range(des_start, des_end);
387 /* Move to next descriptor */
388 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
394 * Get a data block via Ethernet
396 static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
398 struct ftgmac100_data *priv = dev_get_priv(dev);
399 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
400 unsigned short rxlen;
401 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
402 ulong des_end = des_start +
403 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
404 ulong data_start = curr_des->rxdes3;
407 invalidate_dcache_range(des_start, des_end);
409 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
412 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
413 FTGMAC100_RXDES0_CRC_ERR |
414 FTGMAC100_RXDES0_FTL |
415 FTGMAC100_RXDES0_RUNT |
416 FTGMAC100_RXDES0_RX_ODD_NB)) {
420 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
422 debug("%s(): RX buffer %d, %x received\n",
423 __func__, priv->rx_index, rxlen);
425 /* Invalidate received data */
426 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
427 invalidate_dcache_range(data_start, data_end);
428 *packetp = (uchar *)data_start;
433 static u32 ftgmac100_read_txdesc(const void *desc)
435 const struct ftgmac100_txdes *txdes = desc;
436 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
437 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
439 invalidate_dcache_range(des_start, des_end);
441 return txdes->txdes0;
444 BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
447 * Send a data block via Ethernet
449 static int ftgmac100_send(struct udevice *dev, void *packet, int length)
451 struct ftgmac100_data *priv = dev_get_priv(dev);
452 struct ftgmac100 *ftgmac100 = priv->iobase;
453 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
454 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
455 ulong des_end = des_start +
456 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
461 invalidate_dcache_range(des_start, des_end);
463 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
464 dev_err(dev, "no TX descriptor available\n");
468 debug("%s(%x, %x)\n", __func__, (int)packet, length);
470 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
472 curr_des->txdes3 = (unsigned int)packet;
474 /* Flush data to be sent */
475 data_start = curr_des->txdes3;
476 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
477 flush_dcache_range(data_start, data_end);
479 /* Only one segment on TXBUF */
480 curr_des->txdes0 &= priv->txdes0_edotr_mask;
481 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
482 FTGMAC100_TXDES0_LTS |
483 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
484 FTGMAC100_TXDES0_TXDMA_OWN ;
486 /* Flush modified buffer descriptor */
487 flush_dcache_range(des_start, des_end);
490 writel(1, &ftgmac100->txpd);
492 rc = wait_for_bit_ftgmac100_txdone(curr_des,
493 FTGMAC100_TXDES0_TXDMA_OWN, false,
494 FTGMAC100_TX_TIMEOUT_MS, true);
498 debug("%s(): packet sent\n", __func__);
500 /* Move to next descriptor */
501 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
506 static int ftgmac100_write_hwaddr(struct udevice *dev)
508 struct eth_pdata *pdata = dev_get_platdata(dev);
509 struct ftgmac100_data *priv = dev_get_priv(dev);
511 return ftgmac100_set_mac(priv, pdata->enetaddr);
514 static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
516 struct eth_pdata *pdata = dev_get_platdata(dev);
517 struct ftgmac100_data *priv = dev_get_priv(dev);
518 const char *phy_mode;
520 pdata->iobase = dev_read_addr(dev);
521 pdata->phy_interface = -1;
522 phy_mode = dev_read_string(dev, "phy-mode");
524 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
525 if (pdata->phy_interface == -1) {
526 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
530 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
532 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
533 priv->rxdes0_edorr_mask = BIT(30);
534 priv->txdes0_edotr_mask = BIT(30);
536 priv->rxdes0_edorr_mask = BIT(15);
537 priv->txdes0_edotr_mask = BIT(15);
540 return clk_get_bulk(dev, &priv->clks);
543 static int ftgmac100_probe(struct udevice *dev)
545 struct eth_pdata *pdata = dev_get_platdata(dev);
546 struct ftgmac100_data *priv = dev_get_priv(dev);
549 priv->iobase = (struct ftgmac100 *)pdata->iobase;
550 priv->phy_mode = pdata->phy_interface;
551 priv->max_speed = pdata->max_speed;
554 #ifdef CONFIG_PHY_ADDR
555 priv->phy_addr = CONFIG_PHY_ADDR;
558 ret = clk_enable_bulk(&priv->clks);
562 ret = ftgmac100_mdio_init(dev);
564 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
568 ret = ftgmac100_phy_init(dev);
570 dev_err(dev, "Failed to initialize PHY: %d\n", ret);
576 clk_release_bulk(&priv->clks);
581 static int ftgmac100_remove(struct udevice *dev)
583 struct ftgmac100_data *priv = dev_get_priv(dev);
586 mdio_unregister(priv->bus);
587 mdio_free(priv->bus);
588 clk_release_bulk(&priv->clks);
593 static const struct eth_ops ftgmac100_ops = {
594 .start = ftgmac100_start,
595 .send = ftgmac100_send,
596 .recv = ftgmac100_recv,
597 .stop = ftgmac100_stop,
598 .free_pkt = ftgmac100_free_pkt,
599 .write_hwaddr = ftgmac100_write_hwaddr,
602 static const struct udevice_id ftgmac100_ids[] = {
603 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
604 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
608 U_BOOT_DRIVER(ftgmac100) = {
611 .of_match = ftgmac100_ids,
612 .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
613 .probe = ftgmac100_probe,
614 .remove = ftgmac100_remove,
615 .ops = &ftgmac100_ops,
616 .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
617 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
618 .flags = DM_FLAG_ALLOC_PRIV_DMA,