1 // SPDX-License-Identifier: GPL-2.0+
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
15 #include "fsl_enetc.h"
19 * - set a more explicit name on the interface
21 static int enetc_bind(struct udevice *dev)
24 static int eth_num_devices;
27 * prefer using PCI function numbers to number interfaces, but these
28 * are only available if dts nodes are present. For PCI they are
29 * optional, handle that case too. Just in case some nodes are present
30 * and some are not, use different naming scheme - enetc-N based on
31 * PCI function # and enetc#N based on interface count
33 if (ofnode_valid(dev->node))
34 sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
36 sprintf(name, "enetc#%u", eth_num_devices++);
37 device_set_name(dev, name);
42 /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
43 static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
45 struct enetc_mdio_priv priv;
47 priv.regs_base = bus->priv;
48 return enetc_mdio_read_priv(&priv, addr, devad, reg);
51 static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
54 struct enetc_mdio_priv priv;
56 priv.regs_base = bus->priv;
57 return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
60 /* only interfaces that can pin out through serdes have internal MDIO */
61 static bool enetc_has_imdio(struct udevice *dev)
63 struct enetc_priv *priv = dev_get_priv(dev);
65 return !!(priv->imdio.priv);
68 /* set up serdes for SGMII */
69 static int enetc_init_sgmii(struct udevice *dev)
71 struct enetc_priv *priv = dev_get_priv(dev);
75 if (!enetc_has_imdio(dev))
78 if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
82 * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
83 * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
84 * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
87 reg = ENETC_PCS_IF_MODE_SGMII;
88 reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
89 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
90 ENETC_PCS_IF_MODE, reg);
92 /* Dev ability - SGMII */
93 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
94 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
96 /* Adjust link timer for SGMII */
97 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
98 ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
99 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
100 ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
102 reg = ENETC_PCS_CR_DEF_VAL;
103 reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
105 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
111 /* set up MAC for RGMII */
112 static int enetc_init_rgmii(struct udevice *dev)
114 struct enetc_priv *priv = dev_get_priv(dev);
117 /* enable RGMII AN */
118 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
119 if_mode |= ENETC_PM_IF_MODE_AN_ENA;
120 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
125 /* set up MAC and serdes for SXGMII */
126 static int enetc_init_sxgmii(struct udevice *dev)
128 struct enetc_priv *priv = dev_get_priv(dev);
131 /* set ifmode to (US)XGMII */
132 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
133 if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
134 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
136 if (!enetc_has_imdio(dev))
139 /* Dev ability - SXGMII */
140 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
141 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
144 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
146 ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
151 /* Apply protocol specific configuration to MAC, serdes as needed */
152 static void enetc_start_pcs(struct udevice *dev)
154 struct enetc_priv *priv = dev_get_priv(dev);
157 priv->if_type = PHY_INTERFACE_MODE_NONE;
159 /* check internal mdio capability, not all ports need it */
160 if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
162 * set up internal MDIO, this is part of ETH PCI function and is
163 * used to access serdes / internal SoC PHYs.
164 * We don't currently register it as a MDIO bus as it goes away
165 * when the interface is removed, so it can't practically be
166 * used in the console.
168 priv->imdio.read = enetc_mdio_read;
169 priv->imdio.write = enetc_mdio_write;
170 priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
171 strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
174 if (!ofnode_valid(dev->node)) {
175 enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
179 if_str = ofnode_read_string(dev->node, "phy-mode");
181 priv->if_type = phy_get_interface_by_name(if_str);
184 "phy-mode property not found, defaulting to SGMII\n");
185 if (priv->if_type < 0)
186 priv->if_type = PHY_INTERFACE_MODE_NONE;
188 switch (priv->if_type) {
189 case PHY_INTERFACE_MODE_SGMII:
190 case PHY_INTERFACE_MODE_SGMII_2500:
191 enetc_init_sgmii(dev);
193 case PHY_INTERFACE_MODE_RGMII:
194 case PHY_INTERFACE_MODE_RGMII_ID:
195 case PHY_INTERFACE_MODE_RGMII_RXID:
196 case PHY_INTERFACE_MODE_RGMII_TXID:
197 enetc_init_rgmii(dev);
199 case PHY_INTERFACE_MODE_XGMII:
200 case PHY_INTERFACE_MODE_USXGMII:
201 case PHY_INTERFACE_MODE_XFI:
202 enetc_init_sxgmii(dev);
207 /* Configure the actual/external ethernet PHY, if one is found */
208 static void enetc_config_phy(struct udevice *dev)
210 struct enetc_priv *priv = dev_get_priv(dev);
213 priv->phy = dm_eth_phy_connect(dev);
218 supported = GENMASK(6, 0); /* speeds up to 1G & AN */
219 priv->phy->advertising = priv->phy->supported & supported;
221 phy_config(priv->phy);
225 * Probe ENETC driver:
226 * - initialize port and station interface BARs
228 static int enetc_probe(struct udevice *dev)
230 struct enetc_priv *priv = dev_get_priv(dev);
232 if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
233 enetc_dbg(dev, "interface disabled\n");
237 priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
238 sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
239 priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
240 sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
242 if (!priv->enetc_txbd || !priv->enetc_rxbd) {
243 /* free should be able to handle NULL, just free all pointers */
244 free(priv->enetc_txbd);
245 free(priv->enetc_rxbd);
250 /* initialize register */
251 priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
252 if (!priv->regs_base) {
253 enetc_dbg(dev, "failed to map BAR0\n");
256 priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
258 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
264 * Remove the driver from an interface:
265 * - free up allocated memory
267 static int enetc_remove(struct udevice *dev)
269 struct enetc_priv *priv = dev_get_priv(dev);
271 free(priv->enetc_txbd);
272 free(priv->enetc_rxbd);
277 /* ENETC Port MAC address registers, accepts big-endian format */
278 static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
280 u16 lower = *(const u16 *)(addr + 4);
281 u32 upper = *(const u32 *)addr;
283 enetc_write_port(priv, ENETC_PSIPMAR0, upper);
284 enetc_write_port(priv, ENETC_PSIPMAR1, lower);
287 /* Configure port parameters (# of rings, frame size, enable port) */
288 static void enetc_enable_si_port(struct enetc_priv *priv)
292 /* set Rx/Tx BDR count */
293 val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
294 val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
295 enetc_write_port(priv, ENETC_PSICFGR(0), val);
296 /* set Rx max frame size */
297 enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
298 /* enable MAC port */
299 enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
301 enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
302 /* set SI cache policy */
303 enetc_write(priv, ENETC_SICAR0,
304 ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
306 enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
309 /* returns DMA address for a given buffer index */
310 static inline u64 enetc_rxb_address(struct udevice *dev, int i)
312 return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
316 * Setup a single Tx BD Ring (ID = 0):
317 * - set Tx buffer descriptor address
319 * - initialize the producer and consumer index
321 static void enetc_setup_tx_bdr(struct udevice *dev)
323 struct enetc_priv *priv = dev_get_priv(dev);
324 struct bd_ring *tx_bdr = &priv->tx_bdr;
325 u64 tx_bd_add = (u64)priv->enetc_txbd;
327 /* used later to advance to the next Tx BD */
328 tx_bdr->bd_count = ENETC_BD_CNT;
329 tx_bdr->next_prod_idx = 0;
330 tx_bdr->next_cons_idx = 0;
331 tx_bdr->cons_idx = priv->regs_base +
332 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
333 tx_bdr->prod_idx = priv->regs_base +
334 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
336 /* set Tx BD address */
337 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
338 lower_32_bits(tx_bd_add));
339 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
340 upper_32_bits(tx_bd_add));
341 /* set Tx 8 BD count */
342 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
345 /* reset both producer/consumer indexes */
346 enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
347 enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
350 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
354 * Setup a single Rx BD Ring (ID = 0):
355 * - set Rx buffer descriptors address (one descriptor per buffer)
356 * - set buffer size as max frame size
358 * - reset consumer and producer indexes
359 * - set buffer for each descriptor
361 static void enetc_setup_rx_bdr(struct udevice *dev)
363 struct enetc_priv *priv = dev_get_priv(dev);
364 struct bd_ring *rx_bdr = &priv->rx_bdr;
365 u64 rx_bd_add = (u64)priv->enetc_rxbd;
368 /* used later to advance to the next BD produced by ENETC HW */
369 rx_bdr->bd_count = ENETC_BD_CNT;
370 rx_bdr->next_prod_idx = 0;
371 rx_bdr->next_cons_idx = 0;
372 rx_bdr->cons_idx = priv->regs_base +
373 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
374 rx_bdr->prod_idx = priv->regs_base +
375 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
377 /* set Rx BD address */
378 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
379 lower_32_bits(rx_bd_add));
380 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
381 upper_32_bits(rx_bd_add));
382 /* set Rx BD count (multiple of 8) */
383 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
385 /* set Rx buffer size */
386 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
389 memset(priv->enetc_rxbd, 0,
390 rx_bdr->bd_count * sizeof(union enetc_rx_bd));
391 for (i = 0; i < rx_bdr->bd_count; i++) {
392 priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
393 /* each RX buffer must be aligned to 64B */
394 WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
397 /* reset producer (ENETC owned) and consumer (SW owned) index */
398 enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
399 enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
402 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
406 * Start ENETC interface:
408 * - enable access to port and SI registers
410 * - setup TX/RX buffer descriptors
411 * - enable Tx/Rx rings
413 static int enetc_start(struct udevice *dev)
415 struct eth_pdata *plat = dev_get_platdata(dev);
416 struct enetc_priv *priv = dev_get_priv(dev);
418 /* reset and enable the PCI device */
420 dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
421 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
423 if (!is_valid_ethaddr(plat->enetaddr)) {
424 enetc_dbg(dev, "invalid MAC address, generate random ...\n");
425 net_random_ethaddr(plat->enetaddr);
427 enetc_set_primary_mac_addr(priv, plat->enetaddr);
429 enetc_enable_si_port(priv);
431 /* setup Tx/Rx buffer descriptors */
432 enetc_setup_tx_bdr(dev);
433 enetc_setup_rx_bdr(dev);
435 enetc_start_pcs(dev);
436 enetc_config_phy(dev);
438 phy_startup(priv->phy);
444 * Stop the network interface:
445 * - just quiesce it, we can wipe all configuration as _start starts from
448 static void enetc_stop(struct udevice *dev)
450 /* FLR is sufficient to quiesce the device */
455 * ENETC transmit packet:
456 * - check if Tx BD ring is full
457 * - set buffer/packet address (dma address)
458 * - set final fragment flag
459 * - try while producer index equals consumer index or timeout
461 static int enetc_send(struct udevice *dev, void *packet, int length)
463 struct enetc_priv *priv = dev_get_priv(dev);
464 struct bd_ring *txr = &priv->tx_bdr;
465 void *nv_packet = (void *)packet;
466 int tries = ENETC_POLL_TRIES;
469 pi = txr->next_prod_idx;
470 ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
471 /* Tx ring is full when */
472 if (((pi + 1) % txr->bd_count) == ci) {
473 enetc_dbg(dev, "Tx BDR full\n");
476 enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
477 upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
480 memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
481 priv->enetc_txbd[pi].addr =
482 cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
483 priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
484 priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
485 priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
487 /* send frame: increment producer index */
488 pi = (pi + 1) % txr->bd_count;
489 txr->next_prod_idx = pi;
490 enetc_write_reg(txr->prod_idx, pi);
491 while ((--tries >= 0) &&
492 (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
495 return tries > 0 ? 0 : -ETIMEDOUT;
500 * - wait for the next BD to get ready bit set
501 * - clean up the descriptor
502 * - move on and indicate to HW that the cleaned BD is available for Rx
504 static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
506 struct enetc_priv *priv = dev_get_priv(dev);
507 struct bd_ring *rxr = &priv->rx_bdr;
508 int tries = ENETC_POLL_TRIES;
509 int pi = rxr->next_prod_idx;
510 int ci = rxr->next_cons_idx;
517 status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
518 /* check if current BD is ready to be consumed */
519 rdy = ENETC_RXBD_STATUS_R(status);
520 } while (--tries >= 0 && !rdy);
526 len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
527 *packetp = (uchar *)enetc_rxb_address(dev, pi);
528 enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
529 ENETC_RXBD_STATUS_ERRORS(status),
530 upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
532 /* BD clean up and advance to next in ring */
533 memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
534 priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
535 rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
536 ci = (ci + 1) % rxr->bd_count;
537 rxr->next_cons_idx = ci;
539 /* free up the slot in the ring for HW */
540 enetc_write_reg(rxr->cons_idx, ci);
545 static const struct eth_ops enetc_ops = {
546 .start = enetc_start,
552 U_BOOT_DRIVER(eth_enetc) = {
556 .probe = enetc_probe,
557 .remove = enetc_remove,
559 .priv_auto_alloc_size = sizeof(struct enetc_priv),
560 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
563 static struct pci_device_id enetc_ids[] = {
564 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
568 U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);