2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_serdes.h>
15 u32 port_to_devdisr[] = {
16 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
17 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
18 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
19 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
20 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
21 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
22 [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
23 [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
24 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
25 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
26 [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
27 [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
30 static int is_device_disabled(enum fm_port port)
32 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 u32 devdisr2 = in_be32(&gur->devdisr2);
35 return port_to_devdisr[port] & devdisr2;
38 void fman_disable_port(enum fm_port port)
40 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
42 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
45 phy_interface_t fman_port_enet_if(enum fm_port port)
47 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
50 if (is_device_disabled(port))
51 return PHY_INTERFACE_MODE_NONE;
53 if ((port == FM1_10GEC1 || port == FM1_10GEC2 ||
54 port == FM1_10GEC3 || port == FM1_10GEC4) &&
55 ((is_serdes_configured(XAUI_FM1_MAC9)) ||
56 (is_serdes_configured(XFI_FM1_MAC1)) ||
57 (is_serdes_configured(XFI_FM1_MAC2)) ||
58 (is_serdes_configured(XFI_FM1_MAC9)) ||
59 (is_serdes_configured(XFI_FM1_MAC10))))
60 return PHY_INTERFACE_MODE_XGMII;
62 if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
63 FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
64 return PHY_INTERFACE_MODE_RGMII;
66 if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
67 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
68 return PHY_INTERFACE_MODE_RGMII;
70 if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
71 FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
72 return PHY_INTERFACE_MODE_RGMII;
83 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
84 return PHY_INTERFACE_MODE_SGMII;
87 return PHY_INTERFACE_MODE_NONE;
90 return PHY_INTERFACE_MODE_NONE;